1 /* 2 * DM81xx hwmod data. 3 * 4 * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/ 5 * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/ 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation version 2. 10 * 11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 12 * kind, whether express or implied; without even the implied warranty 13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 */ 17 18 #include <linux/types.h> 19 20 #include <linux/platform_data/hsmmc-omap.h> 21 22 #include "omap_hwmod_common_data.h" 23 #include "cm81xx.h" 24 #include "ti81xx.h" 25 #include "wd_timer.h" 26 27 /* 28 * DM816X hardware modules integration data 29 * 30 * Note: This is incomplete and at present, not generated from h/w database. 31 */ 32 33 /* 34 * Common alwon .clkctrl_offs from dm814x TRM "Table 2-278. CM_ALWON REGISTERS" 35 * also dm816x TRM 18.7.17 CM_ALWON device register values minus 0x1400. 36 */ 37 #define DM81XX_CM_ALWON_MCASP0_CLKCTRL 0x140 38 #define DM81XX_CM_ALWON_MCASP1_CLKCTRL 0x144 39 #define DM81XX_CM_ALWON_MCASP2_CLKCTRL 0x148 40 #define DM81XX_CM_ALWON_MCBSP_CLKCTRL 0x14c 41 #define DM81XX_CM_ALWON_UART_0_CLKCTRL 0x150 42 #define DM81XX_CM_ALWON_UART_1_CLKCTRL 0x154 43 #define DM81XX_CM_ALWON_UART_2_CLKCTRL 0x158 44 #define DM81XX_CM_ALWON_GPIO_0_CLKCTRL 0x15c 45 #define DM81XX_CM_ALWON_GPIO_1_CLKCTRL 0x160 46 #define DM81XX_CM_ALWON_I2C_0_CLKCTRL 0x164 47 #define DM81XX_CM_ALWON_I2C_1_CLKCTRL 0x168 48 #define DM81XX_CM_ALWON_WDTIMER_CLKCTRL 0x18c 49 #define DM81XX_CM_ALWON_SPI_CLKCTRL 0x190 50 #define DM81XX_CM_ALWON_MAILBOX_CLKCTRL 0x194 51 #define DM81XX_CM_ALWON_SPINBOX_CLKCTRL 0x198 52 #define DM81XX_CM_ALWON_MMUDATA_CLKCTRL 0x19c 53 #define DM81XX_CM_ALWON_MMUCFG_CLKCTRL 0x1a8 54 #define DM81XX_CM_ALWON_CONTROL_CLKCTRL 0x1c4 55 #define DM81XX_CM_ALWON_GPMC_CLKCTRL 0x1d0 56 #define DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL 0x1d4 57 #define DM81XX_CM_ALWON_L3_CLKCTRL 0x1e4 58 #define DM81XX_CM_ALWON_L4HS_CLKCTRL 0x1e8 59 #define DM81XX_CM_ALWON_L4LS_CLKCTRL 0x1ec 60 #define DM81XX_CM_ALWON_RTC_CLKCTRL 0x1f0 61 #define DM81XX_CM_ALWON_TPCC_CLKCTRL 0x1f4 62 #define DM81XX_CM_ALWON_TPTC0_CLKCTRL 0x1f8 63 #define DM81XX_CM_ALWON_TPTC1_CLKCTRL 0x1fc 64 #define DM81XX_CM_ALWON_TPTC2_CLKCTRL 0x200 65 #define DM81XX_CM_ALWON_TPTC3_CLKCTRL 0x204 66 67 /* Registers specific to dm814x */ 68 #define DM814X_CM_ALWON_MCASP_3_4_5_CLKCTRL 0x16c 69 #define DM814X_CM_ALWON_ATL_CLKCTRL 0x170 70 #define DM814X_CM_ALWON_MLB_CLKCTRL 0x174 71 #define DM814X_CM_ALWON_PATA_CLKCTRL 0x178 72 #define DM814X_CM_ALWON_UART_3_CLKCTRL 0x180 73 #define DM814X_CM_ALWON_UART_4_CLKCTRL 0x184 74 #define DM814X_CM_ALWON_UART_5_CLKCTRL 0x188 75 #define DM814X_CM_ALWON_OCM_0_CLKCTRL 0x1b4 76 #define DM814X_CM_ALWON_VCP_CLKCTRL 0x1b8 77 #define DM814X_CM_ALWON_MPU_CLKCTRL 0x1dc 78 #define DM814X_CM_ALWON_DEBUGSS_CLKCTRL 0x1e0 79 #define DM814X_CM_ALWON_DCAN_0_1_CLKCTRL 0x218 80 #define DM814X_CM_ALWON_MMCHS_0_CLKCTRL 0x21c 81 #define DM814X_CM_ALWON_MMCHS_1_CLKCTRL 0x220 82 #define DM814X_CM_ALWON_MMCHS_2_CLKCTRL 0x224 83 #define DM814X_CM_ALWON_CUST_EFUSE_CLKCTRL 0x228 84 85 /* Registers specific to dm816x */ 86 #define DM816X_DM_ALWON_BASE 0x1400 87 #define DM816X_CM_ALWON_TIMER_1_CLKCTRL (0x1570 - DM816X_DM_ALWON_BASE) 88 #define DM816X_CM_ALWON_TIMER_2_CLKCTRL (0x1574 - DM816X_DM_ALWON_BASE) 89 #define DM816X_CM_ALWON_TIMER_3_CLKCTRL (0x1578 - DM816X_DM_ALWON_BASE) 90 #define DM816X_CM_ALWON_TIMER_4_CLKCTRL (0x157c - DM816X_DM_ALWON_BASE) 91 #define DM816X_CM_ALWON_TIMER_5_CLKCTRL (0x1580 - DM816X_DM_ALWON_BASE) 92 #define DM816X_CM_ALWON_TIMER_6_CLKCTRL (0x1584 - DM816X_DM_ALWON_BASE) 93 #define DM816X_CM_ALWON_TIMER_7_CLKCTRL (0x1588 - DM816X_DM_ALWON_BASE) 94 #define DM816X_CM_ALWON_SDIO_CLKCTRL (0x15b0 - DM816X_DM_ALWON_BASE) 95 #define DM816X_CM_ALWON_OCMC_0_CLKCTRL (0x15b4 - DM816X_DM_ALWON_BASE) 96 #define DM816X_CM_ALWON_OCMC_1_CLKCTRL (0x15b8 - DM816X_DM_ALWON_BASE) 97 #define DM816X_CM_ALWON_ETHERNET_1_CLKCTRL (0x15d8 - DM816X_DM_ALWON_BASE) 98 #define DM816X_CM_ALWON_MPU_CLKCTRL (0x15dc - DM816X_DM_ALWON_BASE) 99 #define DM816X_CM_ALWON_SR_0_CLKCTRL (0x1608 - DM816X_DM_ALWON_BASE) 100 #define DM816X_CM_ALWON_SR_1_CLKCTRL (0x160c - DM816X_DM_ALWON_BASE) 101 102 /* 103 * The default .clkctrl_offs field is offset from CM_DEFAULT, that's 104 * TRM 18.7.6 CM_DEFAULT device register values minus 0x500 105 */ 106 #define DM81XX_CM_DEFAULT_OFFSET 0x500 107 #define DM81XX_CM_DEFAULT_USB_CLKCTRL (0x558 - DM81XX_CM_DEFAULT_OFFSET) 108 #define DM81XX_CM_DEFAULT_SATA_CLKCTRL (0x560 - DM81XX_CM_DEFAULT_OFFSET) 109 110 /* L3 Interconnect entries clocked at 125, 250 and 500MHz */ 111 static struct omap_hwmod dm81xx_alwon_l3_slow_hwmod = { 112 .name = "alwon_l3_slow", 113 .clkdm_name = "alwon_l3s_clkdm", 114 .class = &l3_hwmod_class, 115 .flags = HWMOD_NO_IDLEST, 116 }; 117 118 static struct omap_hwmod dm81xx_default_l3_slow_hwmod = { 119 .name = "default_l3_slow", 120 .clkdm_name = "default_l3_slow_clkdm", 121 .class = &l3_hwmod_class, 122 .flags = HWMOD_NO_IDLEST, 123 }; 124 125 static struct omap_hwmod dm81xx_alwon_l3_med_hwmod = { 126 .name = "l3_med", 127 .clkdm_name = "alwon_l3_med_clkdm", 128 .class = &l3_hwmod_class, 129 .flags = HWMOD_NO_IDLEST, 130 }; 131 132 static struct omap_hwmod dm81xx_alwon_l3_fast_hwmod = { 133 .name = "l3_fast", 134 .clkdm_name = "alwon_l3_fast_clkdm", 135 .class = &l3_hwmod_class, 136 .flags = HWMOD_NO_IDLEST, 137 }; 138 139 /* 140 * L4 standard peripherals, see TRM table 1-12 for devices using this. 141 * See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock. 142 */ 143 static struct omap_hwmod dm81xx_l4_ls_hwmod = { 144 .name = "l4_ls", 145 .clkdm_name = "alwon_l3s_clkdm", 146 .class = &l4_hwmod_class, 147 .flags = HWMOD_NO_IDLEST, 148 }; 149 150 /* 151 * L4 high-speed peripherals. For devices using this, please see the TRM 152 * table 1-13. On dm816x, only EMAC, MDIO and SATA use this. See also TRM 153 * table 1-73 for devices using 250MHz SYSCLK5 clock. 154 */ 155 static struct omap_hwmod dm81xx_l4_hs_hwmod = { 156 .name = "l4_hs", 157 .clkdm_name = "alwon_l3_med_clkdm", 158 .class = &l4_hwmod_class, 159 .flags = HWMOD_NO_IDLEST, 160 }; 161 162 /* L3 slow -> L4 ls peripheral interface running at 125MHz */ 163 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_ls = { 164 .master = &dm81xx_alwon_l3_slow_hwmod, 165 .slave = &dm81xx_l4_ls_hwmod, 166 .user = OCP_USER_MPU, 167 }; 168 169 /* L3 med -> L4 fast peripheral interface running at 250MHz */ 170 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_hs = { 171 .master = &dm81xx_alwon_l3_med_hwmod, 172 .slave = &dm81xx_l4_hs_hwmod, 173 .user = OCP_USER_MPU, 174 }; 175 176 /* MPU */ 177 static struct omap_hwmod dm814x_mpu_hwmod = { 178 .name = "mpu", 179 .clkdm_name = "alwon_l3s_clkdm", 180 .class = &mpu_hwmod_class, 181 .flags = HWMOD_INIT_NO_IDLE, 182 .main_clk = "mpu_ck", 183 .prcm = { 184 .omap4 = { 185 .clkctrl_offs = DM814X_CM_ALWON_MPU_CLKCTRL, 186 .modulemode = MODULEMODE_SWCTRL, 187 }, 188 }, 189 }; 190 191 static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_slow = { 192 .master = &dm814x_mpu_hwmod, 193 .slave = &dm81xx_alwon_l3_slow_hwmod, 194 .user = OCP_USER_MPU, 195 }; 196 197 /* L3 med peripheral interface running at 200MHz */ 198 static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_med = { 199 .master = &dm814x_mpu_hwmod, 200 .slave = &dm81xx_alwon_l3_med_hwmod, 201 .user = OCP_USER_MPU, 202 }; 203 204 static struct omap_hwmod dm816x_mpu_hwmod = { 205 .name = "mpu", 206 .clkdm_name = "alwon_mpu_clkdm", 207 .class = &mpu_hwmod_class, 208 .flags = HWMOD_INIT_NO_IDLE, 209 .main_clk = "mpu_ck", 210 .prcm = { 211 .omap4 = { 212 .clkctrl_offs = DM816X_CM_ALWON_MPU_CLKCTRL, 213 .modulemode = MODULEMODE_SWCTRL, 214 }, 215 }, 216 }; 217 218 static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_slow = { 219 .master = &dm816x_mpu_hwmod, 220 .slave = &dm81xx_alwon_l3_slow_hwmod, 221 .user = OCP_USER_MPU, 222 }; 223 224 /* L3 med peripheral interface running at 250MHz */ 225 static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_med = { 226 .master = &dm816x_mpu_hwmod, 227 .slave = &dm81xx_alwon_l3_med_hwmod, 228 .user = OCP_USER_MPU, 229 }; 230 231 /* RTC */ 232 static struct omap_hwmod_class_sysconfig ti81xx_rtc_sysc = { 233 .rev_offs = 0x74, 234 .sysc_offs = 0x78, 235 .sysc_flags = SYSC_HAS_SIDLEMODE, 236 .idlemodes = SIDLE_FORCE | SIDLE_NO | 237 SIDLE_SMART | SIDLE_SMART_WKUP, 238 .sysc_fields = &omap_hwmod_sysc_type3, 239 }; 240 241 static struct omap_hwmod_class ti81xx_rtc_hwmod_class = { 242 .name = "rtc", 243 .sysc = &ti81xx_rtc_sysc, 244 }; 245 246 static struct omap_hwmod ti81xx_rtc_hwmod = { 247 .name = "rtc", 248 .class = &ti81xx_rtc_hwmod_class, 249 .clkdm_name = "alwon_l3s_clkdm", 250 .flags = HWMOD_NO_IDLEST, 251 .main_clk = "sysclk18_ck", 252 .prcm = { 253 .omap4 = { 254 .clkctrl_offs = DM81XX_CM_ALWON_RTC_CLKCTRL, 255 .modulemode = MODULEMODE_SWCTRL, 256 }, 257 }, 258 }; 259 260 static struct omap_hwmod_ocp_if ti81xx_l4_ls__rtc = { 261 .master = &dm81xx_l4_ls_hwmod, 262 .slave = &ti81xx_rtc_hwmod, 263 .clk = "sysclk6_ck", 264 .user = OCP_USER_MPU, 265 }; 266 267 /* UART common */ 268 static struct omap_hwmod_class_sysconfig uart_sysc = { 269 .rev_offs = 0x50, 270 .sysc_offs = 0x54, 271 .syss_offs = 0x58, 272 .sysc_flags = SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | 273 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | 274 SYSS_HAS_RESET_STATUS, 275 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 276 MSTANDBY_SMART_WKUP, 277 .sysc_fields = &omap_hwmod_sysc_type1, 278 }; 279 280 static struct omap_hwmod_class uart_class = { 281 .name = "uart", 282 .sysc = &uart_sysc, 283 }; 284 285 static struct omap_hwmod dm81xx_uart1_hwmod = { 286 .name = "uart1", 287 .clkdm_name = "alwon_l3s_clkdm", 288 .main_clk = "sysclk10_ck", 289 .prcm = { 290 .omap4 = { 291 .clkctrl_offs = DM81XX_CM_ALWON_UART_0_CLKCTRL, 292 .modulemode = MODULEMODE_SWCTRL, 293 }, 294 }, 295 .class = &uart_class, 296 .flags = DEBUG_TI81XXUART1_FLAGS, 297 }; 298 299 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart1 = { 300 .master = &dm81xx_l4_ls_hwmod, 301 .slave = &dm81xx_uart1_hwmod, 302 .clk = "sysclk6_ck", 303 .user = OCP_USER_MPU, 304 }; 305 306 static struct omap_hwmod dm81xx_uart2_hwmod = { 307 .name = "uart2", 308 .clkdm_name = "alwon_l3s_clkdm", 309 .main_clk = "sysclk10_ck", 310 .prcm = { 311 .omap4 = { 312 .clkctrl_offs = DM81XX_CM_ALWON_UART_1_CLKCTRL, 313 .modulemode = MODULEMODE_SWCTRL, 314 }, 315 }, 316 .class = &uart_class, 317 .flags = DEBUG_TI81XXUART2_FLAGS, 318 }; 319 320 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart2 = { 321 .master = &dm81xx_l4_ls_hwmod, 322 .slave = &dm81xx_uart2_hwmod, 323 .clk = "sysclk6_ck", 324 .user = OCP_USER_MPU, 325 }; 326 327 static struct omap_hwmod dm81xx_uart3_hwmod = { 328 .name = "uart3", 329 .clkdm_name = "alwon_l3s_clkdm", 330 .main_clk = "sysclk10_ck", 331 .prcm = { 332 .omap4 = { 333 .clkctrl_offs = DM81XX_CM_ALWON_UART_2_CLKCTRL, 334 .modulemode = MODULEMODE_SWCTRL, 335 }, 336 }, 337 .class = &uart_class, 338 .flags = DEBUG_TI81XXUART3_FLAGS, 339 }; 340 341 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart3 = { 342 .master = &dm81xx_l4_ls_hwmod, 343 .slave = &dm81xx_uart3_hwmod, 344 .clk = "sysclk6_ck", 345 .user = OCP_USER_MPU, 346 }; 347 348 static struct omap_hwmod_class_sysconfig wd_timer_sysc = { 349 .rev_offs = 0x0, 350 .sysc_offs = 0x10, 351 .syss_offs = 0x14, 352 .sysc_flags = SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | 353 SYSS_HAS_RESET_STATUS, 354 .sysc_fields = &omap_hwmod_sysc_type1, 355 }; 356 357 static struct omap_hwmod_class wd_timer_class = { 358 .name = "wd_timer", 359 .sysc = &wd_timer_sysc, 360 .pre_shutdown = &omap2_wd_timer_disable, 361 .reset = &omap2_wd_timer_reset, 362 }; 363 364 static struct omap_hwmod dm81xx_wd_timer_hwmod = { 365 .name = "wd_timer", 366 .clkdm_name = "alwon_l3s_clkdm", 367 .main_clk = "sysclk18_ck", 368 .flags = HWMOD_NO_IDLEST, 369 .prcm = { 370 .omap4 = { 371 .clkctrl_offs = DM81XX_CM_ALWON_WDTIMER_CLKCTRL, 372 .modulemode = MODULEMODE_SWCTRL, 373 }, 374 }, 375 .class = &wd_timer_class, 376 }; 377 378 static struct omap_hwmod_ocp_if dm81xx_l4_ls__wd_timer1 = { 379 .master = &dm81xx_l4_ls_hwmod, 380 .slave = &dm81xx_wd_timer_hwmod, 381 .clk = "sysclk6_ck", 382 .user = OCP_USER_MPU, 383 }; 384 385 /* I2C common */ 386 static struct omap_hwmod_class_sysconfig i2c_sysc = { 387 .rev_offs = 0x0, 388 .sysc_offs = 0x10, 389 .syss_offs = 0x90, 390 .sysc_flags = SYSC_HAS_SIDLEMODE | 391 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 392 SYSC_HAS_AUTOIDLE, 393 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 394 .sysc_fields = &omap_hwmod_sysc_type1, 395 }; 396 397 static struct omap_hwmod_class i2c_class = { 398 .name = "i2c", 399 .sysc = &i2c_sysc, 400 }; 401 402 static struct omap_hwmod dm81xx_i2c1_hwmod = { 403 .name = "i2c1", 404 .clkdm_name = "alwon_l3s_clkdm", 405 .main_clk = "sysclk10_ck", 406 .prcm = { 407 .omap4 = { 408 .clkctrl_offs = DM81XX_CM_ALWON_I2C_0_CLKCTRL, 409 .modulemode = MODULEMODE_SWCTRL, 410 }, 411 }, 412 .class = &i2c_class, 413 }; 414 415 static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c1 = { 416 .master = &dm81xx_l4_ls_hwmod, 417 .slave = &dm81xx_i2c1_hwmod, 418 .clk = "sysclk6_ck", 419 .user = OCP_USER_MPU, 420 }; 421 422 static struct omap_hwmod dm81xx_i2c2_hwmod = { 423 .name = "i2c2", 424 .clkdm_name = "alwon_l3s_clkdm", 425 .main_clk = "sysclk10_ck", 426 .prcm = { 427 .omap4 = { 428 .clkctrl_offs = DM81XX_CM_ALWON_I2C_1_CLKCTRL, 429 .modulemode = MODULEMODE_SWCTRL, 430 }, 431 }, 432 .class = &i2c_class, 433 }; 434 435 static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c2 = { 436 .master = &dm81xx_l4_ls_hwmod, 437 .slave = &dm81xx_i2c2_hwmod, 438 .clk = "sysclk6_ck", 439 .user = OCP_USER_MPU, 440 }; 441 442 static struct omap_hwmod_class_sysconfig dm81xx_elm_sysc = { 443 .rev_offs = 0x0000, 444 .sysc_offs = 0x0010, 445 .syss_offs = 0x0014, 446 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 447 SYSC_HAS_SOFTRESET | 448 SYSS_HAS_RESET_STATUS, 449 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 450 .sysc_fields = &omap_hwmod_sysc_type1, 451 }; 452 453 static struct omap_hwmod_class dm81xx_elm_hwmod_class = { 454 .name = "elm", 455 .sysc = &dm81xx_elm_sysc, 456 }; 457 458 static struct omap_hwmod dm81xx_elm_hwmod = { 459 .name = "elm", 460 .clkdm_name = "alwon_l3s_clkdm", 461 .class = &dm81xx_elm_hwmod_class, 462 .main_clk = "sysclk6_ck", 463 }; 464 465 static struct omap_hwmod_ocp_if dm81xx_l4_ls__elm = { 466 .master = &dm81xx_l4_ls_hwmod, 467 .slave = &dm81xx_elm_hwmod, 468 .clk = "sysclk6_ck", 469 .user = OCP_USER_MPU, 470 }; 471 472 static struct omap_hwmod_class_sysconfig dm81xx_gpio_sysc = { 473 .rev_offs = 0x0000, 474 .sysc_offs = 0x0010, 475 .syss_offs = 0x0114, 476 .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | 477 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 478 SYSS_HAS_RESET_STATUS, 479 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 480 SIDLE_SMART_WKUP, 481 .sysc_fields = &omap_hwmod_sysc_type1, 482 }; 483 484 static struct omap_hwmod_class dm81xx_gpio_hwmod_class = { 485 .name = "gpio", 486 .sysc = &dm81xx_gpio_sysc, 487 }; 488 489 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { 490 { .role = "dbclk", .clk = "sysclk18_ck" }, 491 }; 492 493 static struct omap_hwmod dm81xx_gpio1_hwmod = { 494 .name = "gpio1", 495 .clkdm_name = "alwon_l3s_clkdm", 496 .class = &dm81xx_gpio_hwmod_class, 497 .main_clk = "sysclk6_ck", 498 .prcm = { 499 .omap4 = { 500 .clkctrl_offs = DM81XX_CM_ALWON_GPIO_0_CLKCTRL, 501 .modulemode = MODULEMODE_SWCTRL, 502 }, 503 }, 504 .opt_clks = gpio1_opt_clks, 505 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), 506 }; 507 508 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio1 = { 509 .master = &dm81xx_l4_ls_hwmod, 510 .slave = &dm81xx_gpio1_hwmod, 511 .clk = "sysclk6_ck", 512 .user = OCP_USER_MPU, 513 }; 514 515 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { 516 { .role = "dbclk", .clk = "sysclk18_ck" }, 517 }; 518 519 static struct omap_hwmod dm81xx_gpio2_hwmod = { 520 .name = "gpio2", 521 .clkdm_name = "alwon_l3s_clkdm", 522 .class = &dm81xx_gpio_hwmod_class, 523 .main_clk = "sysclk6_ck", 524 .prcm = { 525 .omap4 = { 526 .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL, 527 .modulemode = MODULEMODE_SWCTRL, 528 }, 529 }, 530 .opt_clks = gpio2_opt_clks, 531 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), 532 }; 533 534 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = { 535 .master = &dm81xx_l4_ls_hwmod, 536 .slave = &dm81xx_gpio2_hwmod, 537 .clk = "sysclk6_ck", 538 .user = OCP_USER_MPU, 539 }; 540 541 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { 542 { .role = "dbclk", .clk = "sysclk18_ck" }, 543 }; 544 545 static struct omap_hwmod dm81xx_gpio3_hwmod = { 546 .name = "gpio3", 547 .clkdm_name = "alwon_l3s_clkdm", 548 .class = &dm81xx_gpio_hwmod_class, 549 .main_clk = "sysclk6_ck", 550 .prcm = { 551 .omap4 = { 552 .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL, 553 .modulemode = MODULEMODE_SWCTRL, 554 }, 555 }, 556 .opt_clks = gpio3_opt_clks, 557 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), 558 }; 559 560 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio3 = { 561 .master = &dm81xx_l4_ls_hwmod, 562 .slave = &dm81xx_gpio3_hwmod, 563 .clk = "sysclk6_ck", 564 .user = OCP_USER_MPU, 565 }; 566 567 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { 568 { .role = "dbclk", .clk = "sysclk18_ck" }, 569 }; 570 571 static struct omap_hwmod dm81xx_gpio4_hwmod = { 572 .name = "gpio4", 573 .clkdm_name = "alwon_l3s_clkdm", 574 .class = &dm81xx_gpio_hwmod_class, 575 .main_clk = "sysclk6_ck", 576 .prcm = { 577 .omap4 = { 578 .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL, 579 .modulemode = MODULEMODE_SWCTRL, 580 }, 581 }, 582 .opt_clks = gpio4_opt_clks, 583 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), 584 }; 585 586 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio4 = { 587 .master = &dm81xx_l4_ls_hwmod, 588 .slave = &dm81xx_gpio4_hwmod, 589 .clk = "sysclk6_ck", 590 .user = OCP_USER_MPU, 591 }; 592 593 static struct omap_hwmod_class_sysconfig dm81xx_gpmc_sysc = { 594 .rev_offs = 0x0, 595 .sysc_offs = 0x10, 596 .syss_offs = 0x14, 597 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 598 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS, 599 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 600 .sysc_fields = &omap_hwmod_sysc_type1, 601 }; 602 603 static struct omap_hwmod_class dm81xx_gpmc_hwmod_class = { 604 .name = "gpmc", 605 .sysc = &dm81xx_gpmc_sysc, 606 }; 607 608 static struct omap_hwmod dm81xx_gpmc_hwmod = { 609 .name = "gpmc", 610 .clkdm_name = "alwon_l3s_clkdm", 611 .class = &dm81xx_gpmc_hwmod_class, 612 .main_clk = "sysclk6_ck", 613 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */ 614 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS, 615 .prcm = { 616 .omap4 = { 617 .clkctrl_offs = DM81XX_CM_ALWON_GPMC_CLKCTRL, 618 .modulemode = MODULEMODE_SWCTRL, 619 }, 620 }, 621 }; 622 623 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__gpmc = { 624 .master = &dm81xx_alwon_l3_slow_hwmod, 625 .slave = &dm81xx_gpmc_hwmod, 626 .user = OCP_USER_MPU, 627 }; 628 629 /* USB needs udelay 1 after reset at least on hp t410, use 2 for margin */ 630 static struct omap_hwmod_class_sysconfig dm81xx_usbhsotg_sysc = { 631 .rev_offs = 0x0, 632 .sysc_offs = 0x10, 633 .srst_udelay = 2, 634 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | 635 SYSC_HAS_SOFTRESET, 636 .idlemodes = SIDLE_SMART | MSTANDBY_FORCE | MSTANDBY_SMART, 637 .sysc_fields = &omap_hwmod_sysc_type2, 638 }; 639 640 static struct omap_hwmod_class dm81xx_usbotg_class = { 641 .name = "usbotg", 642 .sysc = &dm81xx_usbhsotg_sysc, 643 }; 644 645 static struct omap_hwmod dm814x_usbss_hwmod = { 646 .name = "usb_otg_hs", 647 .clkdm_name = "default_l3_slow_clkdm", 648 .main_clk = "pll260dcoclkldo", /* 481c5260.adpll.dcoclkldo */ 649 .prcm = { 650 .omap4 = { 651 .clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL, 652 .modulemode = MODULEMODE_SWCTRL, 653 }, 654 }, 655 .class = &dm81xx_usbotg_class, 656 }; 657 658 static struct omap_hwmod_ocp_if dm814x_default_l3_slow__usbss = { 659 .master = &dm81xx_default_l3_slow_hwmod, 660 .slave = &dm814x_usbss_hwmod, 661 .clk = "sysclk6_ck", 662 .user = OCP_USER_MPU, 663 }; 664 665 static struct omap_hwmod dm816x_usbss_hwmod = { 666 .name = "usb_otg_hs", 667 .clkdm_name = "default_l3_slow_clkdm", 668 .main_clk = "sysclk6_ck", 669 .prcm = { 670 .omap4 = { 671 .clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL, 672 .modulemode = MODULEMODE_SWCTRL, 673 }, 674 }, 675 .class = &dm81xx_usbotg_class, 676 }; 677 678 static struct omap_hwmod_ocp_if dm816x_default_l3_slow__usbss = { 679 .master = &dm81xx_default_l3_slow_hwmod, 680 .slave = &dm816x_usbss_hwmod, 681 .clk = "sysclk6_ck", 682 .user = OCP_USER_MPU, 683 }; 684 685 static struct omap_hwmod_class_sysconfig dm816x_timer_sysc = { 686 .rev_offs = 0x0000, 687 .sysc_offs = 0x0010, 688 .syss_offs = 0x0014, 689 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET, 690 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 691 SIDLE_SMART_WKUP, 692 .sysc_fields = &omap_hwmod_sysc_type2, 693 }; 694 695 static struct omap_hwmod_class dm816x_timer_hwmod_class = { 696 .name = "timer", 697 .sysc = &dm816x_timer_sysc, 698 }; 699 700 static struct omap_hwmod dm814x_timer1_hwmod = { 701 .name = "timer1", 702 .clkdm_name = "alwon_l3s_clkdm", 703 .main_clk = "timer1_fck", 704 .class = &dm816x_timer_hwmod_class, 705 .flags = HWMOD_NO_IDLEST, 706 }; 707 708 static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = { 709 .master = &dm81xx_l4_ls_hwmod, 710 .slave = &dm814x_timer1_hwmod, 711 .clk = "sysclk6_ck", 712 .user = OCP_USER_MPU, 713 }; 714 715 static struct omap_hwmod dm816x_timer1_hwmod = { 716 .name = "timer1", 717 .clkdm_name = "alwon_l3s_clkdm", 718 .main_clk = "timer1_fck", 719 .prcm = { 720 .omap4 = { 721 .clkctrl_offs = DM816X_CM_ALWON_TIMER_1_CLKCTRL, 722 .modulemode = MODULEMODE_SWCTRL, 723 }, 724 }, 725 .class = &dm816x_timer_hwmod_class, 726 }; 727 728 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = { 729 .master = &dm81xx_l4_ls_hwmod, 730 .slave = &dm816x_timer1_hwmod, 731 .clk = "sysclk6_ck", 732 .user = OCP_USER_MPU, 733 }; 734 735 static struct omap_hwmod dm814x_timer2_hwmod = { 736 .name = "timer2", 737 .clkdm_name = "alwon_l3s_clkdm", 738 .main_clk = "timer2_fck", 739 .class = &dm816x_timer_hwmod_class, 740 .flags = HWMOD_NO_IDLEST, 741 }; 742 743 static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = { 744 .master = &dm81xx_l4_ls_hwmod, 745 .slave = &dm814x_timer2_hwmod, 746 .clk = "sysclk6_ck", 747 .user = OCP_USER_MPU, 748 }; 749 750 static struct omap_hwmod dm816x_timer2_hwmod = { 751 .name = "timer2", 752 .clkdm_name = "alwon_l3s_clkdm", 753 .main_clk = "timer2_fck", 754 .prcm = { 755 .omap4 = { 756 .clkctrl_offs = DM816X_CM_ALWON_TIMER_2_CLKCTRL, 757 .modulemode = MODULEMODE_SWCTRL, 758 }, 759 }, 760 .class = &dm816x_timer_hwmod_class, 761 }; 762 763 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer2 = { 764 .master = &dm81xx_l4_ls_hwmod, 765 .slave = &dm816x_timer2_hwmod, 766 .clk = "sysclk6_ck", 767 .user = OCP_USER_MPU, 768 }; 769 770 static struct omap_hwmod dm816x_timer3_hwmod = { 771 .name = "timer3", 772 .clkdm_name = "alwon_l3s_clkdm", 773 .main_clk = "timer3_fck", 774 .prcm = { 775 .omap4 = { 776 .clkctrl_offs = DM816X_CM_ALWON_TIMER_3_CLKCTRL, 777 .modulemode = MODULEMODE_SWCTRL, 778 }, 779 }, 780 .class = &dm816x_timer_hwmod_class, 781 }; 782 783 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer3 = { 784 .master = &dm81xx_l4_ls_hwmod, 785 .slave = &dm816x_timer3_hwmod, 786 .clk = "sysclk6_ck", 787 .user = OCP_USER_MPU, 788 }; 789 790 static struct omap_hwmod dm816x_timer4_hwmod = { 791 .name = "timer4", 792 .clkdm_name = "alwon_l3s_clkdm", 793 .main_clk = "timer4_fck", 794 .prcm = { 795 .omap4 = { 796 .clkctrl_offs = DM816X_CM_ALWON_TIMER_4_CLKCTRL, 797 .modulemode = MODULEMODE_SWCTRL, 798 }, 799 }, 800 .class = &dm816x_timer_hwmod_class, 801 }; 802 803 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer4 = { 804 .master = &dm81xx_l4_ls_hwmod, 805 .slave = &dm816x_timer4_hwmod, 806 .clk = "sysclk6_ck", 807 .user = OCP_USER_MPU, 808 }; 809 810 static struct omap_hwmod dm816x_timer5_hwmod = { 811 .name = "timer5", 812 .clkdm_name = "alwon_l3s_clkdm", 813 .main_clk = "timer5_fck", 814 .prcm = { 815 .omap4 = { 816 .clkctrl_offs = DM816X_CM_ALWON_TIMER_5_CLKCTRL, 817 .modulemode = MODULEMODE_SWCTRL, 818 }, 819 }, 820 .class = &dm816x_timer_hwmod_class, 821 }; 822 823 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer5 = { 824 .master = &dm81xx_l4_ls_hwmod, 825 .slave = &dm816x_timer5_hwmod, 826 .clk = "sysclk6_ck", 827 .user = OCP_USER_MPU, 828 }; 829 830 static struct omap_hwmod dm816x_timer6_hwmod = { 831 .name = "timer6", 832 .clkdm_name = "alwon_l3s_clkdm", 833 .main_clk = "timer6_fck", 834 .prcm = { 835 .omap4 = { 836 .clkctrl_offs = DM816X_CM_ALWON_TIMER_6_CLKCTRL, 837 .modulemode = MODULEMODE_SWCTRL, 838 }, 839 }, 840 .class = &dm816x_timer_hwmod_class, 841 }; 842 843 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer6 = { 844 .master = &dm81xx_l4_ls_hwmod, 845 .slave = &dm816x_timer6_hwmod, 846 .clk = "sysclk6_ck", 847 .user = OCP_USER_MPU, 848 }; 849 850 static struct omap_hwmod dm816x_timer7_hwmod = { 851 .name = "timer7", 852 .clkdm_name = "alwon_l3s_clkdm", 853 .main_clk = "timer7_fck", 854 .prcm = { 855 .omap4 = { 856 .clkctrl_offs = DM816X_CM_ALWON_TIMER_7_CLKCTRL, 857 .modulemode = MODULEMODE_SWCTRL, 858 }, 859 }, 860 .class = &dm816x_timer_hwmod_class, 861 }; 862 863 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer7 = { 864 .master = &dm81xx_l4_ls_hwmod, 865 .slave = &dm816x_timer7_hwmod, 866 .clk = "sysclk6_ck", 867 .user = OCP_USER_MPU, 868 }; 869 870 /* CPSW on dm814x */ 871 static struct omap_hwmod_class_sysconfig dm814x_cpgmac_sysc = { 872 .rev_offs = 0x0, 873 .sysc_offs = 0x8, 874 .syss_offs = 0x4, 875 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | 876 SYSS_HAS_RESET_STATUS, 877 .idlemodes = SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE | 878 MSTANDBY_NO, 879 .sysc_fields = &omap_hwmod_sysc_type3, 880 }; 881 882 static struct omap_hwmod_class dm814x_cpgmac0_hwmod_class = { 883 .name = "cpgmac0", 884 .sysc = &dm814x_cpgmac_sysc, 885 }; 886 887 static struct omap_hwmod dm814x_cpgmac0_hwmod = { 888 .name = "cpgmac0", 889 .class = &dm814x_cpgmac0_hwmod_class, 890 .clkdm_name = "alwon_ethernet_clkdm", 891 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, 892 .main_clk = "cpsw_125mhz_gclk", 893 .prcm = { 894 .omap4 = { 895 .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL, 896 .modulemode = MODULEMODE_SWCTRL, 897 }, 898 }, 899 }; 900 901 static struct omap_hwmod_class dm814x_mdio_hwmod_class = { 902 .name = "davinci_mdio", 903 }; 904 905 static struct omap_hwmod dm814x_mdio_hwmod = { 906 .name = "davinci_mdio", 907 .class = &dm814x_mdio_hwmod_class, 908 .clkdm_name = "alwon_ethernet_clkdm", 909 .main_clk = "cpsw_125mhz_gclk", 910 }; 911 912 static struct omap_hwmod_ocp_if dm814x_l4_hs__cpgmac0 = { 913 .master = &dm81xx_l4_hs_hwmod, 914 .slave = &dm814x_cpgmac0_hwmod, 915 .clk = "cpsw_125mhz_gclk", 916 .user = OCP_USER_MPU, 917 }; 918 919 static struct omap_hwmod_ocp_if dm814x_cpgmac0__mdio = { 920 .master = &dm814x_cpgmac0_hwmod, 921 .slave = &dm814x_mdio_hwmod, 922 .user = OCP_USER_MPU, 923 .flags = HWMOD_NO_IDLEST, 924 }; 925 926 /* EMAC Ethernet */ 927 static struct omap_hwmod_class_sysconfig dm816x_emac_sysc = { 928 .rev_offs = 0x0, 929 .sysc_offs = 0x4, 930 .sysc_flags = SYSC_HAS_SOFTRESET, 931 .sysc_fields = &omap_hwmod_sysc_type2, 932 }; 933 934 static struct omap_hwmod_class dm816x_emac_hwmod_class = { 935 .name = "emac", 936 .sysc = &dm816x_emac_sysc, 937 }; 938 939 /* 940 * On dm816x the MDIO is within EMAC0. As the MDIO driver is a separate 941 * driver probed before EMAC0, we let MDIO do the clock idling. 942 */ 943 static struct omap_hwmod dm816x_emac0_hwmod = { 944 .name = "emac0", 945 .clkdm_name = "alwon_ethernet_clkdm", 946 .class = &dm816x_emac_hwmod_class, 947 .flags = HWMOD_NO_IDLEST, 948 }; 949 950 static struct omap_hwmod_ocp_if dm81xx_l4_hs__emac0 = { 951 .master = &dm81xx_l4_hs_hwmod, 952 .slave = &dm816x_emac0_hwmod, 953 .clk = "sysclk5_ck", 954 .user = OCP_USER_MPU, 955 }; 956 957 static struct omap_hwmod_class dm81xx_mdio_hwmod_class = { 958 .name = "davinci_mdio", 959 .sysc = &dm816x_emac_sysc, 960 }; 961 962 static struct omap_hwmod dm81xx_emac0_mdio_hwmod = { 963 .name = "davinci_mdio", 964 .class = &dm81xx_mdio_hwmod_class, 965 .clkdm_name = "alwon_ethernet_clkdm", 966 .main_clk = "sysclk24_ck", 967 .flags = HWMOD_NO_IDLEST, 968 /* 969 * REVISIT: This should be moved to the emac0_hwmod 970 * once we have a better way to handle device slaves. 971 */ 972 .prcm = { 973 .omap4 = { 974 .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL, 975 .modulemode = MODULEMODE_SWCTRL, 976 }, 977 }, 978 }; 979 980 static struct omap_hwmod_ocp_if dm81xx_emac0__mdio = { 981 .master = &dm81xx_l4_hs_hwmod, 982 .slave = &dm81xx_emac0_mdio_hwmod, 983 .user = OCP_USER_MPU, 984 }; 985 986 static struct omap_hwmod dm816x_emac1_hwmod = { 987 .name = "emac1", 988 .clkdm_name = "alwon_ethernet_clkdm", 989 .main_clk = "sysclk24_ck", 990 .flags = HWMOD_NO_IDLEST, 991 .prcm = { 992 .omap4 = { 993 .clkctrl_offs = DM816X_CM_ALWON_ETHERNET_1_CLKCTRL, 994 .modulemode = MODULEMODE_SWCTRL, 995 }, 996 }, 997 .class = &dm816x_emac_hwmod_class, 998 }; 999 1000 static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1 = { 1001 .master = &dm81xx_l4_hs_hwmod, 1002 .slave = &dm816x_emac1_hwmod, 1003 .clk = "sysclk5_ck", 1004 .user = OCP_USER_MPU, 1005 }; 1006 1007 static struct omap_hwmod_class_sysconfig dm81xx_sata_sysc = { 1008 .rev_offs = 0x00fc, 1009 .sysc_offs = 0x1100, 1010 .sysc_flags = SYSC_HAS_SIDLEMODE, 1011 .idlemodes = SIDLE_FORCE, 1012 .sysc_fields = &omap_hwmod_sysc_type3, 1013 }; 1014 1015 static struct omap_hwmod_class dm81xx_sata_hwmod_class = { 1016 .name = "sata", 1017 .sysc = &dm81xx_sata_sysc, 1018 }; 1019 1020 static struct omap_hwmod dm81xx_sata_hwmod = { 1021 .name = "sata", 1022 .clkdm_name = "default_clkdm", 1023 .flags = HWMOD_NO_IDLEST, 1024 .prcm = { 1025 .omap4 = { 1026 .clkctrl_offs = DM81XX_CM_DEFAULT_SATA_CLKCTRL, 1027 .modulemode = MODULEMODE_SWCTRL, 1028 }, 1029 }, 1030 .class = &dm81xx_sata_hwmod_class, 1031 }; 1032 1033 static struct omap_hwmod_ocp_if dm81xx_l4_hs__sata = { 1034 .master = &dm81xx_l4_hs_hwmod, 1035 .slave = &dm81xx_sata_hwmod, 1036 .clk = "sysclk5_ck", 1037 .user = OCP_USER_MPU, 1038 }; 1039 1040 static struct omap_hwmod_class_sysconfig dm81xx_mmc_sysc = { 1041 .rev_offs = 0x0, 1042 .sysc_offs = 0x110, 1043 .syss_offs = 0x114, 1044 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1045 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 1046 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS, 1047 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 1048 .sysc_fields = &omap_hwmod_sysc_type1, 1049 }; 1050 1051 static struct omap_hwmod_class dm81xx_mmc_class = { 1052 .name = "mmc", 1053 .sysc = &dm81xx_mmc_sysc, 1054 }; 1055 1056 static struct omap_hwmod_opt_clk dm81xx_mmc_opt_clks[] = { 1057 { .role = "dbck", .clk = "sysclk18_ck", }, 1058 }; 1059 1060 static struct omap_hsmmc_dev_attr mmc_dev_attr = { 1061 }; 1062 1063 static struct omap_hwmod dm814x_mmc1_hwmod = { 1064 .name = "mmc1", 1065 .clkdm_name = "alwon_l3s_clkdm", 1066 .opt_clks = dm81xx_mmc_opt_clks, 1067 .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks), 1068 .main_clk = "sysclk8_ck", 1069 .prcm = { 1070 .omap4 = { 1071 .clkctrl_offs = DM814X_CM_ALWON_MMCHS_0_CLKCTRL, 1072 .modulemode = MODULEMODE_SWCTRL, 1073 }, 1074 }, 1075 .dev_attr = &mmc_dev_attr, 1076 .class = &dm81xx_mmc_class, 1077 }; 1078 1079 static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc1 = { 1080 .master = &dm81xx_l4_ls_hwmod, 1081 .slave = &dm814x_mmc1_hwmod, 1082 .clk = "sysclk6_ck", 1083 .user = OCP_USER_MPU, 1084 .flags = OMAP_FIREWALL_L4 1085 }; 1086 1087 static struct omap_hwmod dm814x_mmc2_hwmod = { 1088 .name = "mmc2", 1089 .clkdm_name = "alwon_l3s_clkdm", 1090 .opt_clks = dm81xx_mmc_opt_clks, 1091 .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks), 1092 .main_clk = "sysclk8_ck", 1093 .prcm = { 1094 .omap4 = { 1095 .clkctrl_offs = DM814X_CM_ALWON_MMCHS_1_CLKCTRL, 1096 .modulemode = MODULEMODE_SWCTRL, 1097 }, 1098 }, 1099 .dev_attr = &mmc_dev_attr, 1100 .class = &dm81xx_mmc_class, 1101 }; 1102 1103 static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc2 = { 1104 .master = &dm81xx_l4_ls_hwmod, 1105 .slave = &dm814x_mmc2_hwmod, 1106 .clk = "sysclk6_ck", 1107 .user = OCP_USER_MPU, 1108 .flags = OMAP_FIREWALL_L4 1109 }; 1110 1111 static struct omap_hwmod dm814x_mmc3_hwmod = { 1112 .name = "mmc3", 1113 .clkdm_name = "alwon_l3_med_clkdm", 1114 .opt_clks = dm81xx_mmc_opt_clks, 1115 .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks), 1116 .main_clk = "sysclk8_ck", 1117 .prcm = { 1118 .omap4 = { 1119 .clkctrl_offs = DM814X_CM_ALWON_MMCHS_2_CLKCTRL, 1120 .modulemode = MODULEMODE_SWCTRL, 1121 }, 1122 }, 1123 .dev_attr = &mmc_dev_attr, 1124 .class = &dm81xx_mmc_class, 1125 }; 1126 1127 static struct omap_hwmod_ocp_if dm814x_alwon_l3_med__mmc3 = { 1128 .master = &dm81xx_alwon_l3_med_hwmod, 1129 .slave = &dm814x_mmc3_hwmod, 1130 .clk = "sysclk4_ck", 1131 .user = OCP_USER_MPU, 1132 }; 1133 1134 static struct omap_hwmod dm816x_mmc1_hwmod = { 1135 .name = "mmc1", 1136 .clkdm_name = "alwon_l3s_clkdm", 1137 .opt_clks = dm81xx_mmc_opt_clks, 1138 .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks), 1139 .main_clk = "sysclk10_ck", 1140 .prcm = { 1141 .omap4 = { 1142 .clkctrl_offs = DM816X_CM_ALWON_SDIO_CLKCTRL, 1143 .modulemode = MODULEMODE_SWCTRL, 1144 }, 1145 }, 1146 .dev_attr = &mmc_dev_attr, 1147 .class = &dm81xx_mmc_class, 1148 }; 1149 1150 static struct omap_hwmod_ocp_if dm816x_l4_ls__mmc1 = { 1151 .master = &dm81xx_l4_ls_hwmod, 1152 .slave = &dm816x_mmc1_hwmod, 1153 .clk = "sysclk6_ck", 1154 .user = OCP_USER_MPU, 1155 .flags = OMAP_FIREWALL_L4 1156 }; 1157 1158 static struct omap_hwmod_class_sysconfig dm816x_mcspi_sysc = { 1159 .rev_offs = 0x0, 1160 .sysc_offs = 0x110, 1161 .syss_offs = 0x114, 1162 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1163 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 1164 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS, 1165 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 1166 .sysc_fields = &omap_hwmod_sysc_type1, 1167 }; 1168 1169 static struct omap_hwmod_class dm816x_mcspi_class = { 1170 .name = "mcspi", 1171 .sysc = &dm816x_mcspi_sysc, 1172 }; 1173 1174 static struct omap_hwmod dm81xx_mcspi1_hwmod = { 1175 .name = "mcspi1", 1176 .clkdm_name = "alwon_l3s_clkdm", 1177 .main_clk = "sysclk10_ck", 1178 .prcm = { 1179 .omap4 = { 1180 .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL, 1181 .modulemode = MODULEMODE_SWCTRL, 1182 }, 1183 }, 1184 .class = &dm816x_mcspi_class, 1185 }; 1186 1187 static struct omap_hwmod dm81xx_mcspi2_hwmod = { 1188 .name = "mcspi2", 1189 .clkdm_name = "alwon_l3s_clkdm", 1190 .main_clk = "sysclk10_ck", 1191 .prcm = { 1192 .omap4 = { 1193 .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL, 1194 .modulemode = MODULEMODE_SWCTRL, 1195 }, 1196 }, 1197 .class = &dm816x_mcspi_class, 1198 }; 1199 1200 static struct omap_hwmod dm81xx_mcspi3_hwmod = { 1201 .name = "mcspi3", 1202 .clkdm_name = "alwon_l3s_clkdm", 1203 .main_clk = "sysclk10_ck", 1204 .prcm = { 1205 .omap4 = { 1206 .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL, 1207 .modulemode = MODULEMODE_SWCTRL, 1208 }, 1209 }, 1210 .class = &dm816x_mcspi_class, 1211 }; 1212 1213 static struct omap_hwmod dm81xx_mcspi4_hwmod = { 1214 .name = "mcspi4", 1215 .clkdm_name = "alwon_l3s_clkdm", 1216 .main_clk = "sysclk10_ck", 1217 .prcm = { 1218 .omap4 = { 1219 .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL, 1220 .modulemode = MODULEMODE_SWCTRL, 1221 }, 1222 }, 1223 .class = &dm816x_mcspi_class, 1224 }; 1225 1226 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = { 1227 .master = &dm81xx_l4_ls_hwmod, 1228 .slave = &dm81xx_mcspi1_hwmod, 1229 .clk = "sysclk6_ck", 1230 .user = OCP_USER_MPU, 1231 }; 1232 1233 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi2 = { 1234 .master = &dm81xx_l4_ls_hwmod, 1235 .slave = &dm81xx_mcspi2_hwmod, 1236 .clk = "sysclk6_ck", 1237 .user = OCP_USER_MPU, 1238 }; 1239 1240 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi3 = { 1241 .master = &dm81xx_l4_ls_hwmod, 1242 .slave = &dm81xx_mcspi3_hwmod, 1243 .clk = "sysclk6_ck", 1244 .user = OCP_USER_MPU, 1245 }; 1246 1247 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi4 = { 1248 .master = &dm81xx_l4_ls_hwmod, 1249 .slave = &dm81xx_mcspi4_hwmod, 1250 .clk = "sysclk6_ck", 1251 .user = OCP_USER_MPU, 1252 }; 1253 1254 static struct omap_hwmod_class_sysconfig dm81xx_mailbox_sysc = { 1255 .rev_offs = 0x000, 1256 .sysc_offs = 0x010, 1257 .syss_offs = 0x014, 1258 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1259 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE, 1260 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 1261 .sysc_fields = &omap_hwmod_sysc_type1, 1262 }; 1263 1264 static struct omap_hwmod_class dm81xx_mailbox_hwmod_class = { 1265 .name = "mailbox", 1266 .sysc = &dm81xx_mailbox_sysc, 1267 }; 1268 1269 static struct omap_hwmod dm81xx_mailbox_hwmod = { 1270 .name = "mailbox", 1271 .clkdm_name = "alwon_l3s_clkdm", 1272 .class = &dm81xx_mailbox_hwmod_class, 1273 .main_clk = "sysclk6_ck", 1274 .prcm = { 1275 .omap4 = { 1276 .clkctrl_offs = DM81XX_CM_ALWON_MAILBOX_CLKCTRL, 1277 .modulemode = MODULEMODE_SWCTRL, 1278 }, 1279 }, 1280 }; 1281 1282 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mailbox = { 1283 .master = &dm81xx_l4_ls_hwmod, 1284 .slave = &dm81xx_mailbox_hwmod, 1285 .clk = "sysclk6_ck", 1286 .user = OCP_USER_MPU, 1287 }; 1288 1289 static struct omap_hwmod_class_sysconfig dm81xx_spinbox_sysc = { 1290 .rev_offs = 0x000, 1291 .sysc_offs = 0x010, 1292 .syss_offs = 0x014, 1293 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1294 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE, 1295 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 1296 .sysc_fields = &omap_hwmod_sysc_type1, 1297 }; 1298 1299 static struct omap_hwmod_class dm81xx_spinbox_hwmod_class = { 1300 .name = "spinbox", 1301 .sysc = &dm81xx_spinbox_sysc, 1302 }; 1303 1304 static struct omap_hwmod dm81xx_spinbox_hwmod = { 1305 .name = "spinbox", 1306 .clkdm_name = "alwon_l3s_clkdm", 1307 .class = &dm81xx_spinbox_hwmod_class, 1308 .main_clk = "sysclk6_ck", 1309 .prcm = { 1310 .omap4 = { 1311 .clkctrl_offs = DM81XX_CM_ALWON_SPINBOX_CLKCTRL, 1312 .modulemode = MODULEMODE_SWCTRL, 1313 }, 1314 }, 1315 }; 1316 1317 static struct omap_hwmod_ocp_if dm81xx_l4_ls__spinbox = { 1318 .master = &dm81xx_l4_ls_hwmod, 1319 .slave = &dm81xx_spinbox_hwmod, 1320 .clk = "sysclk6_ck", 1321 .user = OCP_USER_MPU, 1322 }; 1323 1324 static struct omap_hwmod_class dm81xx_tpcc_hwmod_class = { 1325 .name = "tpcc", 1326 }; 1327 1328 static struct omap_hwmod dm81xx_tpcc_hwmod = { 1329 .name = "tpcc", 1330 .class = &dm81xx_tpcc_hwmod_class, 1331 .clkdm_name = "alwon_l3s_clkdm", 1332 .main_clk = "sysclk4_ck", 1333 .prcm = { 1334 .omap4 = { 1335 .clkctrl_offs = DM81XX_CM_ALWON_TPCC_CLKCTRL, 1336 .modulemode = MODULEMODE_SWCTRL, 1337 }, 1338 }, 1339 }; 1340 1341 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tpcc = { 1342 .master = &dm81xx_alwon_l3_fast_hwmod, 1343 .slave = &dm81xx_tpcc_hwmod, 1344 .clk = "sysclk4_ck", 1345 .user = OCP_USER_MPU, 1346 }; 1347 1348 static struct omap_hwmod_class dm81xx_tptc0_hwmod_class = { 1349 .name = "tptc0", 1350 }; 1351 1352 static struct omap_hwmod dm81xx_tptc0_hwmod = { 1353 .name = "tptc0", 1354 .class = &dm81xx_tptc0_hwmod_class, 1355 .clkdm_name = "alwon_l3s_clkdm", 1356 .main_clk = "sysclk4_ck", 1357 .prcm = { 1358 .omap4 = { 1359 .clkctrl_offs = DM81XX_CM_ALWON_TPTC0_CLKCTRL, 1360 .modulemode = MODULEMODE_SWCTRL, 1361 }, 1362 }, 1363 }; 1364 1365 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc0 = { 1366 .master = &dm81xx_alwon_l3_fast_hwmod, 1367 .slave = &dm81xx_tptc0_hwmod, 1368 .clk = "sysclk4_ck", 1369 .user = OCP_USER_MPU, 1370 }; 1371 1372 static struct omap_hwmod_ocp_if dm81xx_tptc0__alwon_l3_fast = { 1373 .master = &dm81xx_tptc0_hwmod, 1374 .slave = &dm81xx_alwon_l3_fast_hwmod, 1375 .clk = "sysclk4_ck", 1376 .user = OCP_USER_MPU, 1377 }; 1378 1379 static struct omap_hwmod_class dm81xx_tptc1_hwmod_class = { 1380 .name = "tptc1", 1381 }; 1382 1383 static struct omap_hwmod dm81xx_tptc1_hwmod = { 1384 .name = "tptc1", 1385 .class = &dm81xx_tptc1_hwmod_class, 1386 .clkdm_name = "alwon_l3s_clkdm", 1387 .main_clk = "sysclk4_ck", 1388 .prcm = { 1389 .omap4 = { 1390 .clkctrl_offs = DM81XX_CM_ALWON_TPTC1_CLKCTRL, 1391 .modulemode = MODULEMODE_SWCTRL, 1392 }, 1393 }, 1394 }; 1395 1396 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc1 = { 1397 .master = &dm81xx_alwon_l3_fast_hwmod, 1398 .slave = &dm81xx_tptc1_hwmod, 1399 .clk = "sysclk4_ck", 1400 .user = OCP_USER_MPU, 1401 }; 1402 1403 static struct omap_hwmod_ocp_if dm81xx_tptc1__alwon_l3_fast = { 1404 .master = &dm81xx_tptc1_hwmod, 1405 .slave = &dm81xx_alwon_l3_fast_hwmod, 1406 .clk = "sysclk4_ck", 1407 .user = OCP_USER_MPU, 1408 }; 1409 1410 static struct omap_hwmod_class dm81xx_tptc2_hwmod_class = { 1411 .name = "tptc2", 1412 }; 1413 1414 static struct omap_hwmod dm81xx_tptc2_hwmod = { 1415 .name = "tptc2", 1416 .class = &dm81xx_tptc2_hwmod_class, 1417 .clkdm_name = "alwon_l3s_clkdm", 1418 .main_clk = "sysclk4_ck", 1419 .prcm = { 1420 .omap4 = { 1421 .clkctrl_offs = DM81XX_CM_ALWON_TPTC2_CLKCTRL, 1422 .modulemode = MODULEMODE_SWCTRL, 1423 }, 1424 }, 1425 }; 1426 1427 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc2 = { 1428 .master = &dm81xx_alwon_l3_fast_hwmod, 1429 .slave = &dm81xx_tptc2_hwmod, 1430 .clk = "sysclk4_ck", 1431 .user = OCP_USER_MPU, 1432 }; 1433 1434 static struct omap_hwmod_ocp_if dm81xx_tptc2__alwon_l3_fast = { 1435 .master = &dm81xx_tptc2_hwmod, 1436 .slave = &dm81xx_alwon_l3_fast_hwmod, 1437 .clk = "sysclk4_ck", 1438 .user = OCP_USER_MPU, 1439 }; 1440 1441 static struct omap_hwmod_class dm81xx_tptc3_hwmod_class = { 1442 .name = "tptc3", 1443 }; 1444 1445 static struct omap_hwmod dm81xx_tptc3_hwmod = { 1446 .name = "tptc3", 1447 .class = &dm81xx_tptc3_hwmod_class, 1448 .clkdm_name = "alwon_l3s_clkdm", 1449 .main_clk = "sysclk4_ck", 1450 .prcm = { 1451 .omap4 = { 1452 .clkctrl_offs = DM81XX_CM_ALWON_TPTC3_CLKCTRL, 1453 .modulemode = MODULEMODE_SWCTRL, 1454 }, 1455 }, 1456 }; 1457 1458 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc3 = { 1459 .master = &dm81xx_alwon_l3_fast_hwmod, 1460 .slave = &dm81xx_tptc3_hwmod, 1461 .clk = "sysclk4_ck", 1462 .user = OCP_USER_MPU, 1463 }; 1464 1465 static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = { 1466 .master = &dm81xx_tptc3_hwmod, 1467 .slave = &dm81xx_alwon_l3_fast_hwmod, 1468 .clk = "sysclk4_ck", 1469 .user = OCP_USER_MPU, 1470 }; 1471 1472 /* 1473 * REVISIT: Test and enable the following once clocks work: 1474 * dm81xx_l4_ls__mailbox 1475 * 1476 * Also note that some devices share a single clkctrl_offs.. 1477 * For example, i2c1 and 3 share one, and i2c2 and 4 share one. 1478 */ 1479 static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = { 1480 &dm814x_mpu__alwon_l3_slow, 1481 &dm814x_mpu__alwon_l3_med, 1482 &dm81xx_alwon_l3_slow__l4_ls, 1483 &dm81xx_alwon_l3_slow__l4_hs, 1484 &dm81xx_l4_ls__uart1, 1485 &dm81xx_l4_ls__uart2, 1486 &dm81xx_l4_ls__uart3, 1487 &dm81xx_l4_ls__wd_timer1, 1488 &dm81xx_l4_ls__i2c1, 1489 &dm81xx_l4_ls__i2c2, 1490 &dm81xx_l4_ls__gpio1, 1491 &dm81xx_l4_ls__gpio2, 1492 &dm81xx_l4_ls__gpio3, 1493 &dm81xx_l4_ls__gpio4, 1494 &dm81xx_l4_ls__elm, 1495 &dm81xx_l4_ls__mcspi1, 1496 &dm81xx_l4_ls__mcspi2, 1497 &dm81xx_l4_ls__mcspi3, 1498 &dm81xx_l4_ls__mcspi4, 1499 &dm814x_l4_ls__mmc1, 1500 &dm814x_l4_ls__mmc2, 1501 &ti81xx_l4_ls__rtc, 1502 &dm81xx_alwon_l3_fast__tpcc, 1503 &dm81xx_alwon_l3_fast__tptc0, 1504 &dm81xx_alwon_l3_fast__tptc1, 1505 &dm81xx_alwon_l3_fast__tptc2, 1506 &dm81xx_alwon_l3_fast__tptc3, 1507 &dm81xx_tptc0__alwon_l3_fast, 1508 &dm81xx_tptc1__alwon_l3_fast, 1509 &dm81xx_tptc2__alwon_l3_fast, 1510 &dm81xx_tptc3__alwon_l3_fast, 1511 &dm814x_l4_ls__timer1, 1512 &dm814x_l4_ls__timer2, 1513 &dm814x_l4_hs__cpgmac0, 1514 &dm814x_cpgmac0__mdio, 1515 &dm81xx_alwon_l3_slow__gpmc, 1516 &dm814x_default_l3_slow__usbss, 1517 &dm814x_alwon_l3_med__mmc3, 1518 NULL, 1519 }; 1520 1521 int __init dm814x_hwmod_init(void) 1522 { 1523 omap_hwmod_init(); 1524 return omap_hwmod_register_links(dm814x_hwmod_ocp_ifs); 1525 } 1526 1527 static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = { 1528 &dm816x_mpu__alwon_l3_slow, 1529 &dm816x_mpu__alwon_l3_med, 1530 &dm81xx_alwon_l3_slow__l4_ls, 1531 &dm81xx_alwon_l3_slow__l4_hs, 1532 &dm81xx_l4_ls__uart1, 1533 &dm81xx_l4_ls__uart2, 1534 &dm81xx_l4_ls__uart3, 1535 &dm81xx_l4_ls__wd_timer1, 1536 &dm81xx_l4_ls__i2c1, 1537 &dm81xx_l4_ls__i2c2, 1538 &dm81xx_l4_ls__gpio1, 1539 &dm81xx_l4_ls__gpio2, 1540 &dm81xx_l4_ls__elm, 1541 &ti81xx_l4_ls__rtc, 1542 &dm816x_l4_ls__mmc1, 1543 &dm816x_l4_ls__timer1, 1544 &dm816x_l4_ls__timer2, 1545 &dm816x_l4_ls__timer3, 1546 &dm816x_l4_ls__timer4, 1547 &dm816x_l4_ls__timer5, 1548 &dm816x_l4_ls__timer6, 1549 &dm816x_l4_ls__timer7, 1550 &dm81xx_l4_ls__mcspi1, 1551 &dm81xx_l4_ls__mailbox, 1552 &dm81xx_l4_ls__spinbox, 1553 &dm81xx_l4_hs__emac0, 1554 &dm81xx_emac0__mdio, 1555 &dm816x_l4_hs__emac1, 1556 &dm81xx_l4_hs__sata, 1557 &dm81xx_alwon_l3_fast__tpcc, 1558 &dm81xx_alwon_l3_fast__tptc0, 1559 &dm81xx_alwon_l3_fast__tptc1, 1560 &dm81xx_alwon_l3_fast__tptc2, 1561 &dm81xx_alwon_l3_fast__tptc3, 1562 &dm81xx_tptc0__alwon_l3_fast, 1563 &dm81xx_tptc1__alwon_l3_fast, 1564 &dm81xx_tptc2__alwon_l3_fast, 1565 &dm81xx_tptc3__alwon_l3_fast, 1566 &dm81xx_alwon_l3_slow__gpmc, 1567 &dm816x_default_l3_slow__usbss, 1568 NULL, 1569 }; 1570 1571 int __init dm816x_hwmod_init(void) 1572 { 1573 omap_hwmod_init(); 1574 return omap_hwmod_register_links(dm816x_hwmod_ocp_ifs); 1575 } 1576