1 /* 2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips 3 * 4 * Copyright (C) 2009-2011 Nokia Corporation 5 * Copyright (C) 2012 Texas Instruments, Inc. 6 * Paul Walmsley 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * The data in this file should be completely autogeneratable from 13 * the TI hardware database or other technical documentation. 14 * 15 * XXX these should be marked initdata for multi-OMAP kernels 16 */ 17 18 #include <linux/i2c-omap.h> 19 #include <linux/power/smartreflex.h> 20 #include <linux/platform_data/gpio-omap.h> 21 22 #include <linux/omap-dma.h> 23 #include "l3_3xxx.h" 24 #include "l4_3xxx.h" 25 #include <linux/platform_data/asoc-ti-mcbsp.h> 26 #include <linux/platform_data/spi-omap2-mcspi.h> 27 #include <linux/platform_data/iommu-omap.h> 28 #include <linux/platform_data/mailbox-omap.h> 29 #include <plat/dmtimer.h> 30 31 #include "am35xx.h" 32 33 #include "soc.h" 34 #include "omap_hwmod.h" 35 #include "omap_hwmod_common_data.h" 36 #include "prm-regbits-34xx.h" 37 #include "cm-regbits-34xx.h" 38 39 #include "i2c.h" 40 #include "mmc.h" 41 #include "wd_timer.h" 42 #include "serial.h" 43 44 /* 45 * OMAP3xxx hardware module integration data 46 * 47 * All of the data in this section should be autogeneratable from the 48 * TI hardware database or other technical documentation. Data that 49 * is driver-specific or driver-kernel integration-specific belongs 50 * elsewhere. 51 */ 52 53 /* 54 * IP blocks 55 */ 56 57 /* L3 */ 58 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = { 59 { .irq = 9 + OMAP_INTC_START, }, 60 { .irq = 10 + OMAP_INTC_START, }, 61 { .irq = -1 }, 62 }; 63 64 static struct omap_hwmod omap3xxx_l3_main_hwmod = { 65 .name = "l3_main", 66 .class = &l3_hwmod_class, 67 .mpu_irqs = omap3xxx_l3_main_irqs, 68 .flags = HWMOD_NO_IDLEST, 69 }; 70 71 /* L4 CORE */ 72 static struct omap_hwmod omap3xxx_l4_core_hwmod = { 73 .name = "l4_core", 74 .class = &l4_hwmod_class, 75 .flags = HWMOD_NO_IDLEST, 76 }; 77 78 /* L4 PER */ 79 static struct omap_hwmod omap3xxx_l4_per_hwmod = { 80 .name = "l4_per", 81 .class = &l4_hwmod_class, 82 .flags = HWMOD_NO_IDLEST, 83 }; 84 85 /* L4 WKUP */ 86 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { 87 .name = "l4_wkup", 88 .class = &l4_hwmod_class, 89 .flags = HWMOD_NO_IDLEST, 90 }; 91 92 /* L4 SEC */ 93 static struct omap_hwmod omap3xxx_l4_sec_hwmod = { 94 .name = "l4_sec", 95 .class = &l4_hwmod_class, 96 .flags = HWMOD_NO_IDLEST, 97 }; 98 99 /* MPU */ 100 static struct omap_hwmod_irq_info omap3xxx_mpu_irqs[] = { 101 { .name = "pmu", .irq = 3 + OMAP_INTC_START }, 102 { .irq = -1 } 103 }; 104 105 static struct omap_hwmod omap3xxx_mpu_hwmod = { 106 .name = "mpu", 107 .mpu_irqs = omap3xxx_mpu_irqs, 108 .class = &mpu_hwmod_class, 109 .main_clk = "arm_fck", 110 }; 111 112 /* IVA2 (IVA2) */ 113 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = { 114 { .name = "logic", .rst_shift = 0, .st_shift = 8 }, 115 { .name = "seq0", .rst_shift = 1, .st_shift = 9 }, 116 { .name = "seq1", .rst_shift = 2, .st_shift = 10 }, 117 }; 118 119 static struct omap_hwmod omap3xxx_iva_hwmod = { 120 .name = "iva", 121 .class = &iva_hwmod_class, 122 .clkdm_name = "iva2_clkdm", 123 .rst_lines = omap3xxx_iva_resets, 124 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets), 125 .main_clk = "iva2_ck", 126 .prcm = { 127 .omap2 = { 128 .module_offs = OMAP3430_IVA2_MOD, 129 .prcm_reg_id = 1, 130 .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, 131 .idlest_reg_id = 1, 132 .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT, 133 } 134 }, 135 }; 136 137 /* 138 * 'debugss' class 139 * debug and emulation sub system 140 */ 141 142 static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = { 143 .name = "debugss", 144 }; 145 146 /* debugss */ 147 static struct omap_hwmod omap3xxx_debugss_hwmod = { 148 .name = "debugss", 149 .class = &omap3xxx_debugss_hwmod_class, 150 .clkdm_name = "emu_clkdm", 151 .main_clk = "emu_src_ck", 152 .flags = HWMOD_NO_IDLEST, 153 }; 154 155 /* timer class */ 156 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { 157 .rev_offs = 0x0000, 158 .sysc_offs = 0x0010, 159 .syss_offs = 0x0014, 160 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | 161 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 162 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | 163 SYSS_HAS_RESET_STATUS), 164 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 165 .clockact = CLOCKACT_TEST_ICLK, 166 .sysc_fields = &omap_hwmod_sysc_type1, 167 }; 168 169 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { 170 .name = "timer", 171 .sysc = &omap3xxx_timer_sysc, 172 }; 173 174 /* secure timers dev attribute */ 175 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = { 176 .timer_capability = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE, 177 }; 178 179 /* always-on timers dev attribute */ 180 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { 181 .timer_capability = OMAP_TIMER_ALWON, 182 }; 183 184 /* pwm timers dev attribute */ 185 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { 186 .timer_capability = OMAP_TIMER_HAS_PWM, 187 }; 188 189 /* timers with DSP interrupt dev attribute */ 190 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = { 191 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ, 192 }; 193 194 /* pwm timers with DSP interrupt dev attribute */ 195 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = { 196 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM, 197 }; 198 199 /* timer1 */ 200 static struct omap_hwmod omap3xxx_timer1_hwmod = { 201 .name = "timer1", 202 .mpu_irqs = omap2_timer1_mpu_irqs, 203 .main_clk = "gpt1_fck", 204 .prcm = { 205 .omap2 = { 206 .prcm_reg_id = 1, 207 .module_bit = OMAP3430_EN_GPT1_SHIFT, 208 .module_offs = WKUP_MOD, 209 .idlest_reg_id = 1, 210 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT, 211 }, 212 }, 213 .dev_attr = &capability_alwon_dev_attr, 214 .class = &omap3xxx_timer_hwmod_class, 215 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 216 }; 217 218 /* timer2 */ 219 static struct omap_hwmod omap3xxx_timer2_hwmod = { 220 .name = "timer2", 221 .mpu_irqs = omap2_timer2_mpu_irqs, 222 .main_clk = "gpt2_fck", 223 .prcm = { 224 .omap2 = { 225 .prcm_reg_id = 1, 226 .module_bit = OMAP3430_EN_GPT2_SHIFT, 227 .module_offs = OMAP3430_PER_MOD, 228 .idlest_reg_id = 1, 229 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT, 230 }, 231 }, 232 .class = &omap3xxx_timer_hwmod_class, 233 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 234 }; 235 236 /* timer3 */ 237 static struct omap_hwmod omap3xxx_timer3_hwmod = { 238 .name = "timer3", 239 .mpu_irqs = omap2_timer3_mpu_irqs, 240 .main_clk = "gpt3_fck", 241 .prcm = { 242 .omap2 = { 243 .prcm_reg_id = 1, 244 .module_bit = OMAP3430_EN_GPT3_SHIFT, 245 .module_offs = OMAP3430_PER_MOD, 246 .idlest_reg_id = 1, 247 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT, 248 }, 249 }, 250 .class = &omap3xxx_timer_hwmod_class, 251 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 252 }; 253 254 /* timer4 */ 255 static struct omap_hwmod omap3xxx_timer4_hwmod = { 256 .name = "timer4", 257 .mpu_irqs = omap2_timer4_mpu_irqs, 258 .main_clk = "gpt4_fck", 259 .prcm = { 260 .omap2 = { 261 .prcm_reg_id = 1, 262 .module_bit = OMAP3430_EN_GPT4_SHIFT, 263 .module_offs = OMAP3430_PER_MOD, 264 .idlest_reg_id = 1, 265 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT, 266 }, 267 }, 268 .class = &omap3xxx_timer_hwmod_class, 269 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 270 }; 271 272 /* timer5 */ 273 static struct omap_hwmod omap3xxx_timer5_hwmod = { 274 .name = "timer5", 275 .mpu_irqs = omap2_timer5_mpu_irqs, 276 .main_clk = "gpt5_fck", 277 .prcm = { 278 .omap2 = { 279 .prcm_reg_id = 1, 280 .module_bit = OMAP3430_EN_GPT5_SHIFT, 281 .module_offs = OMAP3430_PER_MOD, 282 .idlest_reg_id = 1, 283 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT, 284 }, 285 }, 286 .dev_attr = &capability_dsp_dev_attr, 287 .class = &omap3xxx_timer_hwmod_class, 288 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 289 }; 290 291 /* timer6 */ 292 static struct omap_hwmod omap3xxx_timer6_hwmod = { 293 .name = "timer6", 294 .mpu_irqs = omap2_timer6_mpu_irqs, 295 .main_clk = "gpt6_fck", 296 .prcm = { 297 .omap2 = { 298 .prcm_reg_id = 1, 299 .module_bit = OMAP3430_EN_GPT6_SHIFT, 300 .module_offs = OMAP3430_PER_MOD, 301 .idlest_reg_id = 1, 302 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT, 303 }, 304 }, 305 .dev_attr = &capability_dsp_dev_attr, 306 .class = &omap3xxx_timer_hwmod_class, 307 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 308 }; 309 310 /* timer7 */ 311 static struct omap_hwmod omap3xxx_timer7_hwmod = { 312 .name = "timer7", 313 .mpu_irqs = omap2_timer7_mpu_irqs, 314 .main_clk = "gpt7_fck", 315 .prcm = { 316 .omap2 = { 317 .prcm_reg_id = 1, 318 .module_bit = OMAP3430_EN_GPT7_SHIFT, 319 .module_offs = OMAP3430_PER_MOD, 320 .idlest_reg_id = 1, 321 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT, 322 }, 323 }, 324 .dev_attr = &capability_dsp_dev_attr, 325 .class = &omap3xxx_timer_hwmod_class, 326 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 327 }; 328 329 /* timer8 */ 330 static struct omap_hwmod omap3xxx_timer8_hwmod = { 331 .name = "timer8", 332 .mpu_irqs = omap2_timer8_mpu_irqs, 333 .main_clk = "gpt8_fck", 334 .prcm = { 335 .omap2 = { 336 .prcm_reg_id = 1, 337 .module_bit = OMAP3430_EN_GPT8_SHIFT, 338 .module_offs = OMAP3430_PER_MOD, 339 .idlest_reg_id = 1, 340 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT, 341 }, 342 }, 343 .dev_attr = &capability_dsp_pwm_dev_attr, 344 .class = &omap3xxx_timer_hwmod_class, 345 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 346 }; 347 348 /* timer9 */ 349 static struct omap_hwmod omap3xxx_timer9_hwmod = { 350 .name = "timer9", 351 .mpu_irqs = omap2_timer9_mpu_irqs, 352 .main_clk = "gpt9_fck", 353 .prcm = { 354 .omap2 = { 355 .prcm_reg_id = 1, 356 .module_bit = OMAP3430_EN_GPT9_SHIFT, 357 .module_offs = OMAP3430_PER_MOD, 358 .idlest_reg_id = 1, 359 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT, 360 }, 361 }, 362 .dev_attr = &capability_pwm_dev_attr, 363 .class = &omap3xxx_timer_hwmod_class, 364 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 365 }; 366 367 /* timer10 */ 368 static struct omap_hwmod omap3xxx_timer10_hwmod = { 369 .name = "timer10", 370 .mpu_irqs = omap2_timer10_mpu_irqs, 371 .main_clk = "gpt10_fck", 372 .prcm = { 373 .omap2 = { 374 .prcm_reg_id = 1, 375 .module_bit = OMAP3430_EN_GPT10_SHIFT, 376 .module_offs = CORE_MOD, 377 .idlest_reg_id = 1, 378 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT, 379 }, 380 }, 381 .dev_attr = &capability_pwm_dev_attr, 382 .class = &omap3xxx_timer_hwmod_class, 383 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 384 }; 385 386 /* timer11 */ 387 static struct omap_hwmod omap3xxx_timer11_hwmod = { 388 .name = "timer11", 389 .mpu_irqs = omap2_timer11_mpu_irqs, 390 .main_clk = "gpt11_fck", 391 .prcm = { 392 .omap2 = { 393 .prcm_reg_id = 1, 394 .module_bit = OMAP3430_EN_GPT11_SHIFT, 395 .module_offs = CORE_MOD, 396 .idlest_reg_id = 1, 397 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT, 398 }, 399 }, 400 .dev_attr = &capability_pwm_dev_attr, 401 .class = &omap3xxx_timer_hwmod_class, 402 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 403 }; 404 405 /* timer12 */ 406 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { 407 { .irq = 95 + OMAP_INTC_START, }, 408 { .irq = -1 }, 409 }; 410 411 static struct omap_hwmod omap3xxx_timer12_hwmod = { 412 .name = "timer12", 413 .mpu_irqs = omap3xxx_timer12_mpu_irqs, 414 .main_clk = "gpt12_fck", 415 .prcm = { 416 .omap2 = { 417 .prcm_reg_id = 1, 418 .module_bit = OMAP3430_EN_GPT12_SHIFT, 419 .module_offs = WKUP_MOD, 420 .idlest_reg_id = 1, 421 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT, 422 }, 423 }, 424 .dev_attr = &capability_secure_dev_attr, 425 .class = &omap3xxx_timer_hwmod_class, 426 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 427 }; 428 429 /* 430 * 'wd_timer' class 431 * 32-bit watchdog upward counter that generates a pulse on the reset pin on 432 * overflow condition 433 */ 434 435 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { 436 .rev_offs = 0x0000, 437 .sysc_offs = 0x0010, 438 .syss_offs = 0x0014, 439 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | 440 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 441 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | 442 SYSS_HAS_RESET_STATUS), 443 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 444 .sysc_fields = &omap_hwmod_sysc_type1, 445 }; 446 447 /* I2C common */ 448 static struct omap_hwmod_class_sysconfig i2c_sysc = { 449 .rev_offs = 0x00, 450 .sysc_offs = 0x20, 451 .syss_offs = 0x10, 452 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 453 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 454 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 455 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 456 .clockact = CLOCKACT_TEST_ICLK, 457 .sysc_fields = &omap_hwmod_sysc_type1, 458 }; 459 460 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { 461 .name = "wd_timer", 462 .sysc = &omap3xxx_wd_timer_sysc, 463 .pre_shutdown = &omap2_wd_timer_disable, 464 .reset = &omap2_wd_timer_reset, 465 }; 466 467 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { 468 .name = "wd_timer2", 469 .class = &omap3xxx_wd_timer_hwmod_class, 470 .main_clk = "wdt2_fck", 471 .prcm = { 472 .omap2 = { 473 .prcm_reg_id = 1, 474 .module_bit = OMAP3430_EN_WDT2_SHIFT, 475 .module_offs = WKUP_MOD, 476 .idlest_reg_id = 1, 477 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, 478 }, 479 }, 480 /* 481 * XXX: Use software supervised mode, HW supervised smartidle seems to 482 * block CORE power domain idle transitions. Maybe a HW bug in wdt2? 483 */ 484 .flags = HWMOD_SWSUP_SIDLE, 485 }; 486 487 /* UART1 */ 488 static struct omap_hwmod omap3xxx_uart1_hwmod = { 489 .name = "uart1", 490 .mpu_irqs = omap2_uart1_mpu_irqs, 491 .sdma_reqs = omap2_uart1_sdma_reqs, 492 .main_clk = "uart1_fck", 493 .flags = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT, 494 .prcm = { 495 .omap2 = { 496 .module_offs = CORE_MOD, 497 .prcm_reg_id = 1, 498 .module_bit = OMAP3430_EN_UART1_SHIFT, 499 .idlest_reg_id = 1, 500 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, 501 }, 502 }, 503 .class = &omap2_uart_class, 504 }; 505 506 /* UART2 */ 507 static struct omap_hwmod omap3xxx_uart2_hwmod = { 508 .name = "uart2", 509 .mpu_irqs = omap2_uart2_mpu_irqs, 510 .sdma_reqs = omap2_uart2_sdma_reqs, 511 .main_clk = "uart2_fck", 512 .flags = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT, 513 .prcm = { 514 .omap2 = { 515 .module_offs = CORE_MOD, 516 .prcm_reg_id = 1, 517 .module_bit = OMAP3430_EN_UART2_SHIFT, 518 .idlest_reg_id = 1, 519 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, 520 }, 521 }, 522 .class = &omap2_uart_class, 523 }; 524 525 /* UART3 */ 526 static struct omap_hwmod omap3xxx_uart3_hwmod = { 527 .name = "uart3", 528 .mpu_irqs = omap2_uart3_mpu_irqs, 529 .sdma_reqs = omap2_uart3_sdma_reqs, 530 .main_clk = "uart3_fck", 531 .flags = DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS | 532 HWMOD_SWSUP_SIDLE_ACT, 533 .prcm = { 534 .omap2 = { 535 .module_offs = OMAP3430_PER_MOD, 536 .prcm_reg_id = 1, 537 .module_bit = OMAP3430_EN_UART3_SHIFT, 538 .idlest_reg_id = 1, 539 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, 540 }, 541 }, 542 .class = &omap2_uart_class, 543 }; 544 545 /* UART4 */ 546 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { 547 { .irq = 80 + OMAP_INTC_START, }, 548 { .irq = -1 }, 549 }; 550 551 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { 552 { .name = "rx", .dma_req = 82, }, 553 { .name = "tx", .dma_req = 81, }, 554 { .dma_req = -1 } 555 }; 556 557 static struct omap_hwmod omap36xx_uart4_hwmod = { 558 .name = "uart4", 559 .mpu_irqs = uart4_mpu_irqs, 560 .sdma_reqs = uart4_sdma_reqs, 561 .main_clk = "uart4_fck", 562 .flags = DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT, 563 .prcm = { 564 .omap2 = { 565 .module_offs = OMAP3430_PER_MOD, 566 .prcm_reg_id = 1, 567 .module_bit = OMAP3630_EN_UART4_SHIFT, 568 .idlest_reg_id = 1, 569 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, 570 }, 571 }, 572 .class = &omap2_uart_class, 573 }; 574 575 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = { 576 { .irq = 84 + OMAP_INTC_START, }, 577 { .irq = -1 }, 578 }; 579 580 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = { 581 { .name = "rx", .dma_req = 55, }, 582 { .name = "tx", .dma_req = 54, }, 583 { .dma_req = -1 } 584 }; 585 586 /* 587 * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or 588 * uart2_fck being enabled. So we add uart1_fck as an optional clock, 589 * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET. This really 590 * should not be needed. The functional clock structure of the AM35xx 591 * UART4 is extremely unclear and opaque; it is unclear what the role 592 * of uart1/2_fck is for the UART4. Any clarification from either 593 * empirical testing or the AM3505/3517 hardware designers would be 594 * most welcome. 595 */ 596 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = { 597 { .role = "softreset_uart1_fck", .clk = "uart1_fck" }, 598 }; 599 600 static struct omap_hwmod am35xx_uart4_hwmod = { 601 .name = "uart4", 602 .mpu_irqs = am35xx_uart4_mpu_irqs, 603 .sdma_reqs = am35xx_uart4_sdma_reqs, 604 .main_clk = "uart4_fck", 605 .prcm = { 606 .omap2 = { 607 .module_offs = CORE_MOD, 608 .prcm_reg_id = 1, 609 .module_bit = AM35XX_EN_UART4_SHIFT, 610 .idlest_reg_id = 1, 611 .idlest_idle_bit = AM35XX_ST_UART4_SHIFT, 612 }, 613 }, 614 .opt_clks = am35xx_uart4_opt_clks, 615 .opt_clks_cnt = ARRAY_SIZE(am35xx_uart4_opt_clks), 616 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 617 .class = &omap2_uart_class, 618 }; 619 620 static struct omap_hwmod_class i2c_class = { 621 .name = "i2c", 622 .sysc = &i2c_sysc, 623 .rev = OMAP_I2C_IP_VERSION_1, 624 .reset = &omap_i2c_reset, 625 }; 626 627 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { 628 { .name = "dispc", .dma_req = 5 }, 629 { .name = "dsi1", .dma_req = 74 }, 630 { .dma_req = -1 } 631 }; 632 633 /* dss */ 634 static struct omap_hwmod_opt_clk dss_opt_clks[] = { 635 /* 636 * The DSS HW needs all DSS clocks enabled during reset. The dss_core 637 * driver does not use these clocks. 638 */ 639 { .role = "sys_clk", .clk = "dss2_alwon_fck" }, 640 { .role = "tv_clk", .clk = "dss_tv_fck" }, 641 /* required only on OMAP3430 */ 642 { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, 643 }; 644 645 static struct omap_hwmod omap3430es1_dss_core_hwmod = { 646 .name = "dss_core", 647 .class = &omap2_dss_hwmod_class, 648 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ 649 .sdma_reqs = omap3xxx_dss_sdma_chs, 650 .prcm = { 651 .omap2 = { 652 .prcm_reg_id = 1, 653 .module_bit = OMAP3430_EN_DSS1_SHIFT, 654 .module_offs = OMAP3430_DSS_MOD, 655 .idlest_reg_id = 1, 656 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT, 657 }, 658 }, 659 .opt_clks = dss_opt_clks, 660 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), 661 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, 662 }; 663 664 static struct omap_hwmod omap3xxx_dss_core_hwmod = { 665 .name = "dss_core", 666 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 667 .class = &omap2_dss_hwmod_class, 668 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ 669 .sdma_reqs = omap3xxx_dss_sdma_chs, 670 .prcm = { 671 .omap2 = { 672 .prcm_reg_id = 1, 673 .module_bit = OMAP3430_EN_DSS1_SHIFT, 674 .module_offs = OMAP3430_DSS_MOD, 675 .idlest_reg_id = 1, 676 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT, 677 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT, 678 }, 679 }, 680 .opt_clks = dss_opt_clks, 681 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), 682 }; 683 684 /* 685 * 'dispc' class 686 * display controller 687 */ 688 689 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = { 690 .rev_offs = 0x0000, 691 .sysc_offs = 0x0010, 692 .syss_offs = 0x0014, 693 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | 694 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | 695 SYSC_HAS_ENAWAKEUP), 696 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 697 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 698 .sysc_fields = &omap_hwmod_sysc_type1, 699 }; 700 701 static struct omap_hwmod_class omap3_dispc_hwmod_class = { 702 .name = "dispc", 703 .sysc = &omap3_dispc_sysc, 704 }; 705 706 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { 707 .name = "dss_dispc", 708 .class = &omap3_dispc_hwmod_class, 709 .mpu_irqs = omap2_dispc_irqs, 710 .main_clk = "dss1_alwon_fck", 711 .prcm = { 712 .omap2 = { 713 .prcm_reg_id = 1, 714 .module_bit = OMAP3430_EN_DSS1_SHIFT, 715 .module_offs = OMAP3430_DSS_MOD, 716 }, 717 }, 718 .flags = HWMOD_NO_IDLEST, 719 .dev_attr = &omap2_3_dss_dispc_dev_attr 720 }; 721 722 /* 723 * 'dsi' class 724 * display serial interface controller 725 */ 726 727 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = { 728 .name = "dsi", 729 }; 730 731 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = { 732 { .irq = 25 + OMAP_INTC_START, }, 733 { .irq = -1 }, 734 }; 735 736 /* dss_dsi1 */ 737 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { 738 { .role = "sys_clk", .clk = "dss2_alwon_fck" }, 739 }; 740 741 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { 742 .name = "dss_dsi1", 743 .class = &omap3xxx_dsi_hwmod_class, 744 .mpu_irqs = omap3xxx_dsi1_irqs, 745 .main_clk = "dss1_alwon_fck", 746 .prcm = { 747 .omap2 = { 748 .prcm_reg_id = 1, 749 .module_bit = OMAP3430_EN_DSS1_SHIFT, 750 .module_offs = OMAP3430_DSS_MOD, 751 }, 752 }, 753 .opt_clks = dss_dsi1_opt_clks, 754 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), 755 .flags = HWMOD_NO_IDLEST, 756 }; 757 758 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { 759 { .role = "ick", .clk = "dss_ick" }, 760 }; 761 762 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { 763 .name = "dss_rfbi", 764 .class = &omap2_rfbi_hwmod_class, 765 .main_clk = "dss1_alwon_fck", 766 .prcm = { 767 .omap2 = { 768 .prcm_reg_id = 1, 769 .module_bit = OMAP3430_EN_DSS1_SHIFT, 770 .module_offs = OMAP3430_DSS_MOD, 771 }, 772 }, 773 .opt_clks = dss_rfbi_opt_clks, 774 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), 775 .flags = HWMOD_NO_IDLEST, 776 }; 777 778 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = { 779 /* required only on OMAP3430 */ 780 { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, 781 }; 782 783 static struct omap_hwmod omap3xxx_dss_venc_hwmod = { 784 .name = "dss_venc", 785 .class = &omap2_venc_hwmod_class, 786 .main_clk = "dss_tv_fck", 787 .prcm = { 788 .omap2 = { 789 .prcm_reg_id = 1, 790 .module_bit = OMAP3430_EN_DSS1_SHIFT, 791 .module_offs = OMAP3430_DSS_MOD, 792 }, 793 }, 794 .opt_clks = dss_venc_opt_clks, 795 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks), 796 .flags = HWMOD_NO_IDLEST, 797 }; 798 799 /* I2C1 */ 800 static struct omap_i2c_dev_attr i2c1_dev_attr = { 801 .fifo_depth = 8, /* bytes */ 802 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2, 803 }; 804 805 static struct omap_hwmod omap3xxx_i2c1_hwmod = { 806 .name = "i2c1", 807 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 808 .mpu_irqs = omap2_i2c1_mpu_irqs, 809 .sdma_reqs = omap2_i2c1_sdma_reqs, 810 .main_clk = "i2c1_fck", 811 .prcm = { 812 .omap2 = { 813 .module_offs = CORE_MOD, 814 .prcm_reg_id = 1, 815 .module_bit = OMAP3430_EN_I2C1_SHIFT, 816 .idlest_reg_id = 1, 817 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT, 818 }, 819 }, 820 .class = &i2c_class, 821 .dev_attr = &i2c1_dev_attr, 822 }; 823 824 /* I2C2 */ 825 static struct omap_i2c_dev_attr i2c2_dev_attr = { 826 .fifo_depth = 8, /* bytes */ 827 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2, 828 }; 829 830 static struct omap_hwmod omap3xxx_i2c2_hwmod = { 831 .name = "i2c2", 832 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 833 .mpu_irqs = omap2_i2c2_mpu_irqs, 834 .sdma_reqs = omap2_i2c2_sdma_reqs, 835 .main_clk = "i2c2_fck", 836 .prcm = { 837 .omap2 = { 838 .module_offs = CORE_MOD, 839 .prcm_reg_id = 1, 840 .module_bit = OMAP3430_EN_I2C2_SHIFT, 841 .idlest_reg_id = 1, 842 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT, 843 }, 844 }, 845 .class = &i2c_class, 846 .dev_attr = &i2c2_dev_attr, 847 }; 848 849 /* I2C3 */ 850 static struct omap_i2c_dev_attr i2c3_dev_attr = { 851 .fifo_depth = 64, /* bytes */ 852 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2, 853 }; 854 855 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { 856 { .irq = 61 + OMAP_INTC_START, }, 857 { .irq = -1 }, 858 }; 859 860 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { 861 { .name = "tx", .dma_req = 25 }, 862 { .name = "rx", .dma_req = 26 }, 863 { .dma_req = -1 } 864 }; 865 866 static struct omap_hwmod omap3xxx_i2c3_hwmod = { 867 .name = "i2c3", 868 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 869 .mpu_irqs = i2c3_mpu_irqs, 870 .sdma_reqs = i2c3_sdma_reqs, 871 .main_clk = "i2c3_fck", 872 .prcm = { 873 .omap2 = { 874 .module_offs = CORE_MOD, 875 .prcm_reg_id = 1, 876 .module_bit = OMAP3430_EN_I2C3_SHIFT, 877 .idlest_reg_id = 1, 878 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT, 879 }, 880 }, 881 .class = &i2c_class, 882 .dev_attr = &i2c3_dev_attr, 883 }; 884 885 /* 886 * 'gpio' class 887 * general purpose io module 888 */ 889 890 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = { 891 .rev_offs = 0x0000, 892 .sysc_offs = 0x0010, 893 .syss_offs = 0x0014, 894 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | 895 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | 896 SYSS_HAS_RESET_STATUS), 897 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 898 .sysc_fields = &omap_hwmod_sysc_type1, 899 }; 900 901 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = { 902 .name = "gpio", 903 .sysc = &omap3xxx_gpio_sysc, 904 .rev = 1, 905 }; 906 907 /* gpio_dev_attr */ 908 static struct omap_gpio_dev_attr gpio_dev_attr = { 909 .bank_width = 32, 910 .dbck_flag = true, 911 }; 912 913 /* gpio1 */ 914 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { 915 { .role = "dbclk", .clk = "gpio1_dbck", }, 916 }; 917 918 static struct omap_hwmod omap3xxx_gpio1_hwmod = { 919 .name = "gpio1", 920 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 921 .mpu_irqs = omap2_gpio1_irqs, 922 .main_clk = "gpio1_ick", 923 .opt_clks = gpio1_opt_clks, 924 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), 925 .prcm = { 926 .omap2 = { 927 .prcm_reg_id = 1, 928 .module_bit = OMAP3430_EN_GPIO1_SHIFT, 929 .module_offs = WKUP_MOD, 930 .idlest_reg_id = 1, 931 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT, 932 }, 933 }, 934 .class = &omap3xxx_gpio_hwmod_class, 935 .dev_attr = &gpio_dev_attr, 936 }; 937 938 /* gpio2 */ 939 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { 940 { .role = "dbclk", .clk = "gpio2_dbck", }, 941 }; 942 943 static struct omap_hwmod omap3xxx_gpio2_hwmod = { 944 .name = "gpio2", 945 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 946 .mpu_irqs = omap2_gpio2_irqs, 947 .main_clk = "gpio2_ick", 948 .opt_clks = gpio2_opt_clks, 949 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), 950 .prcm = { 951 .omap2 = { 952 .prcm_reg_id = 1, 953 .module_bit = OMAP3430_EN_GPIO2_SHIFT, 954 .module_offs = OMAP3430_PER_MOD, 955 .idlest_reg_id = 1, 956 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT, 957 }, 958 }, 959 .class = &omap3xxx_gpio_hwmod_class, 960 .dev_attr = &gpio_dev_attr, 961 }; 962 963 /* gpio3 */ 964 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { 965 { .role = "dbclk", .clk = "gpio3_dbck", }, 966 }; 967 968 static struct omap_hwmod omap3xxx_gpio3_hwmod = { 969 .name = "gpio3", 970 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 971 .mpu_irqs = omap2_gpio3_irqs, 972 .main_clk = "gpio3_ick", 973 .opt_clks = gpio3_opt_clks, 974 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), 975 .prcm = { 976 .omap2 = { 977 .prcm_reg_id = 1, 978 .module_bit = OMAP3430_EN_GPIO3_SHIFT, 979 .module_offs = OMAP3430_PER_MOD, 980 .idlest_reg_id = 1, 981 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT, 982 }, 983 }, 984 .class = &omap3xxx_gpio_hwmod_class, 985 .dev_attr = &gpio_dev_attr, 986 }; 987 988 /* gpio4 */ 989 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { 990 { .role = "dbclk", .clk = "gpio4_dbck", }, 991 }; 992 993 static struct omap_hwmod omap3xxx_gpio4_hwmod = { 994 .name = "gpio4", 995 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 996 .mpu_irqs = omap2_gpio4_irqs, 997 .main_clk = "gpio4_ick", 998 .opt_clks = gpio4_opt_clks, 999 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), 1000 .prcm = { 1001 .omap2 = { 1002 .prcm_reg_id = 1, 1003 .module_bit = OMAP3430_EN_GPIO4_SHIFT, 1004 .module_offs = OMAP3430_PER_MOD, 1005 .idlest_reg_id = 1, 1006 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT, 1007 }, 1008 }, 1009 .class = &omap3xxx_gpio_hwmod_class, 1010 .dev_attr = &gpio_dev_attr, 1011 }; 1012 1013 /* gpio5 */ 1014 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = { 1015 { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */ 1016 { .irq = -1 }, 1017 }; 1018 1019 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { 1020 { .role = "dbclk", .clk = "gpio5_dbck", }, 1021 }; 1022 1023 static struct omap_hwmod omap3xxx_gpio5_hwmod = { 1024 .name = "gpio5", 1025 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1026 .mpu_irqs = omap3xxx_gpio5_irqs, 1027 .main_clk = "gpio5_ick", 1028 .opt_clks = gpio5_opt_clks, 1029 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), 1030 .prcm = { 1031 .omap2 = { 1032 .prcm_reg_id = 1, 1033 .module_bit = OMAP3430_EN_GPIO5_SHIFT, 1034 .module_offs = OMAP3430_PER_MOD, 1035 .idlest_reg_id = 1, 1036 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT, 1037 }, 1038 }, 1039 .class = &omap3xxx_gpio_hwmod_class, 1040 .dev_attr = &gpio_dev_attr, 1041 }; 1042 1043 /* gpio6 */ 1044 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = { 1045 { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */ 1046 { .irq = -1 }, 1047 }; 1048 1049 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { 1050 { .role = "dbclk", .clk = "gpio6_dbck", }, 1051 }; 1052 1053 static struct omap_hwmod omap3xxx_gpio6_hwmod = { 1054 .name = "gpio6", 1055 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1056 .mpu_irqs = omap3xxx_gpio6_irqs, 1057 .main_clk = "gpio6_ick", 1058 .opt_clks = gpio6_opt_clks, 1059 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), 1060 .prcm = { 1061 .omap2 = { 1062 .prcm_reg_id = 1, 1063 .module_bit = OMAP3430_EN_GPIO6_SHIFT, 1064 .module_offs = OMAP3430_PER_MOD, 1065 .idlest_reg_id = 1, 1066 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT, 1067 }, 1068 }, 1069 .class = &omap3xxx_gpio_hwmod_class, 1070 .dev_attr = &gpio_dev_attr, 1071 }; 1072 1073 /* dma attributes */ 1074 static struct omap_dma_dev_attr dma_dev_attr = { 1075 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | 1076 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, 1077 .lch_count = 32, 1078 }; 1079 1080 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = { 1081 .rev_offs = 0x0000, 1082 .sysc_offs = 0x002c, 1083 .syss_offs = 0x0028, 1084 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 1085 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | 1086 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | 1087 SYSS_HAS_RESET_STATUS), 1088 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 1089 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 1090 .sysc_fields = &omap_hwmod_sysc_type1, 1091 }; 1092 1093 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = { 1094 .name = "dma", 1095 .sysc = &omap3xxx_dma_sysc, 1096 }; 1097 1098 /* dma_system */ 1099 static struct omap_hwmod omap3xxx_dma_system_hwmod = { 1100 .name = "dma", 1101 .class = &omap3xxx_dma_hwmod_class, 1102 .mpu_irqs = omap2_dma_system_irqs, 1103 .main_clk = "core_l3_ick", 1104 .prcm = { 1105 .omap2 = { 1106 .module_offs = CORE_MOD, 1107 .prcm_reg_id = 1, 1108 .module_bit = OMAP3430_ST_SDMA_SHIFT, 1109 .idlest_reg_id = 1, 1110 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT, 1111 }, 1112 }, 1113 .dev_attr = &dma_dev_attr, 1114 .flags = HWMOD_NO_IDLEST, 1115 }; 1116 1117 /* 1118 * 'mcbsp' class 1119 * multi channel buffered serial port controller 1120 */ 1121 1122 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = { 1123 .sysc_offs = 0x008c, 1124 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | 1125 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), 1126 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1127 .sysc_fields = &omap_hwmod_sysc_type1, 1128 .clockact = 0x2, 1129 }; 1130 1131 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = { 1132 .name = "mcbsp", 1133 .sysc = &omap3xxx_mcbsp_sysc, 1134 .rev = MCBSP_CONFIG_TYPE3, 1135 }; 1136 1137 /* McBSP functional clock mapping */ 1138 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = { 1139 { .role = "pad_fck", .clk = "mcbsp_clks" }, 1140 { .role = "prcm_fck", .clk = "core_96m_fck" }, 1141 }; 1142 1143 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = { 1144 { .role = "pad_fck", .clk = "mcbsp_clks" }, 1145 { .role = "prcm_fck", .clk = "per_96m_fck" }, 1146 }; 1147 1148 /* mcbsp1 */ 1149 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { 1150 { .name = "common", .irq = 16 + OMAP_INTC_START, }, 1151 { .name = "tx", .irq = 59 + OMAP_INTC_START, }, 1152 { .name = "rx", .irq = 60 + OMAP_INTC_START, }, 1153 { .irq = -1 }, 1154 }; 1155 1156 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { 1157 .name = "mcbsp1", 1158 .class = &omap3xxx_mcbsp_hwmod_class, 1159 .mpu_irqs = omap3xxx_mcbsp1_irqs, 1160 .sdma_reqs = omap2_mcbsp1_sdma_reqs, 1161 .main_clk = "mcbsp1_fck", 1162 .prcm = { 1163 .omap2 = { 1164 .prcm_reg_id = 1, 1165 .module_bit = OMAP3430_EN_MCBSP1_SHIFT, 1166 .module_offs = CORE_MOD, 1167 .idlest_reg_id = 1, 1168 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, 1169 }, 1170 }, 1171 .opt_clks = mcbsp15_opt_clks, 1172 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks), 1173 }; 1174 1175 /* mcbsp2 */ 1176 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = { 1177 { .name = "common", .irq = 17 + OMAP_INTC_START, }, 1178 { .name = "tx", .irq = 62 + OMAP_INTC_START, }, 1179 { .name = "rx", .irq = 63 + OMAP_INTC_START, }, 1180 { .irq = -1 }, 1181 }; 1182 1183 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { 1184 .sidetone = "mcbsp2_sidetone", 1185 }; 1186 1187 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { 1188 .name = "mcbsp2", 1189 .class = &omap3xxx_mcbsp_hwmod_class, 1190 .mpu_irqs = omap3xxx_mcbsp2_irqs, 1191 .sdma_reqs = omap2_mcbsp2_sdma_reqs, 1192 .main_clk = "mcbsp2_fck", 1193 .prcm = { 1194 .omap2 = { 1195 .prcm_reg_id = 1, 1196 .module_bit = OMAP3430_EN_MCBSP2_SHIFT, 1197 .module_offs = OMAP3430_PER_MOD, 1198 .idlest_reg_id = 1, 1199 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, 1200 }, 1201 }, 1202 .opt_clks = mcbsp234_opt_clks, 1203 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), 1204 .dev_attr = &omap34xx_mcbsp2_dev_attr, 1205 }; 1206 1207 /* mcbsp3 */ 1208 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = { 1209 { .name = "common", .irq = 22 + OMAP_INTC_START, }, 1210 { .name = "tx", .irq = 89 + OMAP_INTC_START, }, 1211 { .name = "rx", .irq = 90 + OMAP_INTC_START, }, 1212 { .irq = -1 }, 1213 }; 1214 1215 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { 1216 .sidetone = "mcbsp3_sidetone", 1217 }; 1218 1219 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { 1220 .name = "mcbsp3", 1221 .class = &omap3xxx_mcbsp_hwmod_class, 1222 .mpu_irqs = omap3xxx_mcbsp3_irqs, 1223 .sdma_reqs = omap2_mcbsp3_sdma_reqs, 1224 .main_clk = "mcbsp3_fck", 1225 .prcm = { 1226 .omap2 = { 1227 .prcm_reg_id = 1, 1228 .module_bit = OMAP3430_EN_MCBSP3_SHIFT, 1229 .module_offs = OMAP3430_PER_MOD, 1230 .idlest_reg_id = 1, 1231 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, 1232 }, 1233 }, 1234 .opt_clks = mcbsp234_opt_clks, 1235 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), 1236 .dev_attr = &omap34xx_mcbsp3_dev_attr, 1237 }; 1238 1239 /* mcbsp4 */ 1240 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = { 1241 { .name = "common", .irq = 23 + OMAP_INTC_START, }, 1242 { .name = "tx", .irq = 54 + OMAP_INTC_START, }, 1243 { .name = "rx", .irq = 55 + OMAP_INTC_START, }, 1244 { .irq = -1 }, 1245 }; 1246 1247 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = { 1248 { .name = "rx", .dma_req = 20 }, 1249 { .name = "tx", .dma_req = 19 }, 1250 { .dma_req = -1 } 1251 }; 1252 1253 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { 1254 .name = "mcbsp4", 1255 .class = &omap3xxx_mcbsp_hwmod_class, 1256 .mpu_irqs = omap3xxx_mcbsp4_irqs, 1257 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs, 1258 .main_clk = "mcbsp4_fck", 1259 .prcm = { 1260 .omap2 = { 1261 .prcm_reg_id = 1, 1262 .module_bit = OMAP3430_EN_MCBSP4_SHIFT, 1263 .module_offs = OMAP3430_PER_MOD, 1264 .idlest_reg_id = 1, 1265 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, 1266 }, 1267 }, 1268 .opt_clks = mcbsp234_opt_clks, 1269 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), 1270 }; 1271 1272 /* mcbsp5 */ 1273 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = { 1274 { .name = "common", .irq = 27 + OMAP_INTC_START, }, 1275 { .name = "tx", .irq = 81 + OMAP_INTC_START, }, 1276 { .name = "rx", .irq = 82 + OMAP_INTC_START, }, 1277 { .irq = -1 }, 1278 }; 1279 1280 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = { 1281 { .name = "rx", .dma_req = 22 }, 1282 { .name = "tx", .dma_req = 21 }, 1283 { .dma_req = -1 } 1284 }; 1285 1286 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { 1287 .name = "mcbsp5", 1288 .class = &omap3xxx_mcbsp_hwmod_class, 1289 .mpu_irqs = omap3xxx_mcbsp5_irqs, 1290 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs, 1291 .main_clk = "mcbsp5_fck", 1292 .prcm = { 1293 .omap2 = { 1294 .prcm_reg_id = 1, 1295 .module_bit = OMAP3430_EN_MCBSP5_SHIFT, 1296 .module_offs = CORE_MOD, 1297 .idlest_reg_id = 1, 1298 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, 1299 }, 1300 }, 1301 .opt_clks = mcbsp15_opt_clks, 1302 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks), 1303 }; 1304 1305 /* 'mcbsp sidetone' class */ 1306 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = { 1307 .sysc_offs = 0x0010, 1308 .sysc_flags = SYSC_HAS_AUTOIDLE, 1309 .sysc_fields = &omap_hwmod_sysc_type1, 1310 }; 1311 1312 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = { 1313 .name = "mcbsp_sidetone", 1314 .sysc = &omap3xxx_mcbsp_sidetone_sysc, 1315 }; 1316 1317 /* mcbsp2_sidetone */ 1318 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = { 1319 { .name = "irq", .irq = 4 + OMAP_INTC_START, }, 1320 { .irq = -1 }, 1321 }; 1322 1323 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { 1324 .name = "mcbsp2_sidetone", 1325 .class = &omap3xxx_mcbsp_sidetone_hwmod_class, 1326 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs, 1327 .main_clk = "mcbsp2_fck", 1328 .prcm = { 1329 .omap2 = { 1330 .prcm_reg_id = 1, 1331 .module_bit = OMAP3430_EN_MCBSP2_SHIFT, 1332 .module_offs = OMAP3430_PER_MOD, 1333 .idlest_reg_id = 1, 1334 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, 1335 }, 1336 }, 1337 }; 1338 1339 /* mcbsp3_sidetone */ 1340 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = { 1341 { .name = "irq", .irq = 5 + OMAP_INTC_START, }, 1342 { .irq = -1 }, 1343 }; 1344 1345 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { 1346 .name = "mcbsp3_sidetone", 1347 .class = &omap3xxx_mcbsp_sidetone_hwmod_class, 1348 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs, 1349 .main_clk = "mcbsp3_fck", 1350 .prcm = { 1351 .omap2 = { 1352 .prcm_reg_id = 1, 1353 .module_bit = OMAP3430_EN_MCBSP3_SHIFT, 1354 .module_offs = OMAP3430_PER_MOD, 1355 .idlest_reg_id = 1, 1356 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, 1357 }, 1358 }, 1359 }; 1360 1361 /* SR common */ 1362 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { 1363 .clkact_shift = 20, 1364 }; 1365 1366 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = { 1367 .sysc_offs = 0x24, 1368 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE), 1369 .clockact = CLOCKACT_TEST_ICLK, 1370 .sysc_fields = &omap34xx_sr_sysc_fields, 1371 }; 1372 1373 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = { 1374 .name = "smartreflex", 1375 .sysc = &omap34xx_sr_sysc, 1376 .rev = 1, 1377 }; 1378 1379 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = { 1380 .sidle_shift = 24, 1381 .enwkup_shift = 26, 1382 }; 1383 1384 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = { 1385 .sysc_offs = 0x38, 1386 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1387 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | 1388 SYSC_NO_CACHE), 1389 .sysc_fields = &omap36xx_sr_sysc_fields, 1390 }; 1391 1392 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = { 1393 .name = "smartreflex", 1394 .sysc = &omap36xx_sr_sysc, 1395 .rev = 2, 1396 }; 1397 1398 /* SR1 */ 1399 static struct omap_smartreflex_dev_attr sr1_dev_attr = { 1400 .sensor_voltdm_name = "mpu_iva", 1401 }; 1402 1403 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = { 1404 { .irq = 18 + OMAP_INTC_START, }, 1405 { .irq = -1 }, 1406 }; 1407 1408 static struct omap_hwmod omap34xx_sr1_hwmod = { 1409 .name = "smartreflex_mpu_iva", 1410 .class = &omap34xx_smartreflex_hwmod_class, 1411 .main_clk = "sr1_fck", 1412 .prcm = { 1413 .omap2 = { 1414 .prcm_reg_id = 1, 1415 .module_bit = OMAP3430_EN_SR1_SHIFT, 1416 .module_offs = WKUP_MOD, 1417 .idlest_reg_id = 1, 1418 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, 1419 }, 1420 }, 1421 .dev_attr = &sr1_dev_attr, 1422 .mpu_irqs = omap3_smartreflex_mpu_irqs, 1423 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 1424 }; 1425 1426 static struct omap_hwmod omap36xx_sr1_hwmod = { 1427 .name = "smartreflex_mpu_iva", 1428 .class = &omap36xx_smartreflex_hwmod_class, 1429 .main_clk = "sr1_fck", 1430 .prcm = { 1431 .omap2 = { 1432 .prcm_reg_id = 1, 1433 .module_bit = OMAP3430_EN_SR1_SHIFT, 1434 .module_offs = WKUP_MOD, 1435 .idlest_reg_id = 1, 1436 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, 1437 }, 1438 }, 1439 .dev_attr = &sr1_dev_attr, 1440 .mpu_irqs = omap3_smartreflex_mpu_irqs, 1441 }; 1442 1443 /* SR2 */ 1444 static struct omap_smartreflex_dev_attr sr2_dev_attr = { 1445 .sensor_voltdm_name = "core", 1446 }; 1447 1448 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = { 1449 { .irq = 19 + OMAP_INTC_START, }, 1450 { .irq = -1 }, 1451 }; 1452 1453 static struct omap_hwmod omap34xx_sr2_hwmod = { 1454 .name = "smartreflex_core", 1455 .class = &omap34xx_smartreflex_hwmod_class, 1456 .main_clk = "sr2_fck", 1457 .prcm = { 1458 .omap2 = { 1459 .prcm_reg_id = 1, 1460 .module_bit = OMAP3430_EN_SR2_SHIFT, 1461 .module_offs = WKUP_MOD, 1462 .idlest_reg_id = 1, 1463 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, 1464 }, 1465 }, 1466 .dev_attr = &sr2_dev_attr, 1467 .mpu_irqs = omap3_smartreflex_core_irqs, 1468 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 1469 }; 1470 1471 static struct omap_hwmod omap36xx_sr2_hwmod = { 1472 .name = "smartreflex_core", 1473 .class = &omap36xx_smartreflex_hwmod_class, 1474 .main_clk = "sr2_fck", 1475 .prcm = { 1476 .omap2 = { 1477 .prcm_reg_id = 1, 1478 .module_bit = OMAP3430_EN_SR2_SHIFT, 1479 .module_offs = WKUP_MOD, 1480 .idlest_reg_id = 1, 1481 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, 1482 }, 1483 }, 1484 .dev_attr = &sr2_dev_attr, 1485 .mpu_irqs = omap3_smartreflex_core_irqs, 1486 }; 1487 1488 /* 1489 * 'mailbox' class 1490 * mailbox module allowing communication between the on-chip processors 1491 * using a queued mailbox-interrupt mechanism. 1492 */ 1493 1494 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = { 1495 .rev_offs = 0x000, 1496 .sysc_offs = 0x010, 1497 .syss_offs = 0x014, 1498 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1499 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), 1500 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1501 .sysc_fields = &omap_hwmod_sysc_type1, 1502 }; 1503 1504 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = { 1505 .name = "mailbox", 1506 .sysc = &omap3xxx_mailbox_sysc, 1507 }; 1508 1509 static struct omap_mbox_dev_info omap3xxx_mailbox_info[] = { 1510 { .name = "dsp", .tx_id = 0, .rx_id = 1 }, 1511 }; 1512 1513 static struct omap_mbox_pdata omap3xxx_mailbox_attrs = { 1514 .num_users = 2, 1515 .num_fifos = 2, 1516 .info_cnt = ARRAY_SIZE(omap3xxx_mailbox_info), 1517 .info = omap3xxx_mailbox_info, 1518 }; 1519 1520 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { 1521 { .irq = 26 + OMAP_INTC_START, }, 1522 { .irq = -1 }, 1523 }; 1524 1525 static struct omap_hwmod omap3xxx_mailbox_hwmod = { 1526 .name = "mailbox", 1527 .class = &omap3xxx_mailbox_hwmod_class, 1528 .mpu_irqs = omap3xxx_mailbox_irqs, 1529 .main_clk = "mailboxes_ick", 1530 .prcm = { 1531 .omap2 = { 1532 .prcm_reg_id = 1, 1533 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT, 1534 .module_offs = CORE_MOD, 1535 .idlest_reg_id = 1, 1536 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT, 1537 }, 1538 }, 1539 .dev_attr = &omap3xxx_mailbox_attrs, 1540 }; 1541 1542 /* 1543 * 'mcspi' class 1544 * multichannel serial port interface (mcspi) / master/slave synchronous serial 1545 * bus 1546 */ 1547 1548 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = { 1549 .rev_offs = 0x0000, 1550 .sysc_offs = 0x0010, 1551 .syss_offs = 0x0014, 1552 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1553 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 1554 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 1555 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1556 .sysc_fields = &omap_hwmod_sysc_type1, 1557 }; 1558 1559 static struct omap_hwmod_class omap34xx_mcspi_class = { 1560 .name = "mcspi", 1561 .sysc = &omap34xx_mcspi_sysc, 1562 .rev = OMAP3_MCSPI_REV, 1563 }; 1564 1565 /* mcspi1 */ 1566 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { 1567 .num_chipselect = 4, 1568 }; 1569 1570 static struct omap_hwmod omap34xx_mcspi1 = { 1571 .name = "mcspi1", 1572 .mpu_irqs = omap2_mcspi1_mpu_irqs, 1573 .sdma_reqs = omap2_mcspi1_sdma_reqs, 1574 .main_clk = "mcspi1_fck", 1575 .prcm = { 1576 .omap2 = { 1577 .module_offs = CORE_MOD, 1578 .prcm_reg_id = 1, 1579 .module_bit = OMAP3430_EN_MCSPI1_SHIFT, 1580 .idlest_reg_id = 1, 1581 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT, 1582 }, 1583 }, 1584 .class = &omap34xx_mcspi_class, 1585 .dev_attr = &omap_mcspi1_dev_attr, 1586 }; 1587 1588 /* mcspi2 */ 1589 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { 1590 .num_chipselect = 2, 1591 }; 1592 1593 static struct omap_hwmod omap34xx_mcspi2 = { 1594 .name = "mcspi2", 1595 .mpu_irqs = omap2_mcspi2_mpu_irqs, 1596 .sdma_reqs = omap2_mcspi2_sdma_reqs, 1597 .main_clk = "mcspi2_fck", 1598 .prcm = { 1599 .omap2 = { 1600 .module_offs = CORE_MOD, 1601 .prcm_reg_id = 1, 1602 .module_bit = OMAP3430_EN_MCSPI2_SHIFT, 1603 .idlest_reg_id = 1, 1604 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT, 1605 }, 1606 }, 1607 .class = &omap34xx_mcspi_class, 1608 .dev_attr = &omap_mcspi2_dev_attr, 1609 }; 1610 1611 /* mcspi3 */ 1612 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = { 1613 { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */ 1614 { .irq = -1 }, 1615 }; 1616 1617 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = { 1618 { .name = "tx0", .dma_req = 15 }, 1619 { .name = "rx0", .dma_req = 16 }, 1620 { .name = "tx1", .dma_req = 23 }, 1621 { .name = "rx1", .dma_req = 24 }, 1622 { .dma_req = -1 } 1623 }; 1624 1625 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { 1626 .num_chipselect = 2, 1627 }; 1628 1629 static struct omap_hwmod omap34xx_mcspi3 = { 1630 .name = "mcspi3", 1631 .mpu_irqs = omap34xx_mcspi3_mpu_irqs, 1632 .sdma_reqs = omap34xx_mcspi3_sdma_reqs, 1633 .main_clk = "mcspi3_fck", 1634 .prcm = { 1635 .omap2 = { 1636 .module_offs = CORE_MOD, 1637 .prcm_reg_id = 1, 1638 .module_bit = OMAP3430_EN_MCSPI3_SHIFT, 1639 .idlest_reg_id = 1, 1640 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT, 1641 }, 1642 }, 1643 .class = &omap34xx_mcspi_class, 1644 .dev_attr = &omap_mcspi3_dev_attr, 1645 }; 1646 1647 /* mcspi4 */ 1648 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { 1649 { .name = "irq", .irq = 48 + OMAP_INTC_START, }, 1650 { .irq = -1 }, 1651 }; 1652 1653 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = { 1654 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */ 1655 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */ 1656 { .dma_req = -1 } 1657 }; 1658 1659 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { 1660 .num_chipselect = 1, 1661 }; 1662 1663 static struct omap_hwmod omap34xx_mcspi4 = { 1664 .name = "mcspi4", 1665 .mpu_irqs = omap34xx_mcspi4_mpu_irqs, 1666 .sdma_reqs = omap34xx_mcspi4_sdma_reqs, 1667 .main_clk = "mcspi4_fck", 1668 .prcm = { 1669 .omap2 = { 1670 .module_offs = CORE_MOD, 1671 .prcm_reg_id = 1, 1672 .module_bit = OMAP3430_EN_MCSPI4_SHIFT, 1673 .idlest_reg_id = 1, 1674 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT, 1675 }, 1676 }, 1677 .class = &omap34xx_mcspi_class, 1678 .dev_attr = &omap_mcspi4_dev_attr, 1679 }; 1680 1681 /* usbhsotg */ 1682 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = { 1683 .rev_offs = 0x0400, 1684 .sysc_offs = 0x0404, 1685 .syss_offs = 0x0408, 1686 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| 1687 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 1688 SYSC_HAS_AUTOIDLE), 1689 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 1690 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 1691 .sysc_fields = &omap_hwmod_sysc_type1, 1692 }; 1693 1694 static struct omap_hwmod_class usbotg_class = { 1695 .name = "usbotg", 1696 .sysc = &omap3xxx_usbhsotg_sysc, 1697 }; 1698 1699 /* usb_otg_hs */ 1700 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = { 1701 1702 { .name = "mc", .irq = 92 + OMAP_INTC_START, }, 1703 { .name = "dma", .irq = 93 + OMAP_INTC_START, }, 1704 { .irq = -1 }, 1705 }; 1706 1707 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { 1708 .name = "usb_otg_hs", 1709 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs, 1710 .main_clk = "hsotgusb_ick", 1711 .prcm = { 1712 .omap2 = { 1713 .prcm_reg_id = 1, 1714 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT, 1715 .module_offs = CORE_MOD, 1716 .idlest_reg_id = 1, 1717 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT, 1718 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT 1719 }, 1720 }, 1721 .class = &usbotg_class, 1722 1723 /* 1724 * Erratum ID: i479 idle_req / idle_ack mechanism potentially 1725 * broken when autoidle is enabled 1726 * workaround is to disable the autoidle bit at module level. 1727 * 1728 * Enabling the device in any other MIDLEMODE setting but force-idle 1729 * causes core_pwrdm not enter idle states at least on OMAP3630. 1730 * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY 1731 * signal when MIDLEMODE is set to force-idle. 1732 */ 1733 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE 1734 | HWMOD_FORCE_MSTANDBY, 1735 }; 1736 1737 /* usb_otg_hs */ 1738 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { 1739 { .name = "mc", .irq = 71 + OMAP_INTC_START, }, 1740 { .irq = -1 }, 1741 }; 1742 1743 static struct omap_hwmod_class am35xx_usbotg_class = { 1744 .name = "am35xx_usbotg", 1745 }; 1746 1747 static struct omap_hwmod am35xx_usbhsotg_hwmod = { 1748 .name = "am35x_otg_hs", 1749 .mpu_irqs = am35xx_usbhsotg_mpu_irqs, 1750 .main_clk = "hsotgusb_fck", 1751 .class = &am35xx_usbotg_class, 1752 .flags = HWMOD_NO_IDLEST, 1753 }; 1754 1755 /* MMC/SD/SDIO common */ 1756 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = { 1757 .rev_offs = 0x1fc, 1758 .sysc_offs = 0x10, 1759 .syss_offs = 0x14, 1760 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1761 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 1762 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 1763 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1764 .sysc_fields = &omap_hwmod_sysc_type1, 1765 }; 1766 1767 static struct omap_hwmod_class omap34xx_mmc_class = { 1768 .name = "mmc", 1769 .sysc = &omap34xx_mmc_sysc, 1770 }; 1771 1772 /* MMC/SD/SDIO1 */ 1773 1774 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = { 1775 { .irq = 83 + OMAP_INTC_START, }, 1776 { .irq = -1 }, 1777 }; 1778 1779 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = { 1780 { .name = "tx", .dma_req = 61, }, 1781 { .name = "rx", .dma_req = 62, }, 1782 { .dma_req = -1 } 1783 }; 1784 1785 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = { 1786 { .role = "dbck", .clk = "omap_32k_fck", }, 1787 }; 1788 1789 static struct omap_mmc_dev_attr mmc1_dev_attr = { 1790 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, 1791 }; 1792 1793 /* See 35xx errata 2.1.1.128 in SPRZ278F */ 1794 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = { 1795 .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT | 1796 OMAP_HSMMC_BROKEN_MULTIBLOCK_READ), 1797 }; 1798 1799 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = { 1800 .name = "mmc1", 1801 .mpu_irqs = omap34xx_mmc1_mpu_irqs, 1802 .sdma_reqs = omap34xx_mmc1_sdma_reqs, 1803 .opt_clks = omap34xx_mmc1_opt_clks, 1804 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), 1805 .main_clk = "mmchs1_fck", 1806 .prcm = { 1807 .omap2 = { 1808 .module_offs = CORE_MOD, 1809 .prcm_reg_id = 1, 1810 .module_bit = OMAP3430_EN_MMC1_SHIFT, 1811 .idlest_reg_id = 1, 1812 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, 1813 }, 1814 }, 1815 .dev_attr = &mmc1_pre_es3_dev_attr, 1816 .class = &omap34xx_mmc_class, 1817 }; 1818 1819 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = { 1820 .name = "mmc1", 1821 .mpu_irqs = omap34xx_mmc1_mpu_irqs, 1822 .sdma_reqs = omap34xx_mmc1_sdma_reqs, 1823 .opt_clks = omap34xx_mmc1_opt_clks, 1824 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), 1825 .main_clk = "mmchs1_fck", 1826 .prcm = { 1827 .omap2 = { 1828 .module_offs = CORE_MOD, 1829 .prcm_reg_id = 1, 1830 .module_bit = OMAP3430_EN_MMC1_SHIFT, 1831 .idlest_reg_id = 1, 1832 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, 1833 }, 1834 }, 1835 .dev_attr = &mmc1_dev_attr, 1836 .class = &omap34xx_mmc_class, 1837 }; 1838 1839 /* MMC/SD/SDIO2 */ 1840 1841 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = { 1842 { .irq = 86 + OMAP_INTC_START, }, 1843 { .irq = -1 }, 1844 }; 1845 1846 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = { 1847 { .name = "tx", .dma_req = 47, }, 1848 { .name = "rx", .dma_req = 48, }, 1849 { .dma_req = -1 } 1850 }; 1851 1852 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = { 1853 { .role = "dbck", .clk = "omap_32k_fck", }, 1854 }; 1855 1856 /* See 35xx errata 2.1.1.128 in SPRZ278F */ 1857 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = { 1858 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, 1859 }; 1860 1861 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = { 1862 .name = "mmc2", 1863 .mpu_irqs = omap34xx_mmc2_mpu_irqs, 1864 .sdma_reqs = omap34xx_mmc2_sdma_reqs, 1865 .opt_clks = omap34xx_mmc2_opt_clks, 1866 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), 1867 .main_clk = "mmchs2_fck", 1868 .prcm = { 1869 .omap2 = { 1870 .module_offs = CORE_MOD, 1871 .prcm_reg_id = 1, 1872 .module_bit = OMAP3430_EN_MMC2_SHIFT, 1873 .idlest_reg_id = 1, 1874 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, 1875 }, 1876 }, 1877 .dev_attr = &mmc2_pre_es3_dev_attr, 1878 .class = &omap34xx_mmc_class, 1879 }; 1880 1881 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = { 1882 .name = "mmc2", 1883 .mpu_irqs = omap34xx_mmc2_mpu_irqs, 1884 .sdma_reqs = omap34xx_mmc2_sdma_reqs, 1885 .opt_clks = omap34xx_mmc2_opt_clks, 1886 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), 1887 .main_clk = "mmchs2_fck", 1888 .prcm = { 1889 .omap2 = { 1890 .module_offs = CORE_MOD, 1891 .prcm_reg_id = 1, 1892 .module_bit = OMAP3430_EN_MMC2_SHIFT, 1893 .idlest_reg_id = 1, 1894 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, 1895 }, 1896 }, 1897 .class = &omap34xx_mmc_class, 1898 }; 1899 1900 /* MMC/SD/SDIO3 */ 1901 1902 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = { 1903 { .irq = 94 + OMAP_INTC_START, }, 1904 { .irq = -1 }, 1905 }; 1906 1907 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = { 1908 { .name = "tx", .dma_req = 77, }, 1909 { .name = "rx", .dma_req = 78, }, 1910 { .dma_req = -1 } 1911 }; 1912 1913 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = { 1914 { .role = "dbck", .clk = "omap_32k_fck", }, 1915 }; 1916 1917 static struct omap_hwmod omap3xxx_mmc3_hwmod = { 1918 .name = "mmc3", 1919 .mpu_irqs = omap34xx_mmc3_mpu_irqs, 1920 .sdma_reqs = omap34xx_mmc3_sdma_reqs, 1921 .opt_clks = omap34xx_mmc3_opt_clks, 1922 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks), 1923 .main_clk = "mmchs3_fck", 1924 .prcm = { 1925 .omap2 = { 1926 .prcm_reg_id = 1, 1927 .module_bit = OMAP3430_EN_MMC3_SHIFT, 1928 .idlest_reg_id = 1, 1929 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT, 1930 }, 1931 }, 1932 .class = &omap34xx_mmc_class, 1933 }; 1934 1935 /* 1936 * 'usb_host_hs' class 1937 * high-speed multi-port usb host controller 1938 */ 1939 1940 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = { 1941 .rev_offs = 0x0000, 1942 .sysc_offs = 0x0010, 1943 .syss_offs = 0x0014, 1944 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | 1945 SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | 1946 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), 1947 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 1948 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 1949 .sysc_fields = &omap_hwmod_sysc_type1, 1950 }; 1951 1952 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = { 1953 .name = "usb_host_hs", 1954 .sysc = &omap3xxx_usb_host_hs_sysc, 1955 }; 1956 1957 static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = { 1958 { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", }, 1959 }; 1960 1961 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = { 1962 { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, }, 1963 { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, }, 1964 { .irq = -1 }, 1965 }; 1966 1967 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = { 1968 .name = "usb_host_hs", 1969 .class = &omap3xxx_usb_host_hs_hwmod_class, 1970 .clkdm_name = "l3_init_clkdm", 1971 .mpu_irqs = omap3xxx_usb_host_hs_irqs, 1972 .main_clk = "usbhost_48m_fck", 1973 .prcm = { 1974 .omap2 = { 1975 .module_offs = OMAP3430ES2_USBHOST_MOD, 1976 .prcm_reg_id = 1, 1977 .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, 1978 .idlest_reg_id = 1, 1979 .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT, 1980 .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT, 1981 }, 1982 }, 1983 .opt_clks = omap3xxx_usb_host_hs_opt_clks, 1984 .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks), 1985 1986 /* 1987 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock 1988 * id: i660 1989 * 1990 * Description: 1991 * In the following configuration : 1992 * - USBHOST module is set to smart-idle mode 1993 * - PRCM asserts idle_req to the USBHOST module ( This typically 1994 * happens when the system is going to a low power mode : all ports 1995 * have been suspended, the master part of the USBHOST module has 1996 * entered the standby state, and SW has cut the functional clocks) 1997 * - an USBHOST interrupt occurs before the module is able to answer 1998 * idle_ack, typically a remote wakeup IRQ. 1999 * Then the USB HOST module will enter a deadlock situation where it 2000 * is no more accessible nor functional. 2001 * 2002 * Workaround: 2003 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE 2004 */ 2005 2006 /* 2007 * Errata: USB host EHCI may stall when entering smart-standby mode 2008 * Id: i571 2009 * 2010 * Description: 2011 * When the USBHOST module is set to smart-standby mode, and when it is 2012 * ready to enter the standby state (i.e. all ports are suspended and 2013 * all attached devices are in suspend mode), then it can wrongly assert 2014 * the Mstandby signal too early while there are still some residual OCP 2015 * transactions ongoing. If this condition occurs, the internal state 2016 * machine may go to an undefined state and the USB link may be stuck 2017 * upon the next resume. 2018 * 2019 * Workaround: 2020 * Don't use smart standby; use only force standby, 2021 * hence HWMOD_SWSUP_MSTANDBY 2022 */ 2023 2024 /* 2025 * During system boot; If the hwmod framework resets the module 2026 * the module will have smart idle settings; which can lead to deadlock 2027 * (above Errata Id:i660); so, dont reset the module during boot; 2028 * Use HWMOD_INIT_NO_RESET. 2029 */ 2030 2031 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | 2032 HWMOD_INIT_NO_RESET, 2033 }; 2034 2035 /* 2036 * 'usb_tll_hs' class 2037 * usb_tll_hs module is the adapter on the usb_host_hs ports 2038 */ 2039 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = { 2040 .rev_offs = 0x0000, 2041 .sysc_offs = 0x0010, 2042 .syss_offs = 0x0014, 2043 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 2044 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 2045 SYSC_HAS_AUTOIDLE), 2046 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 2047 .sysc_fields = &omap_hwmod_sysc_type1, 2048 }; 2049 2050 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = { 2051 .name = "usb_tll_hs", 2052 .sysc = &omap3xxx_usb_tll_hs_sysc, 2053 }; 2054 2055 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = { 2056 { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, }, 2057 { .irq = -1 }, 2058 }; 2059 2060 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { 2061 .name = "usb_tll_hs", 2062 .class = &omap3xxx_usb_tll_hs_hwmod_class, 2063 .clkdm_name = "l3_init_clkdm", 2064 .mpu_irqs = omap3xxx_usb_tll_hs_irqs, 2065 .main_clk = "usbtll_fck", 2066 .prcm = { 2067 .omap2 = { 2068 .module_offs = CORE_MOD, 2069 .prcm_reg_id = 3, 2070 .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT, 2071 .idlest_reg_id = 3, 2072 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT, 2073 }, 2074 }, 2075 }; 2076 2077 static struct omap_hwmod omap3xxx_hdq1w_hwmod = { 2078 .name = "hdq1w", 2079 .mpu_irqs = omap2_hdq1w_mpu_irqs, 2080 .main_clk = "hdq_fck", 2081 .prcm = { 2082 .omap2 = { 2083 .module_offs = CORE_MOD, 2084 .prcm_reg_id = 1, 2085 .module_bit = OMAP3430_EN_HDQ_SHIFT, 2086 .idlest_reg_id = 1, 2087 .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT, 2088 }, 2089 }, 2090 .class = &omap2_hdq1w_class, 2091 }; 2092 2093 /* SAD2D */ 2094 static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = { 2095 { .name = "rst_modem_pwron_sw", .rst_shift = 0 }, 2096 { .name = "rst_modem_sw", .rst_shift = 1 }, 2097 }; 2098 2099 static struct omap_hwmod_class omap3xxx_sad2d_class = { 2100 .name = "sad2d", 2101 }; 2102 2103 static struct omap_hwmod omap3xxx_sad2d_hwmod = { 2104 .name = "sad2d", 2105 .rst_lines = omap3xxx_sad2d_resets, 2106 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_sad2d_resets), 2107 .main_clk = "sad2d_ick", 2108 .prcm = { 2109 .omap2 = { 2110 .module_offs = CORE_MOD, 2111 .prcm_reg_id = 1, 2112 .module_bit = OMAP3430_EN_SAD2D_SHIFT, 2113 .idlest_reg_id = 1, 2114 .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT, 2115 }, 2116 }, 2117 .class = &omap3xxx_sad2d_class, 2118 }; 2119 2120 /* 2121 * '32K sync counter' class 2122 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock 2123 */ 2124 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = { 2125 .rev_offs = 0x0000, 2126 .sysc_offs = 0x0004, 2127 .sysc_flags = SYSC_HAS_SIDLEMODE, 2128 .idlemodes = (SIDLE_FORCE | SIDLE_NO), 2129 .sysc_fields = &omap_hwmod_sysc_type1, 2130 }; 2131 2132 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = { 2133 .name = "counter", 2134 .sysc = &omap3xxx_counter_sysc, 2135 }; 2136 2137 static struct omap_hwmod omap3xxx_counter_32k_hwmod = { 2138 .name = "counter_32k", 2139 .class = &omap3xxx_counter_hwmod_class, 2140 .clkdm_name = "wkup_clkdm", 2141 .flags = HWMOD_SWSUP_SIDLE, 2142 .main_clk = "wkup_32k_fck", 2143 .prcm = { 2144 .omap2 = { 2145 .module_offs = WKUP_MOD, 2146 .prcm_reg_id = 1, 2147 .module_bit = OMAP3430_ST_32KSYNC_SHIFT, 2148 .idlest_reg_id = 1, 2149 .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT, 2150 }, 2151 }, 2152 }; 2153 2154 /* 2155 * 'gpmc' class 2156 * general purpose memory controller 2157 */ 2158 2159 static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = { 2160 .rev_offs = 0x0000, 2161 .sysc_offs = 0x0010, 2162 .syss_offs = 0x0014, 2163 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | 2164 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 2165 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 2166 .sysc_fields = &omap_hwmod_sysc_type1, 2167 }; 2168 2169 static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = { 2170 .name = "gpmc", 2171 .sysc = &omap3xxx_gpmc_sysc, 2172 }; 2173 2174 static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = { 2175 { .irq = 20 }, 2176 { .irq = -1 } 2177 }; 2178 2179 static struct omap_hwmod omap3xxx_gpmc_hwmod = { 2180 .name = "gpmc", 2181 .class = &omap3xxx_gpmc_hwmod_class, 2182 .clkdm_name = "core_l3_clkdm", 2183 .mpu_irqs = omap3xxx_gpmc_irqs, 2184 .main_clk = "gpmc_fck", 2185 /* 2186 * XXX HWMOD_INIT_NO_RESET should not be needed for this IP 2187 * block. It is not being added due to any known bugs with 2188 * resetting the GPMC IP block, but rather because any timings 2189 * set by the bootloader are not being correctly programmed by 2190 * the kernel from the board file or DT data. 2191 * HWMOD_INIT_NO_RESET should be removed ASAP. 2192 */ 2193 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET | 2194 HWMOD_NO_IDLEST), 2195 }; 2196 2197 /* 2198 * interfaces 2199 */ 2200 2201 /* L3 -> L4_CORE interface */ 2202 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { 2203 .master = &omap3xxx_l3_main_hwmod, 2204 .slave = &omap3xxx_l4_core_hwmod, 2205 .user = OCP_USER_MPU | OCP_USER_SDMA, 2206 }; 2207 2208 /* L3 -> L4_PER interface */ 2209 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { 2210 .master = &omap3xxx_l3_main_hwmod, 2211 .slave = &omap3xxx_l4_per_hwmod, 2212 .user = OCP_USER_MPU | OCP_USER_SDMA, 2213 }; 2214 2215 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = { 2216 { 2217 .pa_start = 0x68000000, 2218 .pa_end = 0x6800ffff, 2219 .flags = ADDR_TYPE_RT, 2220 }, 2221 { } 2222 }; 2223 2224 /* MPU -> L3 interface */ 2225 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { 2226 .master = &omap3xxx_mpu_hwmod, 2227 .slave = &omap3xxx_l3_main_hwmod, 2228 .addr = omap3xxx_l3_main_addrs, 2229 .user = OCP_USER_MPU, 2230 }; 2231 2232 static struct omap_hwmod_addr_space omap3xxx_l4_emu_addrs[] = { 2233 { 2234 .pa_start = 0x54000000, 2235 .pa_end = 0x547fffff, 2236 .flags = ADDR_TYPE_RT, 2237 }, 2238 { } 2239 }; 2240 2241 /* l3 -> debugss */ 2242 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = { 2243 .master = &omap3xxx_l3_main_hwmod, 2244 .slave = &omap3xxx_debugss_hwmod, 2245 .addr = omap3xxx_l4_emu_addrs, 2246 .user = OCP_USER_MPU, 2247 }; 2248 2249 /* DSS -> l3 */ 2250 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = { 2251 .master = &omap3430es1_dss_core_hwmod, 2252 .slave = &omap3xxx_l3_main_hwmod, 2253 .user = OCP_USER_MPU | OCP_USER_SDMA, 2254 }; 2255 2256 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = { 2257 .master = &omap3xxx_dss_core_hwmod, 2258 .slave = &omap3xxx_l3_main_hwmod, 2259 .fw = { 2260 .omap2 = { 2261 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS, 2262 .flags = OMAP_FIREWALL_L3, 2263 } 2264 }, 2265 .user = OCP_USER_MPU | OCP_USER_SDMA, 2266 }; 2267 2268 /* l3_core -> usbhsotg interface */ 2269 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { 2270 .master = &omap3xxx_usbhsotg_hwmod, 2271 .slave = &omap3xxx_l3_main_hwmod, 2272 .clk = "core_l3_ick", 2273 .user = OCP_USER_MPU, 2274 }; 2275 2276 /* l3_core -> am35xx_usbhsotg interface */ 2277 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { 2278 .master = &am35xx_usbhsotg_hwmod, 2279 .slave = &omap3xxx_l3_main_hwmod, 2280 .clk = "hsotgusb_ick", 2281 .user = OCP_USER_MPU, 2282 }; 2283 2284 /* l3_core -> sad2d interface */ 2285 static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = { 2286 .master = &omap3xxx_sad2d_hwmod, 2287 .slave = &omap3xxx_l3_main_hwmod, 2288 .clk = "core_l3_ick", 2289 .user = OCP_USER_MPU, 2290 }; 2291 2292 /* L4_CORE -> L4_WKUP interface */ 2293 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { 2294 .master = &omap3xxx_l4_core_hwmod, 2295 .slave = &omap3xxx_l4_wkup_hwmod, 2296 .user = OCP_USER_MPU | OCP_USER_SDMA, 2297 }; 2298 2299 /* L4 CORE -> MMC1 interface */ 2300 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = { 2301 .master = &omap3xxx_l4_core_hwmod, 2302 .slave = &omap3xxx_pre_es3_mmc1_hwmod, 2303 .clk = "mmchs1_ick", 2304 .addr = omap2430_mmc1_addr_space, 2305 .user = OCP_USER_MPU | OCP_USER_SDMA, 2306 .flags = OMAP_FIREWALL_L4 2307 }; 2308 2309 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = { 2310 .master = &omap3xxx_l4_core_hwmod, 2311 .slave = &omap3xxx_es3plus_mmc1_hwmod, 2312 .clk = "mmchs1_ick", 2313 .addr = omap2430_mmc1_addr_space, 2314 .user = OCP_USER_MPU | OCP_USER_SDMA, 2315 .flags = OMAP_FIREWALL_L4 2316 }; 2317 2318 /* L4 CORE -> MMC2 interface */ 2319 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = { 2320 .master = &omap3xxx_l4_core_hwmod, 2321 .slave = &omap3xxx_pre_es3_mmc2_hwmod, 2322 .clk = "mmchs2_ick", 2323 .addr = omap2430_mmc2_addr_space, 2324 .user = OCP_USER_MPU | OCP_USER_SDMA, 2325 .flags = OMAP_FIREWALL_L4 2326 }; 2327 2328 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = { 2329 .master = &omap3xxx_l4_core_hwmod, 2330 .slave = &omap3xxx_es3plus_mmc2_hwmod, 2331 .clk = "mmchs2_ick", 2332 .addr = omap2430_mmc2_addr_space, 2333 .user = OCP_USER_MPU | OCP_USER_SDMA, 2334 .flags = OMAP_FIREWALL_L4 2335 }; 2336 2337 /* L4 CORE -> MMC3 interface */ 2338 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = { 2339 { 2340 .pa_start = 0x480ad000, 2341 .pa_end = 0x480ad1ff, 2342 .flags = ADDR_TYPE_RT, 2343 }, 2344 { } 2345 }; 2346 2347 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { 2348 .master = &omap3xxx_l4_core_hwmod, 2349 .slave = &omap3xxx_mmc3_hwmod, 2350 .clk = "mmchs3_ick", 2351 .addr = omap3xxx_mmc3_addr_space, 2352 .user = OCP_USER_MPU | OCP_USER_SDMA, 2353 .flags = OMAP_FIREWALL_L4 2354 }; 2355 2356 /* L4 CORE -> UART1 interface */ 2357 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = { 2358 { 2359 .pa_start = OMAP3_UART1_BASE, 2360 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1, 2361 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 2362 }, 2363 { } 2364 }; 2365 2366 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { 2367 .master = &omap3xxx_l4_core_hwmod, 2368 .slave = &omap3xxx_uart1_hwmod, 2369 .clk = "uart1_ick", 2370 .addr = omap3xxx_uart1_addr_space, 2371 .user = OCP_USER_MPU | OCP_USER_SDMA, 2372 }; 2373 2374 /* L4 CORE -> UART2 interface */ 2375 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = { 2376 { 2377 .pa_start = OMAP3_UART2_BASE, 2378 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1, 2379 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 2380 }, 2381 { } 2382 }; 2383 2384 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { 2385 .master = &omap3xxx_l4_core_hwmod, 2386 .slave = &omap3xxx_uart2_hwmod, 2387 .clk = "uart2_ick", 2388 .addr = omap3xxx_uart2_addr_space, 2389 .user = OCP_USER_MPU | OCP_USER_SDMA, 2390 }; 2391 2392 /* L4 PER -> UART3 interface */ 2393 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = { 2394 { 2395 .pa_start = OMAP3_UART3_BASE, 2396 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1, 2397 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 2398 }, 2399 { } 2400 }; 2401 2402 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { 2403 .master = &omap3xxx_l4_per_hwmod, 2404 .slave = &omap3xxx_uart3_hwmod, 2405 .clk = "uart3_ick", 2406 .addr = omap3xxx_uart3_addr_space, 2407 .user = OCP_USER_MPU | OCP_USER_SDMA, 2408 }; 2409 2410 /* L4 PER -> UART4 interface */ 2411 static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = { 2412 { 2413 .pa_start = OMAP3_UART4_BASE, 2414 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1, 2415 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 2416 }, 2417 { } 2418 }; 2419 2420 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = { 2421 .master = &omap3xxx_l4_per_hwmod, 2422 .slave = &omap36xx_uart4_hwmod, 2423 .clk = "uart4_ick", 2424 .addr = omap36xx_uart4_addr_space, 2425 .user = OCP_USER_MPU | OCP_USER_SDMA, 2426 }; 2427 2428 /* AM35xx: L4 CORE -> UART4 interface */ 2429 static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = { 2430 { 2431 .pa_start = OMAP3_UART4_AM35XX_BASE, 2432 .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1, 2433 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 2434 }, 2435 { } 2436 }; 2437 2438 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = { 2439 .master = &omap3xxx_l4_core_hwmod, 2440 .slave = &am35xx_uart4_hwmod, 2441 .clk = "uart4_ick", 2442 .addr = am35xx_uart4_addr_space, 2443 .user = OCP_USER_MPU | OCP_USER_SDMA, 2444 }; 2445 2446 /* L4 CORE -> I2C1 interface */ 2447 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { 2448 .master = &omap3xxx_l4_core_hwmod, 2449 .slave = &omap3xxx_i2c1_hwmod, 2450 .clk = "i2c1_ick", 2451 .addr = omap2_i2c1_addr_space, 2452 .fw = { 2453 .omap2 = { 2454 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, 2455 .l4_prot_group = 7, 2456 .flags = OMAP_FIREWALL_L4, 2457 } 2458 }, 2459 .user = OCP_USER_MPU | OCP_USER_SDMA, 2460 }; 2461 2462 /* L4 CORE -> I2C2 interface */ 2463 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { 2464 .master = &omap3xxx_l4_core_hwmod, 2465 .slave = &omap3xxx_i2c2_hwmod, 2466 .clk = "i2c2_ick", 2467 .addr = omap2_i2c2_addr_space, 2468 .fw = { 2469 .omap2 = { 2470 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, 2471 .l4_prot_group = 7, 2472 .flags = OMAP_FIREWALL_L4, 2473 } 2474 }, 2475 .user = OCP_USER_MPU | OCP_USER_SDMA, 2476 }; 2477 2478 /* L4 CORE -> I2C3 interface */ 2479 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = { 2480 { 2481 .pa_start = 0x48060000, 2482 .pa_end = 0x48060000 + SZ_128 - 1, 2483 .flags = ADDR_TYPE_RT, 2484 }, 2485 { } 2486 }; 2487 2488 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { 2489 .master = &omap3xxx_l4_core_hwmod, 2490 .slave = &omap3xxx_i2c3_hwmod, 2491 .clk = "i2c3_ick", 2492 .addr = omap3xxx_i2c3_addr_space, 2493 .fw = { 2494 .omap2 = { 2495 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, 2496 .l4_prot_group = 7, 2497 .flags = OMAP_FIREWALL_L4, 2498 } 2499 }, 2500 .user = OCP_USER_MPU | OCP_USER_SDMA, 2501 }; 2502 2503 /* L4 CORE -> SR1 interface */ 2504 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = { 2505 { 2506 .pa_start = OMAP34XX_SR1_BASE, 2507 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1, 2508 .flags = ADDR_TYPE_RT, 2509 }, 2510 { } 2511 }; 2512 2513 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = { 2514 .master = &omap3xxx_l4_core_hwmod, 2515 .slave = &omap34xx_sr1_hwmod, 2516 .clk = "sr_l4_ick", 2517 .addr = omap3_sr1_addr_space, 2518 .user = OCP_USER_MPU, 2519 }; 2520 2521 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = { 2522 .master = &omap3xxx_l4_core_hwmod, 2523 .slave = &omap36xx_sr1_hwmod, 2524 .clk = "sr_l4_ick", 2525 .addr = omap3_sr1_addr_space, 2526 .user = OCP_USER_MPU, 2527 }; 2528 2529 /* L4 CORE -> SR1 interface */ 2530 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = { 2531 { 2532 .pa_start = OMAP34XX_SR2_BASE, 2533 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1, 2534 .flags = ADDR_TYPE_RT, 2535 }, 2536 { } 2537 }; 2538 2539 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = { 2540 .master = &omap3xxx_l4_core_hwmod, 2541 .slave = &omap34xx_sr2_hwmod, 2542 .clk = "sr_l4_ick", 2543 .addr = omap3_sr2_addr_space, 2544 .user = OCP_USER_MPU, 2545 }; 2546 2547 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = { 2548 .master = &omap3xxx_l4_core_hwmod, 2549 .slave = &omap36xx_sr2_hwmod, 2550 .clk = "sr_l4_ick", 2551 .addr = omap3_sr2_addr_space, 2552 .user = OCP_USER_MPU, 2553 }; 2554 2555 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = { 2556 { 2557 .pa_start = OMAP34XX_HSUSB_OTG_BASE, 2558 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1, 2559 .flags = ADDR_TYPE_RT 2560 }, 2561 { } 2562 }; 2563 2564 /* l4_core -> usbhsotg */ 2565 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { 2566 .master = &omap3xxx_l4_core_hwmod, 2567 .slave = &omap3xxx_usbhsotg_hwmod, 2568 .clk = "l4_ick", 2569 .addr = omap3xxx_usbhsotg_addrs, 2570 .user = OCP_USER_MPU, 2571 }; 2572 2573 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = { 2574 { 2575 .pa_start = AM35XX_IPSS_USBOTGSS_BASE, 2576 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1, 2577 .flags = ADDR_TYPE_RT 2578 }, 2579 { } 2580 }; 2581 2582 /* l4_core -> usbhsotg */ 2583 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { 2584 .master = &omap3xxx_l4_core_hwmod, 2585 .slave = &am35xx_usbhsotg_hwmod, 2586 .clk = "hsotgusb_ick", 2587 .addr = am35xx_usbhsotg_addrs, 2588 .user = OCP_USER_MPU, 2589 }; 2590 2591 /* L4_WKUP -> L4_SEC interface */ 2592 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = { 2593 .master = &omap3xxx_l4_wkup_hwmod, 2594 .slave = &omap3xxx_l4_sec_hwmod, 2595 .user = OCP_USER_MPU | OCP_USER_SDMA, 2596 }; 2597 2598 /* IVA2 <- L3 interface */ 2599 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = { 2600 .master = &omap3xxx_l3_main_hwmod, 2601 .slave = &omap3xxx_iva_hwmod, 2602 .clk = "core_l3_ick", 2603 .user = OCP_USER_MPU | OCP_USER_SDMA, 2604 }; 2605 2606 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = { 2607 { 2608 .pa_start = 0x48318000, 2609 .pa_end = 0x48318000 + SZ_1K - 1, 2610 .flags = ADDR_TYPE_RT 2611 }, 2612 { } 2613 }; 2614 2615 /* l4_wkup -> timer1 */ 2616 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = { 2617 .master = &omap3xxx_l4_wkup_hwmod, 2618 .slave = &omap3xxx_timer1_hwmod, 2619 .clk = "gpt1_ick", 2620 .addr = omap3xxx_timer1_addrs, 2621 .user = OCP_USER_MPU | OCP_USER_SDMA, 2622 }; 2623 2624 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = { 2625 { 2626 .pa_start = 0x49032000, 2627 .pa_end = 0x49032000 + SZ_1K - 1, 2628 .flags = ADDR_TYPE_RT 2629 }, 2630 { } 2631 }; 2632 2633 /* l4_per -> timer2 */ 2634 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = { 2635 .master = &omap3xxx_l4_per_hwmod, 2636 .slave = &omap3xxx_timer2_hwmod, 2637 .clk = "gpt2_ick", 2638 .addr = omap3xxx_timer2_addrs, 2639 .user = OCP_USER_MPU | OCP_USER_SDMA, 2640 }; 2641 2642 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = { 2643 { 2644 .pa_start = 0x49034000, 2645 .pa_end = 0x49034000 + SZ_1K - 1, 2646 .flags = ADDR_TYPE_RT 2647 }, 2648 { } 2649 }; 2650 2651 /* l4_per -> timer3 */ 2652 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = { 2653 .master = &omap3xxx_l4_per_hwmod, 2654 .slave = &omap3xxx_timer3_hwmod, 2655 .clk = "gpt3_ick", 2656 .addr = omap3xxx_timer3_addrs, 2657 .user = OCP_USER_MPU | OCP_USER_SDMA, 2658 }; 2659 2660 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = { 2661 { 2662 .pa_start = 0x49036000, 2663 .pa_end = 0x49036000 + SZ_1K - 1, 2664 .flags = ADDR_TYPE_RT 2665 }, 2666 { } 2667 }; 2668 2669 /* l4_per -> timer4 */ 2670 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = { 2671 .master = &omap3xxx_l4_per_hwmod, 2672 .slave = &omap3xxx_timer4_hwmod, 2673 .clk = "gpt4_ick", 2674 .addr = omap3xxx_timer4_addrs, 2675 .user = OCP_USER_MPU | OCP_USER_SDMA, 2676 }; 2677 2678 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = { 2679 { 2680 .pa_start = 0x49038000, 2681 .pa_end = 0x49038000 + SZ_1K - 1, 2682 .flags = ADDR_TYPE_RT 2683 }, 2684 { } 2685 }; 2686 2687 /* l4_per -> timer5 */ 2688 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = { 2689 .master = &omap3xxx_l4_per_hwmod, 2690 .slave = &omap3xxx_timer5_hwmod, 2691 .clk = "gpt5_ick", 2692 .addr = omap3xxx_timer5_addrs, 2693 .user = OCP_USER_MPU | OCP_USER_SDMA, 2694 }; 2695 2696 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = { 2697 { 2698 .pa_start = 0x4903A000, 2699 .pa_end = 0x4903A000 + SZ_1K - 1, 2700 .flags = ADDR_TYPE_RT 2701 }, 2702 { } 2703 }; 2704 2705 /* l4_per -> timer6 */ 2706 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = { 2707 .master = &omap3xxx_l4_per_hwmod, 2708 .slave = &omap3xxx_timer6_hwmod, 2709 .clk = "gpt6_ick", 2710 .addr = omap3xxx_timer6_addrs, 2711 .user = OCP_USER_MPU | OCP_USER_SDMA, 2712 }; 2713 2714 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = { 2715 { 2716 .pa_start = 0x4903C000, 2717 .pa_end = 0x4903C000 + SZ_1K - 1, 2718 .flags = ADDR_TYPE_RT 2719 }, 2720 { } 2721 }; 2722 2723 /* l4_per -> timer7 */ 2724 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = { 2725 .master = &omap3xxx_l4_per_hwmod, 2726 .slave = &omap3xxx_timer7_hwmod, 2727 .clk = "gpt7_ick", 2728 .addr = omap3xxx_timer7_addrs, 2729 .user = OCP_USER_MPU | OCP_USER_SDMA, 2730 }; 2731 2732 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = { 2733 { 2734 .pa_start = 0x4903E000, 2735 .pa_end = 0x4903E000 + SZ_1K - 1, 2736 .flags = ADDR_TYPE_RT 2737 }, 2738 { } 2739 }; 2740 2741 /* l4_per -> timer8 */ 2742 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = { 2743 .master = &omap3xxx_l4_per_hwmod, 2744 .slave = &omap3xxx_timer8_hwmod, 2745 .clk = "gpt8_ick", 2746 .addr = omap3xxx_timer8_addrs, 2747 .user = OCP_USER_MPU | OCP_USER_SDMA, 2748 }; 2749 2750 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = { 2751 { 2752 .pa_start = 0x49040000, 2753 .pa_end = 0x49040000 + SZ_1K - 1, 2754 .flags = ADDR_TYPE_RT 2755 }, 2756 { } 2757 }; 2758 2759 /* l4_per -> timer9 */ 2760 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = { 2761 .master = &omap3xxx_l4_per_hwmod, 2762 .slave = &omap3xxx_timer9_hwmod, 2763 .clk = "gpt9_ick", 2764 .addr = omap3xxx_timer9_addrs, 2765 .user = OCP_USER_MPU | OCP_USER_SDMA, 2766 }; 2767 2768 /* l4_core -> timer10 */ 2769 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = { 2770 .master = &omap3xxx_l4_core_hwmod, 2771 .slave = &omap3xxx_timer10_hwmod, 2772 .clk = "gpt10_ick", 2773 .addr = omap2_timer10_addrs, 2774 .user = OCP_USER_MPU | OCP_USER_SDMA, 2775 }; 2776 2777 /* l4_core -> timer11 */ 2778 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { 2779 .master = &omap3xxx_l4_core_hwmod, 2780 .slave = &omap3xxx_timer11_hwmod, 2781 .clk = "gpt11_ick", 2782 .addr = omap2_timer11_addrs, 2783 .user = OCP_USER_MPU | OCP_USER_SDMA, 2784 }; 2785 2786 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = { 2787 { 2788 .pa_start = 0x48304000, 2789 .pa_end = 0x48304000 + SZ_1K - 1, 2790 .flags = ADDR_TYPE_RT 2791 }, 2792 { } 2793 }; 2794 2795 /* l4_core -> timer12 */ 2796 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = { 2797 .master = &omap3xxx_l4_sec_hwmod, 2798 .slave = &omap3xxx_timer12_hwmod, 2799 .clk = "gpt12_ick", 2800 .addr = omap3xxx_timer12_addrs, 2801 .user = OCP_USER_MPU | OCP_USER_SDMA, 2802 }; 2803 2804 /* l4_wkup -> wd_timer2 */ 2805 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { 2806 { 2807 .pa_start = 0x48314000, 2808 .pa_end = 0x4831407f, 2809 .flags = ADDR_TYPE_RT 2810 }, 2811 { } 2812 }; 2813 2814 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { 2815 .master = &omap3xxx_l4_wkup_hwmod, 2816 .slave = &omap3xxx_wd_timer2_hwmod, 2817 .clk = "wdt2_ick", 2818 .addr = omap3xxx_wd_timer2_addrs, 2819 .user = OCP_USER_MPU | OCP_USER_SDMA, 2820 }; 2821 2822 /* l4_core -> dss */ 2823 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { 2824 .master = &omap3xxx_l4_core_hwmod, 2825 .slave = &omap3430es1_dss_core_hwmod, 2826 .clk = "dss_ick", 2827 .addr = omap2_dss_addrs, 2828 .fw = { 2829 .omap2 = { 2830 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, 2831 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 2832 .flags = OMAP_FIREWALL_L4, 2833 } 2834 }, 2835 .user = OCP_USER_MPU | OCP_USER_SDMA, 2836 }; 2837 2838 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = { 2839 .master = &omap3xxx_l4_core_hwmod, 2840 .slave = &omap3xxx_dss_core_hwmod, 2841 .clk = "dss_ick", 2842 .addr = omap2_dss_addrs, 2843 .fw = { 2844 .omap2 = { 2845 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, 2846 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 2847 .flags = OMAP_FIREWALL_L4, 2848 } 2849 }, 2850 .user = OCP_USER_MPU | OCP_USER_SDMA, 2851 }; 2852 2853 /* l4_core -> dss_dispc */ 2854 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { 2855 .master = &omap3xxx_l4_core_hwmod, 2856 .slave = &omap3xxx_dss_dispc_hwmod, 2857 .clk = "dss_ick", 2858 .addr = omap2_dss_dispc_addrs, 2859 .fw = { 2860 .omap2 = { 2861 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, 2862 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 2863 .flags = OMAP_FIREWALL_L4, 2864 } 2865 }, 2866 .user = OCP_USER_MPU | OCP_USER_SDMA, 2867 }; 2868 2869 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = { 2870 { 2871 .pa_start = 0x4804FC00, 2872 .pa_end = 0x4804FFFF, 2873 .flags = ADDR_TYPE_RT 2874 }, 2875 { } 2876 }; 2877 2878 /* l4_core -> dss_dsi1 */ 2879 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { 2880 .master = &omap3xxx_l4_core_hwmod, 2881 .slave = &omap3xxx_dss_dsi1_hwmod, 2882 .clk = "dss_ick", 2883 .addr = omap3xxx_dss_dsi1_addrs, 2884 .fw = { 2885 .omap2 = { 2886 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, 2887 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 2888 .flags = OMAP_FIREWALL_L4, 2889 } 2890 }, 2891 .user = OCP_USER_MPU | OCP_USER_SDMA, 2892 }; 2893 2894 /* l4_core -> dss_rfbi */ 2895 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { 2896 .master = &omap3xxx_l4_core_hwmod, 2897 .slave = &omap3xxx_dss_rfbi_hwmod, 2898 .clk = "dss_ick", 2899 .addr = omap2_dss_rfbi_addrs, 2900 .fw = { 2901 .omap2 = { 2902 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, 2903 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP , 2904 .flags = OMAP_FIREWALL_L4, 2905 } 2906 }, 2907 .user = OCP_USER_MPU | OCP_USER_SDMA, 2908 }; 2909 2910 /* l4_core -> dss_venc */ 2911 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { 2912 .master = &omap3xxx_l4_core_hwmod, 2913 .slave = &omap3xxx_dss_venc_hwmod, 2914 .clk = "dss_ick", 2915 .addr = omap2_dss_venc_addrs, 2916 .fw = { 2917 .omap2 = { 2918 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, 2919 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 2920 .flags = OMAP_FIREWALL_L4, 2921 } 2922 }, 2923 .flags = OCPIF_SWSUP_IDLE, 2924 .user = OCP_USER_MPU | OCP_USER_SDMA, 2925 }; 2926 2927 /* l4_wkup -> gpio1 */ 2928 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = { 2929 { 2930 .pa_start = 0x48310000, 2931 .pa_end = 0x483101ff, 2932 .flags = ADDR_TYPE_RT 2933 }, 2934 { } 2935 }; 2936 2937 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { 2938 .master = &omap3xxx_l4_wkup_hwmod, 2939 .slave = &omap3xxx_gpio1_hwmod, 2940 .addr = omap3xxx_gpio1_addrs, 2941 .user = OCP_USER_MPU | OCP_USER_SDMA, 2942 }; 2943 2944 /* l4_per -> gpio2 */ 2945 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = { 2946 { 2947 .pa_start = 0x49050000, 2948 .pa_end = 0x490501ff, 2949 .flags = ADDR_TYPE_RT 2950 }, 2951 { } 2952 }; 2953 2954 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { 2955 .master = &omap3xxx_l4_per_hwmod, 2956 .slave = &omap3xxx_gpio2_hwmod, 2957 .addr = omap3xxx_gpio2_addrs, 2958 .user = OCP_USER_MPU | OCP_USER_SDMA, 2959 }; 2960 2961 /* l4_per -> gpio3 */ 2962 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = { 2963 { 2964 .pa_start = 0x49052000, 2965 .pa_end = 0x490521ff, 2966 .flags = ADDR_TYPE_RT 2967 }, 2968 { } 2969 }; 2970 2971 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { 2972 .master = &omap3xxx_l4_per_hwmod, 2973 .slave = &omap3xxx_gpio3_hwmod, 2974 .addr = omap3xxx_gpio3_addrs, 2975 .user = OCP_USER_MPU | OCP_USER_SDMA, 2976 }; 2977 2978 /* 2979 * 'mmu' class 2980 * The memory management unit performs virtual to physical address translation 2981 * for its requestors. 2982 */ 2983 2984 static struct omap_hwmod_class_sysconfig mmu_sysc = { 2985 .rev_offs = 0x000, 2986 .sysc_offs = 0x010, 2987 .syss_offs = 0x014, 2988 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 2989 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), 2990 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 2991 .sysc_fields = &omap_hwmod_sysc_type1, 2992 }; 2993 2994 static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = { 2995 .name = "mmu", 2996 .sysc = &mmu_sysc, 2997 }; 2998 2999 /* mmu isp */ 3000 3001 static struct omap_mmu_dev_attr mmu_isp_dev_attr = { 3002 .da_start = 0x0, 3003 .da_end = 0xfffff000, 3004 .nr_tlb_entries = 8, 3005 }; 3006 3007 static struct omap_hwmod omap3xxx_mmu_isp_hwmod; 3008 static struct omap_hwmod_irq_info omap3xxx_mmu_isp_irqs[] = { 3009 { .irq = 24 }, 3010 { .irq = -1 } 3011 }; 3012 3013 static struct omap_hwmod_addr_space omap3xxx_mmu_isp_addrs[] = { 3014 { 3015 .pa_start = 0x480bd400, 3016 .pa_end = 0x480bd47f, 3017 .flags = ADDR_TYPE_RT, 3018 }, 3019 { } 3020 }; 3021 3022 /* l4_core -> mmu isp */ 3023 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = { 3024 .master = &omap3xxx_l4_core_hwmod, 3025 .slave = &omap3xxx_mmu_isp_hwmod, 3026 .addr = omap3xxx_mmu_isp_addrs, 3027 .user = OCP_USER_MPU | OCP_USER_SDMA, 3028 }; 3029 3030 static struct omap_hwmod omap3xxx_mmu_isp_hwmod = { 3031 .name = "mmu_isp", 3032 .class = &omap3xxx_mmu_hwmod_class, 3033 .mpu_irqs = omap3xxx_mmu_isp_irqs, 3034 .main_clk = "cam_ick", 3035 .dev_attr = &mmu_isp_dev_attr, 3036 .flags = HWMOD_NO_IDLEST, 3037 }; 3038 3039 #ifdef CONFIG_OMAP_IOMMU_IVA2 3040 3041 /* mmu iva */ 3042 3043 static struct omap_mmu_dev_attr mmu_iva_dev_attr = { 3044 .da_start = 0x11000000, 3045 .da_end = 0xfffff000, 3046 .nr_tlb_entries = 32, 3047 }; 3048 3049 static struct omap_hwmod omap3xxx_mmu_iva_hwmod; 3050 static struct omap_hwmod_irq_info omap3xxx_mmu_iva_irqs[] = { 3051 { .irq = 28 }, 3052 { .irq = -1 } 3053 }; 3054 3055 static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = { 3056 { .name = "mmu", .rst_shift = 1, .st_shift = 9 }, 3057 }; 3058 3059 static struct omap_hwmod_addr_space omap3xxx_mmu_iva_addrs[] = { 3060 { 3061 .pa_start = 0x5d000000, 3062 .pa_end = 0x5d00007f, 3063 .flags = ADDR_TYPE_RT, 3064 }, 3065 { } 3066 }; 3067 3068 /* l3_main -> iva mmu */ 3069 static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = { 3070 .master = &omap3xxx_l3_main_hwmod, 3071 .slave = &omap3xxx_mmu_iva_hwmod, 3072 .addr = omap3xxx_mmu_iva_addrs, 3073 .user = OCP_USER_MPU | OCP_USER_SDMA, 3074 }; 3075 3076 static struct omap_hwmod omap3xxx_mmu_iva_hwmod = { 3077 .name = "mmu_iva", 3078 .class = &omap3xxx_mmu_hwmod_class, 3079 .mpu_irqs = omap3xxx_mmu_iva_irqs, 3080 .rst_lines = omap3xxx_mmu_iva_resets, 3081 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_mmu_iva_resets), 3082 .main_clk = "iva2_ck", 3083 .prcm = { 3084 .omap2 = { 3085 .module_offs = OMAP3430_IVA2_MOD, 3086 }, 3087 }, 3088 .dev_attr = &mmu_iva_dev_attr, 3089 .flags = HWMOD_NO_IDLEST, 3090 }; 3091 3092 #endif 3093 3094 /* l4_per -> gpio4 */ 3095 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = { 3096 { 3097 .pa_start = 0x49054000, 3098 .pa_end = 0x490541ff, 3099 .flags = ADDR_TYPE_RT 3100 }, 3101 { } 3102 }; 3103 3104 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { 3105 .master = &omap3xxx_l4_per_hwmod, 3106 .slave = &omap3xxx_gpio4_hwmod, 3107 .addr = omap3xxx_gpio4_addrs, 3108 .user = OCP_USER_MPU | OCP_USER_SDMA, 3109 }; 3110 3111 /* l4_per -> gpio5 */ 3112 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = { 3113 { 3114 .pa_start = 0x49056000, 3115 .pa_end = 0x490561ff, 3116 .flags = ADDR_TYPE_RT 3117 }, 3118 { } 3119 }; 3120 3121 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { 3122 .master = &omap3xxx_l4_per_hwmod, 3123 .slave = &omap3xxx_gpio5_hwmod, 3124 .addr = omap3xxx_gpio5_addrs, 3125 .user = OCP_USER_MPU | OCP_USER_SDMA, 3126 }; 3127 3128 /* l4_per -> gpio6 */ 3129 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = { 3130 { 3131 .pa_start = 0x49058000, 3132 .pa_end = 0x490581ff, 3133 .flags = ADDR_TYPE_RT 3134 }, 3135 { } 3136 }; 3137 3138 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { 3139 .master = &omap3xxx_l4_per_hwmod, 3140 .slave = &omap3xxx_gpio6_hwmod, 3141 .addr = omap3xxx_gpio6_addrs, 3142 .user = OCP_USER_MPU | OCP_USER_SDMA, 3143 }; 3144 3145 /* dma_system -> L3 */ 3146 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = { 3147 .master = &omap3xxx_dma_system_hwmod, 3148 .slave = &omap3xxx_l3_main_hwmod, 3149 .clk = "core_l3_ick", 3150 .user = OCP_USER_MPU | OCP_USER_SDMA, 3151 }; 3152 3153 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { 3154 { 3155 .pa_start = 0x48056000, 3156 .pa_end = 0x48056fff, 3157 .flags = ADDR_TYPE_RT 3158 }, 3159 { } 3160 }; 3161 3162 /* l4_cfg -> dma_system */ 3163 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = { 3164 .master = &omap3xxx_l4_core_hwmod, 3165 .slave = &omap3xxx_dma_system_hwmod, 3166 .clk = "core_l4_ick", 3167 .addr = omap3xxx_dma_system_addrs, 3168 .user = OCP_USER_MPU | OCP_USER_SDMA, 3169 }; 3170 3171 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = { 3172 { 3173 .name = "mpu", 3174 .pa_start = 0x48074000, 3175 .pa_end = 0x480740ff, 3176 .flags = ADDR_TYPE_RT 3177 }, 3178 { } 3179 }; 3180 3181 /* l4_core -> mcbsp1 */ 3182 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = { 3183 .master = &omap3xxx_l4_core_hwmod, 3184 .slave = &omap3xxx_mcbsp1_hwmod, 3185 .clk = "mcbsp1_ick", 3186 .addr = omap3xxx_mcbsp1_addrs, 3187 .user = OCP_USER_MPU | OCP_USER_SDMA, 3188 }; 3189 3190 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = { 3191 { 3192 .name = "mpu", 3193 .pa_start = 0x49022000, 3194 .pa_end = 0x490220ff, 3195 .flags = ADDR_TYPE_RT 3196 }, 3197 { } 3198 }; 3199 3200 /* l4_per -> mcbsp2 */ 3201 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = { 3202 .master = &omap3xxx_l4_per_hwmod, 3203 .slave = &omap3xxx_mcbsp2_hwmod, 3204 .clk = "mcbsp2_ick", 3205 .addr = omap3xxx_mcbsp2_addrs, 3206 .user = OCP_USER_MPU | OCP_USER_SDMA, 3207 }; 3208 3209 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = { 3210 { 3211 .name = "mpu", 3212 .pa_start = 0x49024000, 3213 .pa_end = 0x490240ff, 3214 .flags = ADDR_TYPE_RT 3215 }, 3216 { } 3217 }; 3218 3219 /* l4_per -> mcbsp3 */ 3220 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = { 3221 .master = &omap3xxx_l4_per_hwmod, 3222 .slave = &omap3xxx_mcbsp3_hwmod, 3223 .clk = "mcbsp3_ick", 3224 .addr = omap3xxx_mcbsp3_addrs, 3225 .user = OCP_USER_MPU | OCP_USER_SDMA, 3226 }; 3227 3228 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = { 3229 { 3230 .name = "mpu", 3231 .pa_start = 0x49026000, 3232 .pa_end = 0x490260ff, 3233 .flags = ADDR_TYPE_RT 3234 }, 3235 { } 3236 }; 3237 3238 /* l4_per -> mcbsp4 */ 3239 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = { 3240 .master = &omap3xxx_l4_per_hwmod, 3241 .slave = &omap3xxx_mcbsp4_hwmod, 3242 .clk = "mcbsp4_ick", 3243 .addr = omap3xxx_mcbsp4_addrs, 3244 .user = OCP_USER_MPU | OCP_USER_SDMA, 3245 }; 3246 3247 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = { 3248 { 3249 .name = "mpu", 3250 .pa_start = 0x48096000, 3251 .pa_end = 0x480960ff, 3252 .flags = ADDR_TYPE_RT 3253 }, 3254 { } 3255 }; 3256 3257 /* l4_core -> mcbsp5 */ 3258 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = { 3259 .master = &omap3xxx_l4_core_hwmod, 3260 .slave = &omap3xxx_mcbsp5_hwmod, 3261 .clk = "mcbsp5_ick", 3262 .addr = omap3xxx_mcbsp5_addrs, 3263 .user = OCP_USER_MPU | OCP_USER_SDMA, 3264 }; 3265 3266 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = { 3267 { 3268 .name = "sidetone", 3269 .pa_start = 0x49028000, 3270 .pa_end = 0x490280ff, 3271 .flags = ADDR_TYPE_RT 3272 }, 3273 { } 3274 }; 3275 3276 /* l4_per -> mcbsp2_sidetone */ 3277 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = { 3278 .master = &omap3xxx_l4_per_hwmod, 3279 .slave = &omap3xxx_mcbsp2_sidetone_hwmod, 3280 .clk = "mcbsp2_ick", 3281 .addr = omap3xxx_mcbsp2_sidetone_addrs, 3282 .user = OCP_USER_MPU, 3283 }; 3284 3285 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = { 3286 { 3287 .name = "sidetone", 3288 .pa_start = 0x4902A000, 3289 .pa_end = 0x4902A0ff, 3290 .flags = ADDR_TYPE_RT 3291 }, 3292 { } 3293 }; 3294 3295 /* l4_per -> mcbsp3_sidetone */ 3296 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = { 3297 .master = &omap3xxx_l4_per_hwmod, 3298 .slave = &omap3xxx_mcbsp3_sidetone_hwmod, 3299 .clk = "mcbsp3_ick", 3300 .addr = omap3xxx_mcbsp3_sidetone_addrs, 3301 .user = OCP_USER_MPU, 3302 }; 3303 3304 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = { 3305 { 3306 .pa_start = 0x48094000, 3307 .pa_end = 0x480941ff, 3308 .flags = ADDR_TYPE_RT, 3309 }, 3310 { } 3311 }; 3312 3313 /* l4_core -> mailbox */ 3314 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = { 3315 .master = &omap3xxx_l4_core_hwmod, 3316 .slave = &omap3xxx_mailbox_hwmod, 3317 .addr = omap3xxx_mailbox_addrs, 3318 .user = OCP_USER_MPU | OCP_USER_SDMA, 3319 }; 3320 3321 /* l4 core -> mcspi1 interface */ 3322 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { 3323 .master = &omap3xxx_l4_core_hwmod, 3324 .slave = &omap34xx_mcspi1, 3325 .clk = "mcspi1_ick", 3326 .addr = omap2_mcspi1_addr_space, 3327 .user = OCP_USER_MPU | OCP_USER_SDMA, 3328 }; 3329 3330 /* l4 core -> mcspi2 interface */ 3331 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { 3332 .master = &omap3xxx_l4_core_hwmod, 3333 .slave = &omap34xx_mcspi2, 3334 .clk = "mcspi2_ick", 3335 .addr = omap2_mcspi2_addr_space, 3336 .user = OCP_USER_MPU | OCP_USER_SDMA, 3337 }; 3338 3339 /* l4 core -> mcspi3 interface */ 3340 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { 3341 .master = &omap3xxx_l4_core_hwmod, 3342 .slave = &omap34xx_mcspi3, 3343 .clk = "mcspi3_ick", 3344 .addr = omap2430_mcspi3_addr_space, 3345 .user = OCP_USER_MPU | OCP_USER_SDMA, 3346 }; 3347 3348 /* l4 core -> mcspi4 interface */ 3349 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = { 3350 { 3351 .pa_start = 0x480ba000, 3352 .pa_end = 0x480ba0ff, 3353 .flags = ADDR_TYPE_RT, 3354 }, 3355 { } 3356 }; 3357 3358 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { 3359 .master = &omap3xxx_l4_core_hwmod, 3360 .slave = &omap34xx_mcspi4, 3361 .clk = "mcspi4_ick", 3362 .addr = omap34xx_mcspi4_addr_space, 3363 .user = OCP_USER_MPU | OCP_USER_SDMA, 3364 }; 3365 3366 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = { 3367 .master = &omap3xxx_usb_host_hs_hwmod, 3368 .slave = &omap3xxx_l3_main_hwmod, 3369 .clk = "core_l3_ick", 3370 .user = OCP_USER_MPU, 3371 }; 3372 3373 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = { 3374 { 3375 .name = "uhh", 3376 .pa_start = 0x48064000, 3377 .pa_end = 0x480643ff, 3378 .flags = ADDR_TYPE_RT 3379 }, 3380 { 3381 .name = "ohci", 3382 .pa_start = 0x48064400, 3383 .pa_end = 0x480647ff, 3384 }, 3385 { 3386 .name = "ehci", 3387 .pa_start = 0x48064800, 3388 .pa_end = 0x48064cff, 3389 }, 3390 {} 3391 }; 3392 3393 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = { 3394 .master = &omap3xxx_l4_core_hwmod, 3395 .slave = &omap3xxx_usb_host_hs_hwmod, 3396 .clk = "usbhost_ick", 3397 .addr = omap3xxx_usb_host_hs_addrs, 3398 .user = OCP_USER_MPU | OCP_USER_SDMA, 3399 }; 3400 3401 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = { 3402 { 3403 .name = "tll", 3404 .pa_start = 0x48062000, 3405 .pa_end = 0x48062fff, 3406 .flags = ADDR_TYPE_RT 3407 }, 3408 {} 3409 }; 3410 3411 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = { 3412 .master = &omap3xxx_l4_core_hwmod, 3413 .slave = &omap3xxx_usb_tll_hs_hwmod, 3414 .clk = "usbtll_ick", 3415 .addr = omap3xxx_usb_tll_hs_addrs, 3416 .user = OCP_USER_MPU | OCP_USER_SDMA, 3417 }; 3418 3419 /* l4_core -> hdq1w interface */ 3420 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = { 3421 .master = &omap3xxx_l4_core_hwmod, 3422 .slave = &omap3xxx_hdq1w_hwmod, 3423 .clk = "hdq_ick", 3424 .addr = omap2_hdq1w_addr_space, 3425 .user = OCP_USER_MPU | OCP_USER_SDMA, 3426 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, 3427 }; 3428 3429 /* l4_wkup -> 32ksync_counter */ 3430 static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = { 3431 { 3432 .pa_start = 0x48320000, 3433 .pa_end = 0x4832001f, 3434 .flags = ADDR_TYPE_RT 3435 }, 3436 { } 3437 }; 3438 3439 static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = { 3440 { 3441 .pa_start = 0x6e000000, 3442 .pa_end = 0x6e000fff, 3443 .flags = ADDR_TYPE_RT 3444 }, 3445 { } 3446 }; 3447 3448 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = { 3449 .master = &omap3xxx_l4_wkup_hwmod, 3450 .slave = &omap3xxx_counter_32k_hwmod, 3451 .clk = "omap_32ksync_ick", 3452 .addr = omap3xxx_counter_32k_addrs, 3453 .user = OCP_USER_MPU | OCP_USER_SDMA, 3454 }; 3455 3456 /* am35xx has Davinci MDIO & EMAC */ 3457 static struct omap_hwmod_class am35xx_mdio_class = { 3458 .name = "davinci_mdio", 3459 }; 3460 3461 static struct omap_hwmod am35xx_mdio_hwmod = { 3462 .name = "davinci_mdio", 3463 .class = &am35xx_mdio_class, 3464 .flags = HWMOD_NO_IDLEST, 3465 }; 3466 3467 /* 3468 * XXX Should be connected to an IPSS hwmod, not the L3 directly; 3469 * but this will probably require some additional hwmod core support, 3470 * so is left as a future to-do item. 3471 */ 3472 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = { 3473 .master = &am35xx_mdio_hwmod, 3474 .slave = &omap3xxx_l3_main_hwmod, 3475 .clk = "emac_fck", 3476 .user = OCP_USER_MPU, 3477 }; 3478 3479 static struct omap_hwmod_addr_space am35xx_mdio_addrs[] = { 3480 { 3481 .pa_start = AM35XX_IPSS_MDIO_BASE, 3482 .pa_end = AM35XX_IPSS_MDIO_BASE + SZ_4K - 1, 3483 .flags = ADDR_TYPE_RT, 3484 }, 3485 { } 3486 }; 3487 3488 /* l4_core -> davinci mdio */ 3489 /* 3490 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly; 3491 * but this will probably require some additional hwmod core support, 3492 * so is left as a future to-do item. 3493 */ 3494 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = { 3495 .master = &omap3xxx_l4_core_hwmod, 3496 .slave = &am35xx_mdio_hwmod, 3497 .clk = "emac_fck", 3498 .addr = am35xx_mdio_addrs, 3499 .user = OCP_USER_MPU, 3500 }; 3501 3502 static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = { 3503 { .name = "rxthresh", .irq = 67 + OMAP_INTC_START, }, 3504 { .name = "rx_pulse", .irq = 68 + OMAP_INTC_START, }, 3505 { .name = "tx_pulse", .irq = 69 + OMAP_INTC_START }, 3506 { .name = "misc_pulse", .irq = 70 + OMAP_INTC_START }, 3507 { .irq = -1 }, 3508 }; 3509 3510 static struct omap_hwmod_class am35xx_emac_class = { 3511 .name = "davinci_emac", 3512 }; 3513 3514 static struct omap_hwmod am35xx_emac_hwmod = { 3515 .name = "davinci_emac", 3516 .mpu_irqs = am35xx_emac_mpu_irqs, 3517 .class = &am35xx_emac_class, 3518 /* 3519 * According to Mark Greer, the MPU will not return from WFI 3520 * when the EMAC signals an interrupt. 3521 * http://www.spinics.net/lists/arm-kernel/msg174734.html 3522 */ 3523 .flags = (HWMOD_NO_IDLEST | HWMOD_BLOCK_WFI), 3524 }; 3525 3526 /* l3_core -> davinci emac interface */ 3527 /* 3528 * XXX Should be connected to an IPSS hwmod, not the L3 directly; 3529 * but this will probably require some additional hwmod core support, 3530 * so is left as a future to-do item. 3531 */ 3532 static struct omap_hwmod_ocp_if am35xx_emac__l3 = { 3533 .master = &am35xx_emac_hwmod, 3534 .slave = &omap3xxx_l3_main_hwmod, 3535 .clk = "emac_ick", 3536 .user = OCP_USER_MPU, 3537 }; 3538 3539 static struct omap_hwmod_addr_space am35xx_emac_addrs[] = { 3540 { 3541 .pa_start = AM35XX_IPSS_EMAC_BASE, 3542 .pa_end = AM35XX_IPSS_EMAC_BASE + 0x30000 - 1, 3543 .flags = ADDR_TYPE_RT, 3544 }, 3545 { } 3546 }; 3547 3548 /* l4_core -> davinci emac */ 3549 /* 3550 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly; 3551 * but this will probably require some additional hwmod core support, 3552 * so is left as a future to-do item. 3553 */ 3554 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = { 3555 .master = &omap3xxx_l4_core_hwmod, 3556 .slave = &am35xx_emac_hwmod, 3557 .clk = "emac_ick", 3558 .addr = am35xx_emac_addrs, 3559 .user = OCP_USER_MPU, 3560 }; 3561 3562 static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = { 3563 .master = &omap3xxx_l3_main_hwmod, 3564 .slave = &omap3xxx_gpmc_hwmod, 3565 .clk = "core_l3_ick", 3566 .addr = omap3xxx_gpmc_addrs, 3567 .user = OCP_USER_MPU | OCP_USER_SDMA, 3568 }; 3569 3570 /* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */ 3571 static struct omap_hwmod_sysc_fields omap3_sham_sysc_fields = { 3572 .sidle_shift = 4, 3573 .srst_shift = 1, 3574 .autoidle_shift = 0, 3575 }; 3576 3577 static struct omap_hwmod_class_sysconfig omap3_sham_sysc = { 3578 .rev_offs = 0x5c, 3579 .sysc_offs = 0x60, 3580 .syss_offs = 0x64, 3581 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 3582 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 3583 .sysc_fields = &omap3_sham_sysc_fields, 3584 }; 3585 3586 static struct omap_hwmod_class omap3xxx_sham_class = { 3587 .name = "sham", 3588 .sysc = &omap3_sham_sysc, 3589 }; 3590 3591 static struct omap_hwmod_irq_info omap3_sham_mpu_irqs[] = { 3592 { .irq = 49 + OMAP_INTC_START, }, 3593 { .irq = -1 } 3594 }; 3595 3596 static struct omap_hwmod_dma_info omap3_sham_sdma_reqs[] = { 3597 { .name = "rx", .dma_req = 69, }, 3598 { .dma_req = -1 } 3599 }; 3600 3601 static struct omap_hwmod omap3xxx_sham_hwmod = { 3602 .name = "sham", 3603 .mpu_irqs = omap3_sham_mpu_irqs, 3604 .sdma_reqs = omap3_sham_sdma_reqs, 3605 .main_clk = "sha12_ick", 3606 .prcm = { 3607 .omap2 = { 3608 .module_offs = CORE_MOD, 3609 .prcm_reg_id = 1, 3610 .module_bit = OMAP3430_EN_SHA12_SHIFT, 3611 .idlest_reg_id = 1, 3612 .idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT, 3613 }, 3614 }, 3615 .class = &omap3xxx_sham_class, 3616 }; 3617 3618 static struct omap_hwmod_addr_space omap3xxx_sham_addrs[] = { 3619 { 3620 .pa_start = 0x480c3000, 3621 .pa_end = 0x480c3000 + 0x64 - 1, 3622 .flags = ADDR_TYPE_RT 3623 }, 3624 { } 3625 }; 3626 3627 static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = { 3628 .master = &omap3xxx_l4_core_hwmod, 3629 .slave = &omap3xxx_sham_hwmod, 3630 .clk = "sha12_ick", 3631 .addr = omap3xxx_sham_addrs, 3632 .user = OCP_USER_MPU | OCP_USER_SDMA, 3633 }; 3634 3635 /* l4_core -> AES */ 3636 static struct omap_hwmod_sysc_fields omap3xxx_aes_sysc_fields = { 3637 .sidle_shift = 6, 3638 .srst_shift = 1, 3639 .autoidle_shift = 0, 3640 }; 3641 3642 static struct omap_hwmod_class_sysconfig omap3_aes_sysc = { 3643 .rev_offs = 0x44, 3644 .sysc_offs = 0x48, 3645 .syss_offs = 0x4c, 3646 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 3647 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 3648 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 3649 .sysc_fields = &omap3xxx_aes_sysc_fields, 3650 }; 3651 3652 static struct omap_hwmod_class omap3xxx_aes_class = { 3653 .name = "aes", 3654 .sysc = &omap3_aes_sysc, 3655 }; 3656 3657 static struct omap_hwmod_dma_info omap3_aes_sdma_reqs[] = { 3658 { .name = "tx", .dma_req = 65, }, 3659 { .name = "rx", .dma_req = 66, }, 3660 { .dma_req = -1 } 3661 }; 3662 3663 static struct omap_hwmod omap3xxx_aes_hwmod = { 3664 .name = "aes", 3665 .sdma_reqs = omap3_aes_sdma_reqs, 3666 .main_clk = "aes2_ick", 3667 .prcm = { 3668 .omap2 = { 3669 .module_offs = CORE_MOD, 3670 .prcm_reg_id = 1, 3671 .module_bit = OMAP3430_EN_AES2_SHIFT, 3672 .idlest_reg_id = 1, 3673 .idlest_idle_bit = OMAP3430_ST_AES2_SHIFT, 3674 }, 3675 }, 3676 .class = &omap3xxx_aes_class, 3677 }; 3678 3679 static struct omap_hwmod_addr_space omap3xxx_aes_addrs[] = { 3680 { 3681 .pa_start = 0x480c5000, 3682 .pa_end = 0x480c5000 + 0x50 - 1, 3683 .flags = ADDR_TYPE_RT 3684 }, 3685 { } 3686 }; 3687 3688 static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = { 3689 .master = &omap3xxx_l4_core_hwmod, 3690 .slave = &omap3xxx_aes_hwmod, 3691 .clk = "aes2_ick", 3692 .addr = omap3xxx_aes_addrs, 3693 .user = OCP_USER_MPU | OCP_USER_SDMA, 3694 }; 3695 3696 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { 3697 &omap3xxx_l3_main__l4_core, 3698 &omap3xxx_l3_main__l4_per, 3699 &omap3xxx_mpu__l3_main, 3700 &omap3xxx_l3_main__l4_debugss, 3701 &omap3xxx_l4_core__l4_wkup, 3702 &omap3xxx_l4_core__mmc3, 3703 &omap3_l4_core__uart1, 3704 &omap3_l4_core__uart2, 3705 &omap3_l4_per__uart3, 3706 &omap3_l4_core__i2c1, 3707 &omap3_l4_core__i2c2, 3708 &omap3_l4_core__i2c3, 3709 &omap3xxx_l4_wkup__l4_sec, 3710 &omap3xxx_l4_wkup__timer1, 3711 &omap3xxx_l4_per__timer2, 3712 &omap3xxx_l4_per__timer3, 3713 &omap3xxx_l4_per__timer4, 3714 &omap3xxx_l4_per__timer5, 3715 &omap3xxx_l4_per__timer6, 3716 &omap3xxx_l4_per__timer7, 3717 &omap3xxx_l4_per__timer8, 3718 &omap3xxx_l4_per__timer9, 3719 &omap3xxx_l4_core__timer10, 3720 &omap3xxx_l4_core__timer11, 3721 &omap3xxx_l4_wkup__wd_timer2, 3722 &omap3xxx_l4_wkup__gpio1, 3723 &omap3xxx_l4_per__gpio2, 3724 &omap3xxx_l4_per__gpio3, 3725 &omap3xxx_l4_per__gpio4, 3726 &omap3xxx_l4_per__gpio5, 3727 &omap3xxx_l4_per__gpio6, 3728 &omap3xxx_dma_system__l3, 3729 &omap3xxx_l4_core__dma_system, 3730 &omap3xxx_l4_core__mcbsp1, 3731 &omap3xxx_l4_per__mcbsp2, 3732 &omap3xxx_l4_per__mcbsp3, 3733 &omap3xxx_l4_per__mcbsp4, 3734 &omap3xxx_l4_core__mcbsp5, 3735 &omap3xxx_l4_per__mcbsp2_sidetone, 3736 &omap3xxx_l4_per__mcbsp3_sidetone, 3737 &omap34xx_l4_core__mcspi1, 3738 &omap34xx_l4_core__mcspi2, 3739 &omap34xx_l4_core__mcspi3, 3740 &omap34xx_l4_core__mcspi4, 3741 &omap3xxx_l4_wkup__counter_32k, 3742 &omap3xxx_l3_main__gpmc, 3743 NULL, 3744 }; 3745 3746 /* GP-only hwmod links */ 3747 static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = { 3748 &omap3xxx_l4_sec__timer12, 3749 &omap3xxx_l4_core__sham, 3750 &omap3xxx_l4_core__aes, 3751 NULL 3752 }; 3753 3754 static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = { 3755 &omap3xxx_l4_sec__timer12, 3756 &omap3xxx_l4_core__sham, 3757 &omap3xxx_l4_core__aes, 3758 NULL 3759 }; 3760 3761 static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = { 3762 &omap3xxx_l4_sec__timer12, 3763 /* 3764 * Apparently the SHA/MD5 and AES accelerator IP blocks are 3765 * only present on some AM35xx chips, and no one knows which 3766 * ones. See 3767 * http://www.spinics.net/lists/arm-kernel/msg215466.html So 3768 * if you need these IP blocks on an AM35xx, try uncommenting 3769 * the following lines. 3770 */ 3771 /* &omap3xxx_l4_core__sham, */ 3772 /* &omap3xxx_l4_core__aes, */ 3773 NULL 3774 }; 3775 3776 /* 3430ES1-only hwmod links */ 3777 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = { 3778 &omap3430es1_dss__l3, 3779 &omap3430es1_l4_core__dss, 3780 NULL 3781 }; 3782 3783 /* 3430ES2+-only hwmod links */ 3784 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = { 3785 &omap3xxx_dss__l3, 3786 &omap3xxx_l4_core__dss, 3787 &omap3xxx_usbhsotg__l3, 3788 &omap3xxx_l4_core__usbhsotg, 3789 &omap3xxx_usb_host_hs__l3_main_2, 3790 &omap3xxx_l4_core__usb_host_hs, 3791 &omap3xxx_l4_core__usb_tll_hs, 3792 NULL 3793 }; 3794 3795 /* <= 3430ES3-only hwmod links */ 3796 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = { 3797 &omap3xxx_l4_core__pre_es3_mmc1, 3798 &omap3xxx_l4_core__pre_es3_mmc2, 3799 NULL 3800 }; 3801 3802 /* 3430ES3+-only hwmod links */ 3803 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = { 3804 &omap3xxx_l4_core__es3plus_mmc1, 3805 &omap3xxx_l4_core__es3plus_mmc2, 3806 NULL 3807 }; 3808 3809 /* 34xx-only hwmod links (all ES revisions) */ 3810 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = { 3811 &omap3xxx_l3__iva, 3812 &omap34xx_l4_core__sr1, 3813 &omap34xx_l4_core__sr2, 3814 &omap3xxx_l4_core__mailbox, 3815 &omap3xxx_l4_core__hdq1w, 3816 &omap3xxx_sad2d__l3, 3817 &omap3xxx_l4_core__mmu_isp, 3818 #ifdef CONFIG_OMAP_IOMMU_IVA2 3819 &omap3xxx_l3_main__mmu_iva, 3820 #endif 3821 NULL 3822 }; 3823 3824 /* 36xx-only hwmod links (all ES revisions) */ 3825 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = { 3826 &omap3xxx_l3__iva, 3827 &omap36xx_l4_per__uart4, 3828 &omap3xxx_dss__l3, 3829 &omap3xxx_l4_core__dss, 3830 &omap36xx_l4_core__sr1, 3831 &omap36xx_l4_core__sr2, 3832 &omap3xxx_usbhsotg__l3, 3833 &omap3xxx_l4_core__usbhsotg, 3834 &omap3xxx_l4_core__mailbox, 3835 &omap3xxx_usb_host_hs__l3_main_2, 3836 &omap3xxx_l4_core__usb_host_hs, 3837 &omap3xxx_l4_core__usb_tll_hs, 3838 &omap3xxx_l4_core__es3plus_mmc1, 3839 &omap3xxx_l4_core__es3plus_mmc2, 3840 &omap3xxx_l4_core__hdq1w, 3841 &omap3xxx_sad2d__l3, 3842 &omap3xxx_l4_core__mmu_isp, 3843 #ifdef CONFIG_OMAP_IOMMU_IVA2 3844 &omap3xxx_l3_main__mmu_iva, 3845 #endif 3846 NULL 3847 }; 3848 3849 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = { 3850 &omap3xxx_dss__l3, 3851 &omap3xxx_l4_core__dss, 3852 &am35xx_usbhsotg__l3, 3853 &am35xx_l4_core__usbhsotg, 3854 &am35xx_l4_core__uart4, 3855 &omap3xxx_usb_host_hs__l3_main_2, 3856 &omap3xxx_l4_core__usb_host_hs, 3857 &omap3xxx_l4_core__usb_tll_hs, 3858 &omap3xxx_l4_core__es3plus_mmc1, 3859 &omap3xxx_l4_core__es3plus_mmc2, 3860 &omap3xxx_l4_core__hdq1w, 3861 &am35xx_mdio__l3, 3862 &am35xx_l4_core__mdio, 3863 &am35xx_emac__l3, 3864 &am35xx_l4_core__emac, 3865 NULL 3866 }; 3867 3868 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = { 3869 &omap3xxx_l4_core__dss_dispc, 3870 &omap3xxx_l4_core__dss_dsi1, 3871 &omap3xxx_l4_core__dss_rfbi, 3872 &omap3xxx_l4_core__dss_venc, 3873 NULL 3874 }; 3875 3876 int __init omap3xxx_hwmod_init(void) 3877 { 3878 int r; 3879 struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL; 3880 unsigned int rev; 3881 3882 omap_hwmod_init(); 3883 3884 /* Register hwmod links common to all OMAP3 */ 3885 r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs); 3886 if (r < 0) 3887 return r; 3888 3889 rev = omap_rev(); 3890 3891 /* 3892 * Register hwmod links common to individual OMAP3 families, all 3893 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx) 3894 * All possible revisions should be included in this conditional. 3895 */ 3896 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || 3897 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 || 3898 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { 3899 h = omap34xx_hwmod_ocp_ifs; 3900 h_gp = omap34xx_gp_hwmod_ocp_ifs; 3901 } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) { 3902 h = am35xx_hwmod_ocp_ifs; 3903 h_gp = am35xx_gp_hwmod_ocp_ifs; 3904 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 || 3905 rev == OMAP3630_REV_ES1_2) { 3906 h = omap36xx_hwmod_ocp_ifs; 3907 h_gp = omap36xx_gp_hwmod_ocp_ifs; 3908 } else { 3909 WARN(1, "OMAP3 hwmod family init: unknown chip type\n"); 3910 return -EINVAL; 3911 } 3912 3913 r = omap_hwmod_register_links(h); 3914 if (r < 0) 3915 return r; 3916 3917 /* Register GP-only hwmod links. */ 3918 if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) { 3919 r = omap_hwmod_register_links(h_gp); 3920 if (r < 0) 3921 return r; 3922 } 3923 3924 3925 /* 3926 * Register hwmod links specific to certain ES levels of a 3927 * particular family of silicon (e.g., 34xx ES1.0) 3928 */ 3929 h = NULL; 3930 if (rev == OMAP3430_REV_ES1_0) { 3931 h = omap3430es1_hwmod_ocp_ifs; 3932 } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 || 3933 rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || 3934 rev == OMAP3430_REV_ES3_1_2) { 3935 h = omap3430es2plus_hwmod_ocp_ifs; 3936 } 3937 3938 if (h) { 3939 r = omap_hwmod_register_links(h); 3940 if (r < 0) 3941 return r; 3942 } 3943 3944 h = NULL; 3945 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || 3946 rev == OMAP3430_REV_ES2_1) { 3947 h = omap3430_pre_es3_hwmod_ocp_ifs; 3948 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || 3949 rev == OMAP3430_REV_ES3_1_2) { 3950 h = omap3430_es3plus_hwmod_ocp_ifs; 3951 } 3952 3953 if (h) 3954 r = omap_hwmod_register_links(h); 3955 if (r < 0) 3956 return r; 3957 3958 /* 3959 * DSS code presumes that dss_core hwmod is handled first, 3960 * _before_ any other DSS related hwmods so register common 3961 * DSS hwmod links last to ensure that dss_core is already 3962 * registered. Otherwise some change things may happen, for 3963 * ex. if dispc is handled before dss_core and DSS is enabled 3964 * in bootloader DISPC will be reset with outputs enabled 3965 * which sometimes leads to unrecoverable L3 error. XXX The 3966 * long-term fix to this is to ensure hwmods are set up in 3967 * dependency order in the hwmod core code. 3968 */ 3969 r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs); 3970 3971 return r; 3972 } 3973