1 /* 2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips 3 * 4 * Copyright (C) 2009-2011 Nokia Corporation 5 * Copyright (C) 2012 Texas Instruments, Inc. 6 * Paul Walmsley 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * The data in this file should be completely autogeneratable from 13 * the TI hardware database or other technical documentation. 14 * 15 * XXX these should be marked initdata for multi-OMAP kernels 16 */ 17 18 #include <linux/i2c-omap.h> 19 #include <linux/power/smartreflex.h> 20 #include <linux/platform_data/gpio-omap.h> 21 22 #include <linux/omap-dma.h> 23 #include "l3_3xxx.h" 24 #include "l4_3xxx.h" 25 #include <linux/platform_data/asoc-ti-mcbsp.h> 26 #include <linux/platform_data/spi-omap2-mcspi.h> 27 #include <linux/platform_data/iommu-omap.h> 28 #include <plat/dmtimer.h> 29 30 #include "am35xx.h" 31 32 #include "soc.h" 33 #include "omap_hwmod.h" 34 #include "omap_hwmod_common_data.h" 35 #include "prm-regbits-34xx.h" 36 #include "cm-regbits-34xx.h" 37 38 #include "dma.h" 39 #include "i2c.h" 40 #include "mmc.h" 41 #include "wd_timer.h" 42 #include "serial.h" 43 44 /* 45 * OMAP3xxx hardware module integration data 46 * 47 * All of the data in this section should be autogeneratable from the 48 * TI hardware database or other technical documentation. Data that 49 * is driver-specific or driver-kernel integration-specific belongs 50 * elsewhere. 51 */ 52 53 /* 54 * IP blocks 55 */ 56 57 /* L3 */ 58 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = { 59 { .irq = 9 + OMAP_INTC_START, }, 60 { .irq = 10 + OMAP_INTC_START, }, 61 { .irq = -1 }, 62 }; 63 64 static struct omap_hwmod omap3xxx_l3_main_hwmod = { 65 .name = "l3_main", 66 .class = &l3_hwmod_class, 67 .mpu_irqs = omap3xxx_l3_main_irqs, 68 .flags = HWMOD_NO_IDLEST, 69 }; 70 71 /* L4 CORE */ 72 static struct omap_hwmod omap3xxx_l4_core_hwmod = { 73 .name = "l4_core", 74 .class = &l4_hwmod_class, 75 .flags = HWMOD_NO_IDLEST, 76 }; 77 78 /* L4 PER */ 79 static struct omap_hwmod omap3xxx_l4_per_hwmod = { 80 .name = "l4_per", 81 .class = &l4_hwmod_class, 82 .flags = HWMOD_NO_IDLEST, 83 }; 84 85 /* L4 WKUP */ 86 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { 87 .name = "l4_wkup", 88 .class = &l4_hwmod_class, 89 .flags = HWMOD_NO_IDLEST, 90 }; 91 92 /* L4 SEC */ 93 static struct omap_hwmod omap3xxx_l4_sec_hwmod = { 94 .name = "l4_sec", 95 .class = &l4_hwmod_class, 96 .flags = HWMOD_NO_IDLEST, 97 }; 98 99 /* MPU */ 100 static struct omap_hwmod_irq_info omap3xxx_mpu_irqs[] = { 101 { .name = "pmu", .irq = 3 + OMAP_INTC_START }, 102 { .irq = -1 } 103 }; 104 105 static struct omap_hwmod omap3xxx_mpu_hwmod = { 106 .name = "mpu", 107 .mpu_irqs = omap3xxx_mpu_irqs, 108 .class = &mpu_hwmod_class, 109 .main_clk = "arm_fck", 110 }; 111 112 /* IVA2 (IVA2) */ 113 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = { 114 { .name = "logic", .rst_shift = 0, .st_shift = 8 }, 115 { .name = "seq0", .rst_shift = 1, .st_shift = 9 }, 116 { .name = "seq1", .rst_shift = 2, .st_shift = 10 }, 117 }; 118 119 static struct omap_hwmod omap3xxx_iva_hwmod = { 120 .name = "iva", 121 .class = &iva_hwmod_class, 122 .clkdm_name = "iva2_clkdm", 123 .rst_lines = omap3xxx_iva_resets, 124 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets), 125 .main_clk = "iva2_ck", 126 .prcm = { 127 .omap2 = { 128 .module_offs = OMAP3430_IVA2_MOD, 129 .prcm_reg_id = 1, 130 .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, 131 .idlest_reg_id = 1, 132 .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT, 133 } 134 }, 135 }; 136 137 /* 138 * 'debugss' class 139 * debug and emulation sub system 140 */ 141 142 static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = { 143 .name = "debugss", 144 }; 145 146 /* debugss */ 147 static struct omap_hwmod omap3xxx_debugss_hwmod = { 148 .name = "debugss", 149 .class = &omap3xxx_debugss_hwmod_class, 150 .clkdm_name = "emu_clkdm", 151 .main_clk = "emu_src_ck", 152 .flags = HWMOD_NO_IDLEST, 153 }; 154 155 /* timer class */ 156 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { 157 .rev_offs = 0x0000, 158 .sysc_offs = 0x0010, 159 .syss_offs = 0x0014, 160 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | 161 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 162 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | 163 SYSS_HAS_RESET_STATUS), 164 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 165 .clockact = CLOCKACT_TEST_ICLK, 166 .sysc_fields = &omap_hwmod_sysc_type1, 167 }; 168 169 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { 170 .name = "timer", 171 .sysc = &omap3xxx_timer_sysc, 172 }; 173 174 /* secure timers dev attribute */ 175 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = { 176 .timer_capability = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE, 177 }; 178 179 /* always-on timers dev attribute */ 180 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { 181 .timer_capability = OMAP_TIMER_ALWON, 182 }; 183 184 /* pwm timers dev attribute */ 185 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { 186 .timer_capability = OMAP_TIMER_HAS_PWM, 187 }; 188 189 /* timers with DSP interrupt dev attribute */ 190 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = { 191 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ, 192 }; 193 194 /* pwm timers with DSP interrupt dev attribute */ 195 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = { 196 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM, 197 }; 198 199 /* timer1 */ 200 static struct omap_hwmod omap3xxx_timer1_hwmod = { 201 .name = "timer1", 202 .mpu_irqs = omap2_timer1_mpu_irqs, 203 .main_clk = "gpt1_fck", 204 .prcm = { 205 .omap2 = { 206 .prcm_reg_id = 1, 207 .module_bit = OMAP3430_EN_GPT1_SHIFT, 208 .module_offs = WKUP_MOD, 209 .idlest_reg_id = 1, 210 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT, 211 }, 212 }, 213 .dev_attr = &capability_alwon_dev_attr, 214 .class = &omap3xxx_timer_hwmod_class, 215 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 216 }; 217 218 /* timer2 */ 219 static struct omap_hwmod omap3xxx_timer2_hwmod = { 220 .name = "timer2", 221 .mpu_irqs = omap2_timer2_mpu_irqs, 222 .main_clk = "gpt2_fck", 223 .prcm = { 224 .omap2 = { 225 .prcm_reg_id = 1, 226 .module_bit = OMAP3430_EN_GPT2_SHIFT, 227 .module_offs = OMAP3430_PER_MOD, 228 .idlest_reg_id = 1, 229 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT, 230 }, 231 }, 232 .class = &omap3xxx_timer_hwmod_class, 233 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 234 }; 235 236 /* timer3 */ 237 static struct omap_hwmod omap3xxx_timer3_hwmod = { 238 .name = "timer3", 239 .mpu_irqs = omap2_timer3_mpu_irqs, 240 .main_clk = "gpt3_fck", 241 .prcm = { 242 .omap2 = { 243 .prcm_reg_id = 1, 244 .module_bit = OMAP3430_EN_GPT3_SHIFT, 245 .module_offs = OMAP3430_PER_MOD, 246 .idlest_reg_id = 1, 247 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT, 248 }, 249 }, 250 .class = &omap3xxx_timer_hwmod_class, 251 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 252 }; 253 254 /* timer4 */ 255 static struct omap_hwmod omap3xxx_timer4_hwmod = { 256 .name = "timer4", 257 .mpu_irqs = omap2_timer4_mpu_irqs, 258 .main_clk = "gpt4_fck", 259 .prcm = { 260 .omap2 = { 261 .prcm_reg_id = 1, 262 .module_bit = OMAP3430_EN_GPT4_SHIFT, 263 .module_offs = OMAP3430_PER_MOD, 264 .idlest_reg_id = 1, 265 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT, 266 }, 267 }, 268 .class = &omap3xxx_timer_hwmod_class, 269 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 270 }; 271 272 /* timer5 */ 273 static struct omap_hwmod omap3xxx_timer5_hwmod = { 274 .name = "timer5", 275 .mpu_irqs = omap2_timer5_mpu_irqs, 276 .main_clk = "gpt5_fck", 277 .prcm = { 278 .omap2 = { 279 .prcm_reg_id = 1, 280 .module_bit = OMAP3430_EN_GPT5_SHIFT, 281 .module_offs = OMAP3430_PER_MOD, 282 .idlest_reg_id = 1, 283 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT, 284 }, 285 }, 286 .dev_attr = &capability_dsp_dev_attr, 287 .class = &omap3xxx_timer_hwmod_class, 288 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 289 }; 290 291 /* timer6 */ 292 static struct omap_hwmod omap3xxx_timer6_hwmod = { 293 .name = "timer6", 294 .mpu_irqs = omap2_timer6_mpu_irqs, 295 .main_clk = "gpt6_fck", 296 .prcm = { 297 .omap2 = { 298 .prcm_reg_id = 1, 299 .module_bit = OMAP3430_EN_GPT6_SHIFT, 300 .module_offs = OMAP3430_PER_MOD, 301 .idlest_reg_id = 1, 302 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT, 303 }, 304 }, 305 .dev_attr = &capability_dsp_dev_attr, 306 .class = &omap3xxx_timer_hwmod_class, 307 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 308 }; 309 310 /* timer7 */ 311 static struct omap_hwmod omap3xxx_timer7_hwmod = { 312 .name = "timer7", 313 .mpu_irqs = omap2_timer7_mpu_irqs, 314 .main_clk = "gpt7_fck", 315 .prcm = { 316 .omap2 = { 317 .prcm_reg_id = 1, 318 .module_bit = OMAP3430_EN_GPT7_SHIFT, 319 .module_offs = OMAP3430_PER_MOD, 320 .idlest_reg_id = 1, 321 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT, 322 }, 323 }, 324 .dev_attr = &capability_dsp_dev_attr, 325 .class = &omap3xxx_timer_hwmod_class, 326 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 327 }; 328 329 /* timer8 */ 330 static struct omap_hwmod omap3xxx_timer8_hwmod = { 331 .name = "timer8", 332 .mpu_irqs = omap2_timer8_mpu_irqs, 333 .main_clk = "gpt8_fck", 334 .prcm = { 335 .omap2 = { 336 .prcm_reg_id = 1, 337 .module_bit = OMAP3430_EN_GPT8_SHIFT, 338 .module_offs = OMAP3430_PER_MOD, 339 .idlest_reg_id = 1, 340 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT, 341 }, 342 }, 343 .dev_attr = &capability_dsp_pwm_dev_attr, 344 .class = &omap3xxx_timer_hwmod_class, 345 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 346 }; 347 348 /* timer9 */ 349 static struct omap_hwmod omap3xxx_timer9_hwmod = { 350 .name = "timer9", 351 .mpu_irqs = omap2_timer9_mpu_irqs, 352 .main_clk = "gpt9_fck", 353 .prcm = { 354 .omap2 = { 355 .prcm_reg_id = 1, 356 .module_bit = OMAP3430_EN_GPT9_SHIFT, 357 .module_offs = OMAP3430_PER_MOD, 358 .idlest_reg_id = 1, 359 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT, 360 }, 361 }, 362 .dev_attr = &capability_pwm_dev_attr, 363 .class = &omap3xxx_timer_hwmod_class, 364 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 365 }; 366 367 /* timer10 */ 368 static struct omap_hwmod omap3xxx_timer10_hwmod = { 369 .name = "timer10", 370 .mpu_irqs = omap2_timer10_mpu_irqs, 371 .main_clk = "gpt10_fck", 372 .prcm = { 373 .omap2 = { 374 .prcm_reg_id = 1, 375 .module_bit = OMAP3430_EN_GPT10_SHIFT, 376 .module_offs = CORE_MOD, 377 .idlest_reg_id = 1, 378 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT, 379 }, 380 }, 381 .dev_attr = &capability_pwm_dev_attr, 382 .class = &omap3xxx_timer_hwmod_class, 383 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 384 }; 385 386 /* timer11 */ 387 static struct omap_hwmod omap3xxx_timer11_hwmod = { 388 .name = "timer11", 389 .mpu_irqs = omap2_timer11_mpu_irqs, 390 .main_clk = "gpt11_fck", 391 .prcm = { 392 .omap2 = { 393 .prcm_reg_id = 1, 394 .module_bit = OMAP3430_EN_GPT11_SHIFT, 395 .module_offs = CORE_MOD, 396 .idlest_reg_id = 1, 397 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT, 398 }, 399 }, 400 .dev_attr = &capability_pwm_dev_attr, 401 .class = &omap3xxx_timer_hwmod_class, 402 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 403 }; 404 405 /* timer12 */ 406 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { 407 { .irq = 95 + OMAP_INTC_START, }, 408 { .irq = -1 }, 409 }; 410 411 static struct omap_hwmod omap3xxx_timer12_hwmod = { 412 .name = "timer12", 413 .mpu_irqs = omap3xxx_timer12_mpu_irqs, 414 .main_clk = "gpt12_fck", 415 .prcm = { 416 .omap2 = { 417 .prcm_reg_id = 1, 418 .module_bit = OMAP3430_EN_GPT12_SHIFT, 419 .module_offs = WKUP_MOD, 420 .idlest_reg_id = 1, 421 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT, 422 }, 423 }, 424 .dev_attr = &capability_secure_dev_attr, 425 .class = &omap3xxx_timer_hwmod_class, 426 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 427 }; 428 429 /* 430 * 'wd_timer' class 431 * 32-bit watchdog upward counter that generates a pulse on the reset pin on 432 * overflow condition 433 */ 434 435 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { 436 .rev_offs = 0x0000, 437 .sysc_offs = 0x0010, 438 .syss_offs = 0x0014, 439 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | 440 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 441 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | 442 SYSS_HAS_RESET_STATUS), 443 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 444 .sysc_fields = &omap_hwmod_sysc_type1, 445 }; 446 447 /* I2C common */ 448 static struct omap_hwmod_class_sysconfig i2c_sysc = { 449 .rev_offs = 0x00, 450 .sysc_offs = 0x20, 451 .syss_offs = 0x10, 452 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 453 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 454 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 455 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 456 .clockact = CLOCKACT_TEST_ICLK, 457 .sysc_fields = &omap_hwmod_sysc_type1, 458 }; 459 460 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { 461 .name = "wd_timer", 462 .sysc = &omap3xxx_wd_timer_sysc, 463 .pre_shutdown = &omap2_wd_timer_disable, 464 .reset = &omap2_wd_timer_reset, 465 }; 466 467 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { 468 .name = "wd_timer2", 469 .class = &omap3xxx_wd_timer_hwmod_class, 470 .main_clk = "wdt2_fck", 471 .prcm = { 472 .omap2 = { 473 .prcm_reg_id = 1, 474 .module_bit = OMAP3430_EN_WDT2_SHIFT, 475 .module_offs = WKUP_MOD, 476 .idlest_reg_id = 1, 477 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, 478 }, 479 }, 480 /* 481 * XXX: Use software supervised mode, HW supervised smartidle seems to 482 * block CORE power domain idle transitions. Maybe a HW bug in wdt2? 483 */ 484 .flags = HWMOD_SWSUP_SIDLE, 485 }; 486 487 /* UART1 */ 488 static struct omap_hwmod omap3xxx_uart1_hwmod = { 489 .name = "uart1", 490 .mpu_irqs = omap2_uart1_mpu_irqs, 491 .sdma_reqs = omap2_uart1_sdma_reqs, 492 .main_clk = "uart1_fck", 493 .flags = HWMOD_SWSUP_SIDLE_ACT, 494 .prcm = { 495 .omap2 = { 496 .module_offs = CORE_MOD, 497 .prcm_reg_id = 1, 498 .module_bit = OMAP3430_EN_UART1_SHIFT, 499 .idlest_reg_id = 1, 500 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, 501 }, 502 }, 503 .class = &omap2_uart_class, 504 }; 505 506 /* UART2 */ 507 static struct omap_hwmod omap3xxx_uart2_hwmod = { 508 .name = "uart2", 509 .mpu_irqs = omap2_uart2_mpu_irqs, 510 .sdma_reqs = omap2_uart2_sdma_reqs, 511 .main_clk = "uart2_fck", 512 .flags = HWMOD_SWSUP_SIDLE_ACT, 513 .prcm = { 514 .omap2 = { 515 .module_offs = CORE_MOD, 516 .prcm_reg_id = 1, 517 .module_bit = OMAP3430_EN_UART2_SHIFT, 518 .idlest_reg_id = 1, 519 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, 520 }, 521 }, 522 .class = &omap2_uart_class, 523 }; 524 525 /* UART3 */ 526 static struct omap_hwmod omap3xxx_uart3_hwmod = { 527 .name = "uart3", 528 .mpu_irqs = omap2_uart3_mpu_irqs, 529 .sdma_reqs = omap2_uart3_sdma_reqs, 530 .main_clk = "uart3_fck", 531 .flags = HWMOD_SWSUP_SIDLE_ACT, 532 .prcm = { 533 .omap2 = { 534 .module_offs = OMAP3430_PER_MOD, 535 .prcm_reg_id = 1, 536 .module_bit = OMAP3430_EN_UART3_SHIFT, 537 .idlest_reg_id = 1, 538 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, 539 }, 540 }, 541 .class = &omap2_uart_class, 542 }; 543 544 /* UART4 */ 545 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { 546 { .irq = 80 + OMAP_INTC_START, }, 547 { .irq = -1 }, 548 }; 549 550 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { 551 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, }, 552 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, }, 553 { .dma_req = -1 } 554 }; 555 556 static struct omap_hwmod omap36xx_uart4_hwmod = { 557 .name = "uart4", 558 .mpu_irqs = uart4_mpu_irqs, 559 .sdma_reqs = uart4_sdma_reqs, 560 .main_clk = "uart4_fck", 561 .flags = HWMOD_SWSUP_SIDLE_ACT, 562 .prcm = { 563 .omap2 = { 564 .module_offs = OMAP3430_PER_MOD, 565 .prcm_reg_id = 1, 566 .module_bit = OMAP3630_EN_UART4_SHIFT, 567 .idlest_reg_id = 1, 568 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, 569 }, 570 }, 571 .class = &omap2_uart_class, 572 }; 573 574 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = { 575 { .irq = 84 + OMAP_INTC_START, }, 576 { .irq = -1 }, 577 }; 578 579 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = { 580 { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, }, 581 { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, }, 582 { .dma_req = -1 } 583 }; 584 585 /* 586 * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or 587 * uart2_fck being enabled. So we add uart1_fck as an optional clock, 588 * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET. This really 589 * should not be needed. The functional clock structure of the AM35xx 590 * UART4 is extremely unclear and opaque; it is unclear what the role 591 * of uart1/2_fck is for the UART4. Any clarification from either 592 * empirical testing or the AM3505/3517 hardware designers would be 593 * most welcome. 594 */ 595 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = { 596 { .role = "softreset_uart1_fck", .clk = "uart1_fck" }, 597 }; 598 599 static struct omap_hwmod am35xx_uart4_hwmod = { 600 .name = "uart4", 601 .mpu_irqs = am35xx_uart4_mpu_irqs, 602 .sdma_reqs = am35xx_uart4_sdma_reqs, 603 .main_clk = "uart4_fck", 604 .prcm = { 605 .omap2 = { 606 .module_offs = CORE_MOD, 607 .prcm_reg_id = 1, 608 .module_bit = AM35XX_EN_UART4_SHIFT, 609 .idlest_reg_id = 1, 610 .idlest_idle_bit = AM35XX_ST_UART4_SHIFT, 611 }, 612 }, 613 .opt_clks = am35xx_uart4_opt_clks, 614 .opt_clks_cnt = ARRAY_SIZE(am35xx_uart4_opt_clks), 615 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 616 .class = &omap2_uart_class, 617 }; 618 619 static struct omap_hwmod_class i2c_class = { 620 .name = "i2c", 621 .sysc = &i2c_sysc, 622 .rev = OMAP_I2C_IP_VERSION_1, 623 .reset = &omap_i2c_reset, 624 }; 625 626 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { 627 { .name = "dispc", .dma_req = 5 }, 628 { .name = "dsi1", .dma_req = 74 }, 629 { .dma_req = -1 } 630 }; 631 632 /* dss */ 633 static struct omap_hwmod_opt_clk dss_opt_clks[] = { 634 /* 635 * The DSS HW needs all DSS clocks enabled during reset. The dss_core 636 * driver does not use these clocks. 637 */ 638 { .role = "sys_clk", .clk = "dss2_alwon_fck" }, 639 { .role = "tv_clk", .clk = "dss_tv_fck" }, 640 /* required only on OMAP3430 */ 641 { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, 642 }; 643 644 static struct omap_hwmod omap3430es1_dss_core_hwmod = { 645 .name = "dss_core", 646 .class = &omap2_dss_hwmod_class, 647 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ 648 .sdma_reqs = omap3xxx_dss_sdma_chs, 649 .prcm = { 650 .omap2 = { 651 .prcm_reg_id = 1, 652 .module_bit = OMAP3430_EN_DSS1_SHIFT, 653 .module_offs = OMAP3430_DSS_MOD, 654 .idlest_reg_id = 1, 655 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT, 656 }, 657 }, 658 .opt_clks = dss_opt_clks, 659 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), 660 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, 661 }; 662 663 static struct omap_hwmod omap3xxx_dss_core_hwmod = { 664 .name = "dss_core", 665 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 666 .class = &omap2_dss_hwmod_class, 667 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ 668 .sdma_reqs = omap3xxx_dss_sdma_chs, 669 .prcm = { 670 .omap2 = { 671 .prcm_reg_id = 1, 672 .module_bit = OMAP3430_EN_DSS1_SHIFT, 673 .module_offs = OMAP3430_DSS_MOD, 674 .idlest_reg_id = 1, 675 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT, 676 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT, 677 }, 678 }, 679 .opt_clks = dss_opt_clks, 680 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), 681 }; 682 683 /* 684 * 'dispc' class 685 * display controller 686 */ 687 688 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = { 689 .rev_offs = 0x0000, 690 .sysc_offs = 0x0010, 691 .syss_offs = 0x0014, 692 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | 693 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | 694 SYSC_HAS_ENAWAKEUP), 695 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 696 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 697 .sysc_fields = &omap_hwmod_sysc_type1, 698 }; 699 700 static struct omap_hwmod_class omap3_dispc_hwmod_class = { 701 .name = "dispc", 702 .sysc = &omap3_dispc_sysc, 703 }; 704 705 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { 706 .name = "dss_dispc", 707 .class = &omap3_dispc_hwmod_class, 708 .mpu_irqs = omap2_dispc_irqs, 709 .main_clk = "dss1_alwon_fck", 710 .prcm = { 711 .omap2 = { 712 .prcm_reg_id = 1, 713 .module_bit = OMAP3430_EN_DSS1_SHIFT, 714 .module_offs = OMAP3430_DSS_MOD, 715 }, 716 }, 717 .flags = HWMOD_NO_IDLEST, 718 .dev_attr = &omap2_3_dss_dispc_dev_attr 719 }; 720 721 /* 722 * 'dsi' class 723 * display serial interface controller 724 */ 725 726 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = { 727 .name = "dsi", 728 }; 729 730 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = { 731 { .irq = 25 + OMAP_INTC_START, }, 732 { .irq = -1 }, 733 }; 734 735 /* dss_dsi1 */ 736 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { 737 { .role = "sys_clk", .clk = "dss2_alwon_fck" }, 738 }; 739 740 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { 741 .name = "dss_dsi1", 742 .class = &omap3xxx_dsi_hwmod_class, 743 .mpu_irqs = omap3xxx_dsi1_irqs, 744 .main_clk = "dss1_alwon_fck", 745 .prcm = { 746 .omap2 = { 747 .prcm_reg_id = 1, 748 .module_bit = OMAP3430_EN_DSS1_SHIFT, 749 .module_offs = OMAP3430_DSS_MOD, 750 }, 751 }, 752 .opt_clks = dss_dsi1_opt_clks, 753 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), 754 .flags = HWMOD_NO_IDLEST, 755 }; 756 757 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { 758 { .role = "ick", .clk = "dss_ick" }, 759 }; 760 761 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { 762 .name = "dss_rfbi", 763 .class = &omap2_rfbi_hwmod_class, 764 .main_clk = "dss1_alwon_fck", 765 .prcm = { 766 .omap2 = { 767 .prcm_reg_id = 1, 768 .module_bit = OMAP3430_EN_DSS1_SHIFT, 769 .module_offs = OMAP3430_DSS_MOD, 770 }, 771 }, 772 .opt_clks = dss_rfbi_opt_clks, 773 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), 774 .flags = HWMOD_NO_IDLEST, 775 }; 776 777 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = { 778 /* required only on OMAP3430 */ 779 { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, 780 }; 781 782 static struct omap_hwmod omap3xxx_dss_venc_hwmod = { 783 .name = "dss_venc", 784 .class = &omap2_venc_hwmod_class, 785 .main_clk = "dss_tv_fck", 786 .prcm = { 787 .omap2 = { 788 .prcm_reg_id = 1, 789 .module_bit = OMAP3430_EN_DSS1_SHIFT, 790 .module_offs = OMAP3430_DSS_MOD, 791 }, 792 }, 793 .opt_clks = dss_venc_opt_clks, 794 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks), 795 .flags = HWMOD_NO_IDLEST, 796 }; 797 798 /* I2C1 */ 799 static struct omap_i2c_dev_attr i2c1_dev_attr = { 800 .fifo_depth = 8, /* bytes */ 801 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2, 802 }; 803 804 static struct omap_hwmod omap3xxx_i2c1_hwmod = { 805 .name = "i2c1", 806 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 807 .mpu_irqs = omap2_i2c1_mpu_irqs, 808 .sdma_reqs = omap2_i2c1_sdma_reqs, 809 .main_clk = "i2c1_fck", 810 .prcm = { 811 .omap2 = { 812 .module_offs = CORE_MOD, 813 .prcm_reg_id = 1, 814 .module_bit = OMAP3430_EN_I2C1_SHIFT, 815 .idlest_reg_id = 1, 816 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT, 817 }, 818 }, 819 .class = &i2c_class, 820 .dev_attr = &i2c1_dev_attr, 821 }; 822 823 /* I2C2 */ 824 static struct omap_i2c_dev_attr i2c2_dev_attr = { 825 .fifo_depth = 8, /* bytes */ 826 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2, 827 }; 828 829 static struct omap_hwmod omap3xxx_i2c2_hwmod = { 830 .name = "i2c2", 831 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 832 .mpu_irqs = omap2_i2c2_mpu_irqs, 833 .sdma_reqs = omap2_i2c2_sdma_reqs, 834 .main_clk = "i2c2_fck", 835 .prcm = { 836 .omap2 = { 837 .module_offs = CORE_MOD, 838 .prcm_reg_id = 1, 839 .module_bit = OMAP3430_EN_I2C2_SHIFT, 840 .idlest_reg_id = 1, 841 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT, 842 }, 843 }, 844 .class = &i2c_class, 845 .dev_attr = &i2c2_dev_attr, 846 }; 847 848 /* I2C3 */ 849 static struct omap_i2c_dev_attr i2c3_dev_attr = { 850 .fifo_depth = 64, /* bytes */ 851 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2, 852 }; 853 854 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { 855 { .irq = 61 + OMAP_INTC_START, }, 856 { .irq = -1 }, 857 }; 858 859 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { 860 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX }, 861 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX }, 862 { .dma_req = -1 } 863 }; 864 865 static struct omap_hwmod omap3xxx_i2c3_hwmod = { 866 .name = "i2c3", 867 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 868 .mpu_irqs = i2c3_mpu_irqs, 869 .sdma_reqs = i2c3_sdma_reqs, 870 .main_clk = "i2c3_fck", 871 .prcm = { 872 .omap2 = { 873 .module_offs = CORE_MOD, 874 .prcm_reg_id = 1, 875 .module_bit = OMAP3430_EN_I2C3_SHIFT, 876 .idlest_reg_id = 1, 877 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT, 878 }, 879 }, 880 .class = &i2c_class, 881 .dev_attr = &i2c3_dev_attr, 882 }; 883 884 /* 885 * 'gpio' class 886 * general purpose io module 887 */ 888 889 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = { 890 .rev_offs = 0x0000, 891 .sysc_offs = 0x0010, 892 .syss_offs = 0x0014, 893 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | 894 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | 895 SYSS_HAS_RESET_STATUS), 896 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 897 .sysc_fields = &omap_hwmod_sysc_type1, 898 }; 899 900 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = { 901 .name = "gpio", 902 .sysc = &omap3xxx_gpio_sysc, 903 .rev = 1, 904 }; 905 906 /* gpio_dev_attr */ 907 static struct omap_gpio_dev_attr gpio_dev_attr = { 908 .bank_width = 32, 909 .dbck_flag = true, 910 }; 911 912 /* gpio1 */ 913 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { 914 { .role = "dbclk", .clk = "gpio1_dbck", }, 915 }; 916 917 static struct omap_hwmod omap3xxx_gpio1_hwmod = { 918 .name = "gpio1", 919 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 920 .mpu_irqs = omap2_gpio1_irqs, 921 .main_clk = "gpio1_ick", 922 .opt_clks = gpio1_opt_clks, 923 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), 924 .prcm = { 925 .omap2 = { 926 .prcm_reg_id = 1, 927 .module_bit = OMAP3430_EN_GPIO1_SHIFT, 928 .module_offs = WKUP_MOD, 929 .idlest_reg_id = 1, 930 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT, 931 }, 932 }, 933 .class = &omap3xxx_gpio_hwmod_class, 934 .dev_attr = &gpio_dev_attr, 935 }; 936 937 /* gpio2 */ 938 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { 939 { .role = "dbclk", .clk = "gpio2_dbck", }, 940 }; 941 942 static struct omap_hwmod omap3xxx_gpio2_hwmod = { 943 .name = "gpio2", 944 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 945 .mpu_irqs = omap2_gpio2_irqs, 946 .main_clk = "gpio2_ick", 947 .opt_clks = gpio2_opt_clks, 948 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), 949 .prcm = { 950 .omap2 = { 951 .prcm_reg_id = 1, 952 .module_bit = OMAP3430_EN_GPIO2_SHIFT, 953 .module_offs = OMAP3430_PER_MOD, 954 .idlest_reg_id = 1, 955 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT, 956 }, 957 }, 958 .class = &omap3xxx_gpio_hwmod_class, 959 .dev_attr = &gpio_dev_attr, 960 }; 961 962 /* gpio3 */ 963 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { 964 { .role = "dbclk", .clk = "gpio3_dbck", }, 965 }; 966 967 static struct omap_hwmod omap3xxx_gpio3_hwmod = { 968 .name = "gpio3", 969 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 970 .mpu_irqs = omap2_gpio3_irqs, 971 .main_clk = "gpio3_ick", 972 .opt_clks = gpio3_opt_clks, 973 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), 974 .prcm = { 975 .omap2 = { 976 .prcm_reg_id = 1, 977 .module_bit = OMAP3430_EN_GPIO3_SHIFT, 978 .module_offs = OMAP3430_PER_MOD, 979 .idlest_reg_id = 1, 980 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT, 981 }, 982 }, 983 .class = &omap3xxx_gpio_hwmod_class, 984 .dev_attr = &gpio_dev_attr, 985 }; 986 987 /* gpio4 */ 988 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { 989 { .role = "dbclk", .clk = "gpio4_dbck", }, 990 }; 991 992 static struct omap_hwmod omap3xxx_gpio4_hwmod = { 993 .name = "gpio4", 994 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 995 .mpu_irqs = omap2_gpio4_irqs, 996 .main_clk = "gpio4_ick", 997 .opt_clks = gpio4_opt_clks, 998 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), 999 .prcm = { 1000 .omap2 = { 1001 .prcm_reg_id = 1, 1002 .module_bit = OMAP3430_EN_GPIO4_SHIFT, 1003 .module_offs = OMAP3430_PER_MOD, 1004 .idlest_reg_id = 1, 1005 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT, 1006 }, 1007 }, 1008 .class = &omap3xxx_gpio_hwmod_class, 1009 .dev_attr = &gpio_dev_attr, 1010 }; 1011 1012 /* gpio5 */ 1013 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = { 1014 { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */ 1015 { .irq = -1 }, 1016 }; 1017 1018 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { 1019 { .role = "dbclk", .clk = "gpio5_dbck", }, 1020 }; 1021 1022 static struct omap_hwmod omap3xxx_gpio5_hwmod = { 1023 .name = "gpio5", 1024 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1025 .mpu_irqs = omap3xxx_gpio5_irqs, 1026 .main_clk = "gpio5_ick", 1027 .opt_clks = gpio5_opt_clks, 1028 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), 1029 .prcm = { 1030 .omap2 = { 1031 .prcm_reg_id = 1, 1032 .module_bit = OMAP3430_EN_GPIO5_SHIFT, 1033 .module_offs = OMAP3430_PER_MOD, 1034 .idlest_reg_id = 1, 1035 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT, 1036 }, 1037 }, 1038 .class = &omap3xxx_gpio_hwmod_class, 1039 .dev_attr = &gpio_dev_attr, 1040 }; 1041 1042 /* gpio6 */ 1043 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = { 1044 { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */ 1045 { .irq = -1 }, 1046 }; 1047 1048 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { 1049 { .role = "dbclk", .clk = "gpio6_dbck", }, 1050 }; 1051 1052 static struct omap_hwmod omap3xxx_gpio6_hwmod = { 1053 .name = "gpio6", 1054 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1055 .mpu_irqs = omap3xxx_gpio6_irqs, 1056 .main_clk = "gpio6_ick", 1057 .opt_clks = gpio6_opt_clks, 1058 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), 1059 .prcm = { 1060 .omap2 = { 1061 .prcm_reg_id = 1, 1062 .module_bit = OMAP3430_EN_GPIO6_SHIFT, 1063 .module_offs = OMAP3430_PER_MOD, 1064 .idlest_reg_id = 1, 1065 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT, 1066 }, 1067 }, 1068 .class = &omap3xxx_gpio_hwmod_class, 1069 .dev_attr = &gpio_dev_attr, 1070 }; 1071 1072 /* dma attributes */ 1073 static struct omap_dma_dev_attr dma_dev_attr = { 1074 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | 1075 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, 1076 .lch_count = 32, 1077 }; 1078 1079 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = { 1080 .rev_offs = 0x0000, 1081 .sysc_offs = 0x002c, 1082 .syss_offs = 0x0028, 1083 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 1084 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | 1085 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | 1086 SYSS_HAS_RESET_STATUS), 1087 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 1088 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 1089 .sysc_fields = &omap_hwmod_sysc_type1, 1090 }; 1091 1092 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = { 1093 .name = "dma", 1094 .sysc = &omap3xxx_dma_sysc, 1095 }; 1096 1097 /* dma_system */ 1098 static struct omap_hwmod omap3xxx_dma_system_hwmod = { 1099 .name = "dma", 1100 .class = &omap3xxx_dma_hwmod_class, 1101 .mpu_irqs = omap2_dma_system_irqs, 1102 .main_clk = "core_l3_ick", 1103 .prcm = { 1104 .omap2 = { 1105 .module_offs = CORE_MOD, 1106 .prcm_reg_id = 1, 1107 .module_bit = OMAP3430_ST_SDMA_SHIFT, 1108 .idlest_reg_id = 1, 1109 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT, 1110 }, 1111 }, 1112 .dev_attr = &dma_dev_attr, 1113 .flags = HWMOD_NO_IDLEST, 1114 }; 1115 1116 /* 1117 * 'mcbsp' class 1118 * multi channel buffered serial port controller 1119 */ 1120 1121 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = { 1122 .sysc_offs = 0x008c, 1123 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | 1124 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), 1125 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1126 .sysc_fields = &omap_hwmod_sysc_type1, 1127 .clockact = 0x2, 1128 }; 1129 1130 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = { 1131 .name = "mcbsp", 1132 .sysc = &omap3xxx_mcbsp_sysc, 1133 .rev = MCBSP_CONFIG_TYPE3, 1134 }; 1135 1136 /* McBSP functional clock mapping */ 1137 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = { 1138 { .role = "pad_fck", .clk = "mcbsp_clks" }, 1139 { .role = "prcm_fck", .clk = "core_96m_fck" }, 1140 }; 1141 1142 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = { 1143 { .role = "pad_fck", .clk = "mcbsp_clks" }, 1144 { .role = "prcm_fck", .clk = "per_96m_fck" }, 1145 }; 1146 1147 /* mcbsp1 */ 1148 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { 1149 { .name = "common", .irq = 16 + OMAP_INTC_START, }, 1150 { .name = "tx", .irq = 59 + OMAP_INTC_START, }, 1151 { .name = "rx", .irq = 60 + OMAP_INTC_START, }, 1152 { .irq = -1 }, 1153 }; 1154 1155 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { 1156 .name = "mcbsp1", 1157 .class = &omap3xxx_mcbsp_hwmod_class, 1158 .mpu_irqs = omap3xxx_mcbsp1_irqs, 1159 .sdma_reqs = omap2_mcbsp1_sdma_reqs, 1160 .main_clk = "mcbsp1_fck", 1161 .prcm = { 1162 .omap2 = { 1163 .prcm_reg_id = 1, 1164 .module_bit = OMAP3430_EN_MCBSP1_SHIFT, 1165 .module_offs = CORE_MOD, 1166 .idlest_reg_id = 1, 1167 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, 1168 }, 1169 }, 1170 .opt_clks = mcbsp15_opt_clks, 1171 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks), 1172 }; 1173 1174 /* mcbsp2 */ 1175 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = { 1176 { .name = "common", .irq = 17 + OMAP_INTC_START, }, 1177 { .name = "tx", .irq = 62 + OMAP_INTC_START, }, 1178 { .name = "rx", .irq = 63 + OMAP_INTC_START, }, 1179 { .irq = -1 }, 1180 }; 1181 1182 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { 1183 .sidetone = "mcbsp2_sidetone", 1184 }; 1185 1186 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { 1187 .name = "mcbsp2", 1188 .class = &omap3xxx_mcbsp_hwmod_class, 1189 .mpu_irqs = omap3xxx_mcbsp2_irqs, 1190 .sdma_reqs = omap2_mcbsp2_sdma_reqs, 1191 .main_clk = "mcbsp2_fck", 1192 .prcm = { 1193 .omap2 = { 1194 .prcm_reg_id = 1, 1195 .module_bit = OMAP3430_EN_MCBSP2_SHIFT, 1196 .module_offs = OMAP3430_PER_MOD, 1197 .idlest_reg_id = 1, 1198 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, 1199 }, 1200 }, 1201 .opt_clks = mcbsp234_opt_clks, 1202 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), 1203 .dev_attr = &omap34xx_mcbsp2_dev_attr, 1204 }; 1205 1206 /* mcbsp3 */ 1207 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = { 1208 { .name = "common", .irq = 22 + OMAP_INTC_START, }, 1209 { .name = "tx", .irq = 89 + OMAP_INTC_START, }, 1210 { .name = "rx", .irq = 90 + OMAP_INTC_START, }, 1211 { .irq = -1 }, 1212 }; 1213 1214 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { 1215 .sidetone = "mcbsp3_sidetone", 1216 }; 1217 1218 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { 1219 .name = "mcbsp3", 1220 .class = &omap3xxx_mcbsp_hwmod_class, 1221 .mpu_irqs = omap3xxx_mcbsp3_irqs, 1222 .sdma_reqs = omap2_mcbsp3_sdma_reqs, 1223 .main_clk = "mcbsp3_fck", 1224 .prcm = { 1225 .omap2 = { 1226 .prcm_reg_id = 1, 1227 .module_bit = OMAP3430_EN_MCBSP3_SHIFT, 1228 .module_offs = OMAP3430_PER_MOD, 1229 .idlest_reg_id = 1, 1230 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, 1231 }, 1232 }, 1233 .opt_clks = mcbsp234_opt_clks, 1234 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), 1235 .dev_attr = &omap34xx_mcbsp3_dev_attr, 1236 }; 1237 1238 /* mcbsp4 */ 1239 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = { 1240 { .name = "common", .irq = 23 + OMAP_INTC_START, }, 1241 { .name = "tx", .irq = 54 + OMAP_INTC_START, }, 1242 { .name = "rx", .irq = 55 + OMAP_INTC_START, }, 1243 { .irq = -1 }, 1244 }; 1245 1246 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = { 1247 { .name = "rx", .dma_req = 20 }, 1248 { .name = "tx", .dma_req = 19 }, 1249 { .dma_req = -1 } 1250 }; 1251 1252 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { 1253 .name = "mcbsp4", 1254 .class = &omap3xxx_mcbsp_hwmod_class, 1255 .mpu_irqs = omap3xxx_mcbsp4_irqs, 1256 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs, 1257 .main_clk = "mcbsp4_fck", 1258 .prcm = { 1259 .omap2 = { 1260 .prcm_reg_id = 1, 1261 .module_bit = OMAP3430_EN_MCBSP4_SHIFT, 1262 .module_offs = OMAP3430_PER_MOD, 1263 .idlest_reg_id = 1, 1264 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, 1265 }, 1266 }, 1267 .opt_clks = mcbsp234_opt_clks, 1268 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), 1269 }; 1270 1271 /* mcbsp5 */ 1272 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = { 1273 { .name = "common", .irq = 27 + OMAP_INTC_START, }, 1274 { .name = "tx", .irq = 81 + OMAP_INTC_START, }, 1275 { .name = "rx", .irq = 82 + OMAP_INTC_START, }, 1276 { .irq = -1 }, 1277 }; 1278 1279 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = { 1280 { .name = "rx", .dma_req = 22 }, 1281 { .name = "tx", .dma_req = 21 }, 1282 { .dma_req = -1 } 1283 }; 1284 1285 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { 1286 .name = "mcbsp5", 1287 .class = &omap3xxx_mcbsp_hwmod_class, 1288 .mpu_irqs = omap3xxx_mcbsp5_irqs, 1289 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs, 1290 .main_clk = "mcbsp5_fck", 1291 .prcm = { 1292 .omap2 = { 1293 .prcm_reg_id = 1, 1294 .module_bit = OMAP3430_EN_MCBSP5_SHIFT, 1295 .module_offs = CORE_MOD, 1296 .idlest_reg_id = 1, 1297 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, 1298 }, 1299 }, 1300 .opt_clks = mcbsp15_opt_clks, 1301 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks), 1302 }; 1303 1304 /* 'mcbsp sidetone' class */ 1305 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = { 1306 .sysc_offs = 0x0010, 1307 .sysc_flags = SYSC_HAS_AUTOIDLE, 1308 .sysc_fields = &omap_hwmod_sysc_type1, 1309 }; 1310 1311 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = { 1312 .name = "mcbsp_sidetone", 1313 .sysc = &omap3xxx_mcbsp_sidetone_sysc, 1314 }; 1315 1316 /* mcbsp2_sidetone */ 1317 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = { 1318 { .name = "irq", .irq = 4 + OMAP_INTC_START, }, 1319 { .irq = -1 }, 1320 }; 1321 1322 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { 1323 .name = "mcbsp2_sidetone", 1324 .class = &omap3xxx_mcbsp_sidetone_hwmod_class, 1325 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs, 1326 .main_clk = "mcbsp2_fck", 1327 .prcm = { 1328 .omap2 = { 1329 .prcm_reg_id = 1, 1330 .module_bit = OMAP3430_EN_MCBSP2_SHIFT, 1331 .module_offs = OMAP3430_PER_MOD, 1332 .idlest_reg_id = 1, 1333 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, 1334 }, 1335 }, 1336 }; 1337 1338 /* mcbsp3_sidetone */ 1339 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = { 1340 { .name = "irq", .irq = 5 + OMAP_INTC_START, }, 1341 { .irq = -1 }, 1342 }; 1343 1344 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { 1345 .name = "mcbsp3_sidetone", 1346 .class = &omap3xxx_mcbsp_sidetone_hwmod_class, 1347 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs, 1348 .main_clk = "mcbsp3_fck", 1349 .prcm = { 1350 .omap2 = { 1351 .prcm_reg_id = 1, 1352 .module_bit = OMAP3430_EN_MCBSP3_SHIFT, 1353 .module_offs = OMAP3430_PER_MOD, 1354 .idlest_reg_id = 1, 1355 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, 1356 }, 1357 }, 1358 }; 1359 1360 /* SR common */ 1361 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { 1362 .clkact_shift = 20, 1363 }; 1364 1365 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = { 1366 .sysc_offs = 0x24, 1367 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE), 1368 .clockact = CLOCKACT_TEST_ICLK, 1369 .sysc_fields = &omap34xx_sr_sysc_fields, 1370 }; 1371 1372 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = { 1373 .name = "smartreflex", 1374 .sysc = &omap34xx_sr_sysc, 1375 .rev = 1, 1376 }; 1377 1378 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = { 1379 .sidle_shift = 24, 1380 .enwkup_shift = 26, 1381 }; 1382 1383 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = { 1384 .sysc_offs = 0x38, 1385 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1386 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | 1387 SYSC_NO_CACHE), 1388 .sysc_fields = &omap36xx_sr_sysc_fields, 1389 }; 1390 1391 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = { 1392 .name = "smartreflex", 1393 .sysc = &omap36xx_sr_sysc, 1394 .rev = 2, 1395 }; 1396 1397 /* SR1 */ 1398 static struct omap_smartreflex_dev_attr sr1_dev_attr = { 1399 .sensor_voltdm_name = "mpu_iva", 1400 }; 1401 1402 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = { 1403 { .irq = 18 + OMAP_INTC_START, }, 1404 { .irq = -1 }, 1405 }; 1406 1407 static struct omap_hwmod omap34xx_sr1_hwmod = { 1408 .name = "smartreflex_mpu_iva", 1409 .class = &omap34xx_smartreflex_hwmod_class, 1410 .main_clk = "sr1_fck", 1411 .prcm = { 1412 .omap2 = { 1413 .prcm_reg_id = 1, 1414 .module_bit = OMAP3430_EN_SR1_SHIFT, 1415 .module_offs = WKUP_MOD, 1416 .idlest_reg_id = 1, 1417 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, 1418 }, 1419 }, 1420 .dev_attr = &sr1_dev_attr, 1421 .mpu_irqs = omap3_smartreflex_mpu_irqs, 1422 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 1423 }; 1424 1425 static struct omap_hwmod omap36xx_sr1_hwmod = { 1426 .name = "smartreflex_mpu_iva", 1427 .class = &omap36xx_smartreflex_hwmod_class, 1428 .main_clk = "sr1_fck", 1429 .prcm = { 1430 .omap2 = { 1431 .prcm_reg_id = 1, 1432 .module_bit = OMAP3430_EN_SR1_SHIFT, 1433 .module_offs = WKUP_MOD, 1434 .idlest_reg_id = 1, 1435 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, 1436 }, 1437 }, 1438 .dev_attr = &sr1_dev_attr, 1439 .mpu_irqs = omap3_smartreflex_mpu_irqs, 1440 }; 1441 1442 /* SR2 */ 1443 static struct omap_smartreflex_dev_attr sr2_dev_attr = { 1444 .sensor_voltdm_name = "core", 1445 }; 1446 1447 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = { 1448 { .irq = 19 + OMAP_INTC_START, }, 1449 { .irq = -1 }, 1450 }; 1451 1452 static struct omap_hwmod omap34xx_sr2_hwmod = { 1453 .name = "smartreflex_core", 1454 .class = &omap34xx_smartreflex_hwmod_class, 1455 .main_clk = "sr2_fck", 1456 .prcm = { 1457 .omap2 = { 1458 .prcm_reg_id = 1, 1459 .module_bit = OMAP3430_EN_SR2_SHIFT, 1460 .module_offs = WKUP_MOD, 1461 .idlest_reg_id = 1, 1462 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, 1463 }, 1464 }, 1465 .dev_attr = &sr2_dev_attr, 1466 .mpu_irqs = omap3_smartreflex_core_irqs, 1467 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 1468 }; 1469 1470 static struct omap_hwmod omap36xx_sr2_hwmod = { 1471 .name = "smartreflex_core", 1472 .class = &omap36xx_smartreflex_hwmod_class, 1473 .main_clk = "sr2_fck", 1474 .prcm = { 1475 .omap2 = { 1476 .prcm_reg_id = 1, 1477 .module_bit = OMAP3430_EN_SR2_SHIFT, 1478 .module_offs = WKUP_MOD, 1479 .idlest_reg_id = 1, 1480 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, 1481 }, 1482 }, 1483 .dev_attr = &sr2_dev_attr, 1484 .mpu_irqs = omap3_smartreflex_core_irqs, 1485 }; 1486 1487 /* 1488 * 'mailbox' class 1489 * mailbox module allowing communication between the on-chip processors 1490 * using a queued mailbox-interrupt mechanism. 1491 */ 1492 1493 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = { 1494 .rev_offs = 0x000, 1495 .sysc_offs = 0x010, 1496 .syss_offs = 0x014, 1497 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1498 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), 1499 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1500 .sysc_fields = &omap_hwmod_sysc_type1, 1501 }; 1502 1503 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = { 1504 .name = "mailbox", 1505 .sysc = &omap3xxx_mailbox_sysc, 1506 }; 1507 1508 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { 1509 { .irq = 26 + OMAP_INTC_START, }, 1510 { .irq = -1 }, 1511 }; 1512 1513 static struct omap_hwmod omap3xxx_mailbox_hwmod = { 1514 .name = "mailbox", 1515 .class = &omap3xxx_mailbox_hwmod_class, 1516 .mpu_irqs = omap3xxx_mailbox_irqs, 1517 .main_clk = "mailboxes_ick", 1518 .prcm = { 1519 .omap2 = { 1520 .prcm_reg_id = 1, 1521 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT, 1522 .module_offs = CORE_MOD, 1523 .idlest_reg_id = 1, 1524 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT, 1525 }, 1526 }, 1527 }; 1528 1529 /* 1530 * 'mcspi' class 1531 * multichannel serial port interface (mcspi) / master/slave synchronous serial 1532 * bus 1533 */ 1534 1535 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = { 1536 .rev_offs = 0x0000, 1537 .sysc_offs = 0x0010, 1538 .syss_offs = 0x0014, 1539 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1540 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 1541 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 1542 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1543 .sysc_fields = &omap_hwmod_sysc_type1, 1544 }; 1545 1546 static struct omap_hwmod_class omap34xx_mcspi_class = { 1547 .name = "mcspi", 1548 .sysc = &omap34xx_mcspi_sysc, 1549 .rev = OMAP3_MCSPI_REV, 1550 }; 1551 1552 /* mcspi1 */ 1553 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { 1554 .num_chipselect = 4, 1555 }; 1556 1557 static struct omap_hwmod omap34xx_mcspi1 = { 1558 .name = "mcspi1", 1559 .mpu_irqs = omap2_mcspi1_mpu_irqs, 1560 .sdma_reqs = omap2_mcspi1_sdma_reqs, 1561 .main_clk = "mcspi1_fck", 1562 .prcm = { 1563 .omap2 = { 1564 .module_offs = CORE_MOD, 1565 .prcm_reg_id = 1, 1566 .module_bit = OMAP3430_EN_MCSPI1_SHIFT, 1567 .idlest_reg_id = 1, 1568 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT, 1569 }, 1570 }, 1571 .class = &omap34xx_mcspi_class, 1572 .dev_attr = &omap_mcspi1_dev_attr, 1573 }; 1574 1575 /* mcspi2 */ 1576 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { 1577 .num_chipselect = 2, 1578 }; 1579 1580 static struct omap_hwmod omap34xx_mcspi2 = { 1581 .name = "mcspi2", 1582 .mpu_irqs = omap2_mcspi2_mpu_irqs, 1583 .sdma_reqs = omap2_mcspi2_sdma_reqs, 1584 .main_clk = "mcspi2_fck", 1585 .prcm = { 1586 .omap2 = { 1587 .module_offs = CORE_MOD, 1588 .prcm_reg_id = 1, 1589 .module_bit = OMAP3430_EN_MCSPI2_SHIFT, 1590 .idlest_reg_id = 1, 1591 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT, 1592 }, 1593 }, 1594 .class = &omap34xx_mcspi_class, 1595 .dev_attr = &omap_mcspi2_dev_attr, 1596 }; 1597 1598 /* mcspi3 */ 1599 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = { 1600 { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */ 1601 { .irq = -1 }, 1602 }; 1603 1604 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = { 1605 { .name = "tx0", .dma_req = 15 }, 1606 { .name = "rx0", .dma_req = 16 }, 1607 { .name = "tx1", .dma_req = 23 }, 1608 { .name = "rx1", .dma_req = 24 }, 1609 { .dma_req = -1 } 1610 }; 1611 1612 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { 1613 .num_chipselect = 2, 1614 }; 1615 1616 static struct omap_hwmod omap34xx_mcspi3 = { 1617 .name = "mcspi3", 1618 .mpu_irqs = omap34xx_mcspi3_mpu_irqs, 1619 .sdma_reqs = omap34xx_mcspi3_sdma_reqs, 1620 .main_clk = "mcspi3_fck", 1621 .prcm = { 1622 .omap2 = { 1623 .module_offs = CORE_MOD, 1624 .prcm_reg_id = 1, 1625 .module_bit = OMAP3430_EN_MCSPI3_SHIFT, 1626 .idlest_reg_id = 1, 1627 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT, 1628 }, 1629 }, 1630 .class = &omap34xx_mcspi_class, 1631 .dev_attr = &omap_mcspi3_dev_attr, 1632 }; 1633 1634 /* mcspi4 */ 1635 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { 1636 { .name = "irq", .irq = 48 + OMAP_INTC_START, }, 1637 { .irq = -1 }, 1638 }; 1639 1640 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = { 1641 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */ 1642 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */ 1643 { .dma_req = -1 } 1644 }; 1645 1646 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { 1647 .num_chipselect = 1, 1648 }; 1649 1650 static struct omap_hwmod omap34xx_mcspi4 = { 1651 .name = "mcspi4", 1652 .mpu_irqs = omap34xx_mcspi4_mpu_irqs, 1653 .sdma_reqs = omap34xx_mcspi4_sdma_reqs, 1654 .main_clk = "mcspi4_fck", 1655 .prcm = { 1656 .omap2 = { 1657 .module_offs = CORE_MOD, 1658 .prcm_reg_id = 1, 1659 .module_bit = OMAP3430_EN_MCSPI4_SHIFT, 1660 .idlest_reg_id = 1, 1661 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT, 1662 }, 1663 }, 1664 .class = &omap34xx_mcspi_class, 1665 .dev_attr = &omap_mcspi4_dev_attr, 1666 }; 1667 1668 /* usbhsotg */ 1669 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = { 1670 .rev_offs = 0x0400, 1671 .sysc_offs = 0x0404, 1672 .syss_offs = 0x0408, 1673 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| 1674 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 1675 SYSC_HAS_AUTOIDLE), 1676 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 1677 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 1678 .sysc_fields = &omap_hwmod_sysc_type1, 1679 }; 1680 1681 static struct omap_hwmod_class usbotg_class = { 1682 .name = "usbotg", 1683 .sysc = &omap3xxx_usbhsotg_sysc, 1684 }; 1685 1686 /* usb_otg_hs */ 1687 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = { 1688 1689 { .name = "mc", .irq = 92 + OMAP_INTC_START, }, 1690 { .name = "dma", .irq = 93 + OMAP_INTC_START, }, 1691 { .irq = -1 }, 1692 }; 1693 1694 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { 1695 .name = "usb_otg_hs", 1696 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs, 1697 .main_clk = "hsotgusb_ick", 1698 .prcm = { 1699 .omap2 = { 1700 .prcm_reg_id = 1, 1701 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT, 1702 .module_offs = CORE_MOD, 1703 .idlest_reg_id = 1, 1704 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT, 1705 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT 1706 }, 1707 }, 1708 .class = &usbotg_class, 1709 1710 /* 1711 * Erratum ID: i479 idle_req / idle_ack mechanism potentially 1712 * broken when autoidle is enabled 1713 * workaround is to disable the autoidle bit at module level. 1714 * 1715 * Enabling the device in any other MIDLEMODE setting but force-idle 1716 * causes core_pwrdm not enter idle states at least on OMAP3630. 1717 * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY 1718 * signal when MIDLEMODE is set to force-idle. 1719 */ 1720 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE 1721 | HWMOD_FORCE_MSTANDBY, 1722 }; 1723 1724 /* usb_otg_hs */ 1725 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { 1726 { .name = "mc", .irq = 71 + OMAP_INTC_START, }, 1727 { .irq = -1 }, 1728 }; 1729 1730 static struct omap_hwmod_class am35xx_usbotg_class = { 1731 .name = "am35xx_usbotg", 1732 }; 1733 1734 static struct omap_hwmod am35xx_usbhsotg_hwmod = { 1735 .name = "am35x_otg_hs", 1736 .mpu_irqs = am35xx_usbhsotg_mpu_irqs, 1737 .main_clk = "hsotgusb_fck", 1738 .class = &am35xx_usbotg_class, 1739 .flags = HWMOD_NO_IDLEST, 1740 }; 1741 1742 /* MMC/SD/SDIO common */ 1743 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = { 1744 .rev_offs = 0x1fc, 1745 .sysc_offs = 0x10, 1746 .syss_offs = 0x14, 1747 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1748 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 1749 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 1750 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1751 .sysc_fields = &omap_hwmod_sysc_type1, 1752 }; 1753 1754 static struct omap_hwmod_class omap34xx_mmc_class = { 1755 .name = "mmc", 1756 .sysc = &omap34xx_mmc_sysc, 1757 }; 1758 1759 /* MMC/SD/SDIO1 */ 1760 1761 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = { 1762 { .irq = 83 + OMAP_INTC_START, }, 1763 { .irq = -1 }, 1764 }; 1765 1766 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = { 1767 { .name = "tx", .dma_req = 61, }, 1768 { .name = "rx", .dma_req = 62, }, 1769 { .dma_req = -1 } 1770 }; 1771 1772 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = { 1773 { .role = "dbck", .clk = "omap_32k_fck", }, 1774 }; 1775 1776 static struct omap_mmc_dev_attr mmc1_dev_attr = { 1777 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, 1778 }; 1779 1780 /* See 35xx errata 2.1.1.128 in SPRZ278F */ 1781 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = { 1782 .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT | 1783 OMAP_HSMMC_BROKEN_MULTIBLOCK_READ), 1784 }; 1785 1786 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = { 1787 .name = "mmc1", 1788 .mpu_irqs = omap34xx_mmc1_mpu_irqs, 1789 .sdma_reqs = omap34xx_mmc1_sdma_reqs, 1790 .opt_clks = omap34xx_mmc1_opt_clks, 1791 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), 1792 .main_clk = "mmchs1_fck", 1793 .prcm = { 1794 .omap2 = { 1795 .module_offs = CORE_MOD, 1796 .prcm_reg_id = 1, 1797 .module_bit = OMAP3430_EN_MMC1_SHIFT, 1798 .idlest_reg_id = 1, 1799 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, 1800 }, 1801 }, 1802 .dev_attr = &mmc1_pre_es3_dev_attr, 1803 .class = &omap34xx_mmc_class, 1804 }; 1805 1806 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = { 1807 .name = "mmc1", 1808 .mpu_irqs = omap34xx_mmc1_mpu_irqs, 1809 .sdma_reqs = omap34xx_mmc1_sdma_reqs, 1810 .opt_clks = omap34xx_mmc1_opt_clks, 1811 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), 1812 .main_clk = "mmchs1_fck", 1813 .prcm = { 1814 .omap2 = { 1815 .module_offs = CORE_MOD, 1816 .prcm_reg_id = 1, 1817 .module_bit = OMAP3430_EN_MMC1_SHIFT, 1818 .idlest_reg_id = 1, 1819 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, 1820 }, 1821 }, 1822 .dev_attr = &mmc1_dev_attr, 1823 .class = &omap34xx_mmc_class, 1824 }; 1825 1826 /* MMC/SD/SDIO2 */ 1827 1828 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = { 1829 { .irq = 86 + OMAP_INTC_START, }, 1830 { .irq = -1 }, 1831 }; 1832 1833 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = { 1834 { .name = "tx", .dma_req = 47, }, 1835 { .name = "rx", .dma_req = 48, }, 1836 { .dma_req = -1 } 1837 }; 1838 1839 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = { 1840 { .role = "dbck", .clk = "omap_32k_fck", }, 1841 }; 1842 1843 /* See 35xx errata 2.1.1.128 in SPRZ278F */ 1844 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = { 1845 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, 1846 }; 1847 1848 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = { 1849 .name = "mmc2", 1850 .mpu_irqs = omap34xx_mmc2_mpu_irqs, 1851 .sdma_reqs = omap34xx_mmc2_sdma_reqs, 1852 .opt_clks = omap34xx_mmc2_opt_clks, 1853 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), 1854 .main_clk = "mmchs2_fck", 1855 .prcm = { 1856 .omap2 = { 1857 .module_offs = CORE_MOD, 1858 .prcm_reg_id = 1, 1859 .module_bit = OMAP3430_EN_MMC2_SHIFT, 1860 .idlest_reg_id = 1, 1861 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, 1862 }, 1863 }, 1864 .dev_attr = &mmc2_pre_es3_dev_attr, 1865 .class = &omap34xx_mmc_class, 1866 }; 1867 1868 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = { 1869 .name = "mmc2", 1870 .mpu_irqs = omap34xx_mmc2_mpu_irqs, 1871 .sdma_reqs = omap34xx_mmc2_sdma_reqs, 1872 .opt_clks = omap34xx_mmc2_opt_clks, 1873 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), 1874 .main_clk = "mmchs2_fck", 1875 .prcm = { 1876 .omap2 = { 1877 .module_offs = CORE_MOD, 1878 .prcm_reg_id = 1, 1879 .module_bit = OMAP3430_EN_MMC2_SHIFT, 1880 .idlest_reg_id = 1, 1881 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, 1882 }, 1883 }, 1884 .class = &omap34xx_mmc_class, 1885 }; 1886 1887 /* MMC/SD/SDIO3 */ 1888 1889 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = { 1890 { .irq = 94 + OMAP_INTC_START, }, 1891 { .irq = -1 }, 1892 }; 1893 1894 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = { 1895 { .name = "tx", .dma_req = 77, }, 1896 { .name = "rx", .dma_req = 78, }, 1897 { .dma_req = -1 } 1898 }; 1899 1900 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = { 1901 { .role = "dbck", .clk = "omap_32k_fck", }, 1902 }; 1903 1904 static struct omap_hwmod omap3xxx_mmc3_hwmod = { 1905 .name = "mmc3", 1906 .mpu_irqs = omap34xx_mmc3_mpu_irqs, 1907 .sdma_reqs = omap34xx_mmc3_sdma_reqs, 1908 .opt_clks = omap34xx_mmc3_opt_clks, 1909 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks), 1910 .main_clk = "mmchs3_fck", 1911 .prcm = { 1912 .omap2 = { 1913 .prcm_reg_id = 1, 1914 .module_bit = OMAP3430_EN_MMC3_SHIFT, 1915 .idlest_reg_id = 1, 1916 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT, 1917 }, 1918 }, 1919 .class = &omap34xx_mmc_class, 1920 }; 1921 1922 /* 1923 * 'usb_host_hs' class 1924 * high-speed multi-port usb host controller 1925 */ 1926 1927 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = { 1928 .rev_offs = 0x0000, 1929 .sysc_offs = 0x0010, 1930 .syss_offs = 0x0014, 1931 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | 1932 SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | 1933 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), 1934 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 1935 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 1936 .sysc_fields = &omap_hwmod_sysc_type1, 1937 }; 1938 1939 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = { 1940 .name = "usb_host_hs", 1941 .sysc = &omap3xxx_usb_host_hs_sysc, 1942 }; 1943 1944 static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = { 1945 { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", }, 1946 }; 1947 1948 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = { 1949 { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, }, 1950 { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, }, 1951 { .irq = -1 }, 1952 }; 1953 1954 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = { 1955 .name = "usb_host_hs", 1956 .class = &omap3xxx_usb_host_hs_hwmod_class, 1957 .clkdm_name = "l3_init_clkdm", 1958 .mpu_irqs = omap3xxx_usb_host_hs_irqs, 1959 .main_clk = "usbhost_48m_fck", 1960 .prcm = { 1961 .omap2 = { 1962 .module_offs = OMAP3430ES2_USBHOST_MOD, 1963 .prcm_reg_id = 1, 1964 .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, 1965 .idlest_reg_id = 1, 1966 .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT, 1967 .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT, 1968 }, 1969 }, 1970 .opt_clks = omap3xxx_usb_host_hs_opt_clks, 1971 .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks), 1972 1973 /* 1974 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock 1975 * id: i660 1976 * 1977 * Description: 1978 * In the following configuration : 1979 * - USBHOST module is set to smart-idle mode 1980 * - PRCM asserts idle_req to the USBHOST module ( This typically 1981 * happens when the system is going to a low power mode : all ports 1982 * have been suspended, the master part of the USBHOST module has 1983 * entered the standby state, and SW has cut the functional clocks) 1984 * - an USBHOST interrupt occurs before the module is able to answer 1985 * idle_ack, typically a remote wakeup IRQ. 1986 * Then the USB HOST module will enter a deadlock situation where it 1987 * is no more accessible nor functional. 1988 * 1989 * Workaround: 1990 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE 1991 */ 1992 1993 /* 1994 * Errata: USB host EHCI may stall when entering smart-standby mode 1995 * Id: i571 1996 * 1997 * Description: 1998 * When the USBHOST module is set to smart-standby mode, and when it is 1999 * ready to enter the standby state (i.e. all ports are suspended and 2000 * all attached devices are in suspend mode), then it can wrongly assert 2001 * the Mstandby signal too early while there are still some residual OCP 2002 * transactions ongoing. If this condition occurs, the internal state 2003 * machine may go to an undefined state and the USB link may be stuck 2004 * upon the next resume. 2005 * 2006 * Workaround: 2007 * Don't use smart standby; use only force standby, 2008 * hence HWMOD_SWSUP_MSTANDBY 2009 */ 2010 2011 /* 2012 * During system boot; If the hwmod framework resets the module 2013 * the module will have smart idle settings; which can lead to deadlock 2014 * (above Errata Id:i660); so, dont reset the module during boot; 2015 * Use HWMOD_INIT_NO_RESET. 2016 */ 2017 2018 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | 2019 HWMOD_INIT_NO_RESET, 2020 }; 2021 2022 /* 2023 * 'usb_tll_hs' class 2024 * usb_tll_hs module is the adapter on the usb_host_hs ports 2025 */ 2026 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = { 2027 .rev_offs = 0x0000, 2028 .sysc_offs = 0x0010, 2029 .syss_offs = 0x0014, 2030 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 2031 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 2032 SYSC_HAS_AUTOIDLE), 2033 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 2034 .sysc_fields = &omap_hwmod_sysc_type1, 2035 }; 2036 2037 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = { 2038 .name = "usb_tll_hs", 2039 .sysc = &omap3xxx_usb_tll_hs_sysc, 2040 }; 2041 2042 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = { 2043 { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, }, 2044 { .irq = -1 }, 2045 }; 2046 2047 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { 2048 .name = "usb_tll_hs", 2049 .class = &omap3xxx_usb_tll_hs_hwmod_class, 2050 .clkdm_name = "l3_init_clkdm", 2051 .mpu_irqs = omap3xxx_usb_tll_hs_irqs, 2052 .main_clk = "usbtll_fck", 2053 .prcm = { 2054 .omap2 = { 2055 .module_offs = CORE_MOD, 2056 .prcm_reg_id = 3, 2057 .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT, 2058 .idlest_reg_id = 3, 2059 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT, 2060 }, 2061 }, 2062 }; 2063 2064 static struct omap_hwmod omap3xxx_hdq1w_hwmod = { 2065 .name = "hdq1w", 2066 .mpu_irqs = omap2_hdq1w_mpu_irqs, 2067 .main_clk = "hdq_fck", 2068 .prcm = { 2069 .omap2 = { 2070 .module_offs = CORE_MOD, 2071 .prcm_reg_id = 1, 2072 .module_bit = OMAP3430_EN_HDQ_SHIFT, 2073 .idlest_reg_id = 1, 2074 .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT, 2075 }, 2076 }, 2077 .class = &omap2_hdq1w_class, 2078 }; 2079 2080 /* SAD2D */ 2081 static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = { 2082 { .name = "rst_modem_pwron_sw", .rst_shift = 0 }, 2083 { .name = "rst_modem_sw", .rst_shift = 1 }, 2084 }; 2085 2086 static struct omap_hwmod_class omap3xxx_sad2d_class = { 2087 .name = "sad2d", 2088 }; 2089 2090 static struct omap_hwmod omap3xxx_sad2d_hwmod = { 2091 .name = "sad2d", 2092 .rst_lines = omap3xxx_sad2d_resets, 2093 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_sad2d_resets), 2094 .main_clk = "sad2d_ick", 2095 .prcm = { 2096 .omap2 = { 2097 .module_offs = CORE_MOD, 2098 .prcm_reg_id = 1, 2099 .module_bit = OMAP3430_EN_SAD2D_SHIFT, 2100 .idlest_reg_id = 1, 2101 .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT, 2102 }, 2103 }, 2104 .class = &omap3xxx_sad2d_class, 2105 }; 2106 2107 /* 2108 * '32K sync counter' class 2109 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock 2110 */ 2111 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = { 2112 .rev_offs = 0x0000, 2113 .sysc_offs = 0x0004, 2114 .sysc_flags = SYSC_HAS_SIDLEMODE, 2115 .idlemodes = (SIDLE_FORCE | SIDLE_NO), 2116 .sysc_fields = &omap_hwmod_sysc_type1, 2117 }; 2118 2119 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = { 2120 .name = "counter", 2121 .sysc = &omap3xxx_counter_sysc, 2122 }; 2123 2124 static struct omap_hwmod omap3xxx_counter_32k_hwmod = { 2125 .name = "counter_32k", 2126 .class = &omap3xxx_counter_hwmod_class, 2127 .clkdm_name = "wkup_clkdm", 2128 .flags = HWMOD_SWSUP_SIDLE, 2129 .main_clk = "wkup_32k_fck", 2130 .prcm = { 2131 .omap2 = { 2132 .module_offs = WKUP_MOD, 2133 .prcm_reg_id = 1, 2134 .module_bit = OMAP3430_ST_32KSYNC_SHIFT, 2135 .idlest_reg_id = 1, 2136 .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT, 2137 }, 2138 }, 2139 }; 2140 2141 /* 2142 * 'gpmc' class 2143 * general purpose memory controller 2144 */ 2145 2146 static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = { 2147 .rev_offs = 0x0000, 2148 .sysc_offs = 0x0010, 2149 .syss_offs = 0x0014, 2150 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | 2151 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 2152 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 2153 .sysc_fields = &omap_hwmod_sysc_type1, 2154 }; 2155 2156 static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = { 2157 .name = "gpmc", 2158 .sysc = &omap3xxx_gpmc_sysc, 2159 }; 2160 2161 static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = { 2162 { .irq = 20 }, 2163 { .irq = -1 } 2164 }; 2165 2166 static struct omap_hwmod omap3xxx_gpmc_hwmod = { 2167 .name = "gpmc", 2168 .class = &omap3xxx_gpmc_hwmod_class, 2169 .clkdm_name = "core_l3_clkdm", 2170 .mpu_irqs = omap3xxx_gpmc_irqs, 2171 .main_clk = "gpmc_fck", 2172 /* 2173 * XXX HWMOD_INIT_NO_RESET should not be needed for this IP 2174 * block. It is not being added due to any known bugs with 2175 * resetting the GPMC IP block, but rather because any timings 2176 * set by the bootloader are not being correctly programmed by 2177 * the kernel from the board file or DT data. 2178 * HWMOD_INIT_NO_RESET should be removed ASAP. 2179 */ 2180 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET | 2181 HWMOD_NO_IDLEST), 2182 }; 2183 2184 /* 2185 * interfaces 2186 */ 2187 2188 /* L3 -> L4_CORE interface */ 2189 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { 2190 .master = &omap3xxx_l3_main_hwmod, 2191 .slave = &omap3xxx_l4_core_hwmod, 2192 .user = OCP_USER_MPU | OCP_USER_SDMA, 2193 }; 2194 2195 /* L3 -> L4_PER interface */ 2196 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { 2197 .master = &omap3xxx_l3_main_hwmod, 2198 .slave = &omap3xxx_l4_per_hwmod, 2199 .user = OCP_USER_MPU | OCP_USER_SDMA, 2200 }; 2201 2202 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = { 2203 { 2204 .pa_start = 0x68000000, 2205 .pa_end = 0x6800ffff, 2206 .flags = ADDR_TYPE_RT, 2207 }, 2208 { } 2209 }; 2210 2211 /* MPU -> L3 interface */ 2212 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { 2213 .master = &omap3xxx_mpu_hwmod, 2214 .slave = &omap3xxx_l3_main_hwmod, 2215 .addr = omap3xxx_l3_main_addrs, 2216 .user = OCP_USER_MPU, 2217 }; 2218 2219 static struct omap_hwmod_addr_space omap3xxx_l4_emu_addrs[] = { 2220 { 2221 .pa_start = 0x54000000, 2222 .pa_end = 0x547fffff, 2223 .flags = ADDR_TYPE_RT, 2224 }, 2225 { } 2226 }; 2227 2228 /* l3 -> debugss */ 2229 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = { 2230 .master = &omap3xxx_l3_main_hwmod, 2231 .slave = &omap3xxx_debugss_hwmod, 2232 .addr = omap3xxx_l4_emu_addrs, 2233 .user = OCP_USER_MPU, 2234 }; 2235 2236 /* DSS -> l3 */ 2237 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = { 2238 .master = &omap3430es1_dss_core_hwmod, 2239 .slave = &omap3xxx_l3_main_hwmod, 2240 .user = OCP_USER_MPU | OCP_USER_SDMA, 2241 }; 2242 2243 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = { 2244 .master = &omap3xxx_dss_core_hwmod, 2245 .slave = &omap3xxx_l3_main_hwmod, 2246 .fw = { 2247 .omap2 = { 2248 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS, 2249 .flags = OMAP_FIREWALL_L3, 2250 } 2251 }, 2252 .user = OCP_USER_MPU | OCP_USER_SDMA, 2253 }; 2254 2255 /* l3_core -> usbhsotg interface */ 2256 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { 2257 .master = &omap3xxx_usbhsotg_hwmod, 2258 .slave = &omap3xxx_l3_main_hwmod, 2259 .clk = "core_l3_ick", 2260 .user = OCP_USER_MPU, 2261 }; 2262 2263 /* l3_core -> am35xx_usbhsotg interface */ 2264 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { 2265 .master = &am35xx_usbhsotg_hwmod, 2266 .slave = &omap3xxx_l3_main_hwmod, 2267 .clk = "hsotgusb_ick", 2268 .user = OCP_USER_MPU, 2269 }; 2270 2271 /* l3_core -> sad2d interface */ 2272 static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = { 2273 .master = &omap3xxx_sad2d_hwmod, 2274 .slave = &omap3xxx_l3_main_hwmod, 2275 .clk = "core_l3_ick", 2276 .user = OCP_USER_MPU, 2277 }; 2278 2279 /* L4_CORE -> L4_WKUP interface */ 2280 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { 2281 .master = &omap3xxx_l4_core_hwmod, 2282 .slave = &omap3xxx_l4_wkup_hwmod, 2283 .user = OCP_USER_MPU | OCP_USER_SDMA, 2284 }; 2285 2286 /* L4 CORE -> MMC1 interface */ 2287 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = { 2288 .master = &omap3xxx_l4_core_hwmod, 2289 .slave = &omap3xxx_pre_es3_mmc1_hwmod, 2290 .clk = "mmchs1_ick", 2291 .addr = omap2430_mmc1_addr_space, 2292 .user = OCP_USER_MPU | OCP_USER_SDMA, 2293 .flags = OMAP_FIREWALL_L4 2294 }; 2295 2296 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = { 2297 .master = &omap3xxx_l4_core_hwmod, 2298 .slave = &omap3xxx_es3plus_mmc1_hwmod, 2299 .clk = "mmchs1_ick", 2300 .addr = omap2430_mmc1_addr_space, 2301 .user = OCP_USER_MPU | OCP_USER_SDMA, 2302 .flags = OMAP_FIREWALL_L4 2303 }; 2304 2305 /* L4 CORE -> MMC2 interface */ 2306 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = { 2307 .master = &omap3xxx_l4_core_hwmod, 2308 .slave = &omap3xxx_pre_es3_mmc2_hwmod, 2309 .clk = "mmchs2_ick", 2310 .addr = omap2430_mmc2_addr_space, 2311 .user = OCP_USER_MPU | OCP_USER_SDMA, 2312 .flags = OMAP_FIREWALL_L4 2313 }; 2314 2315 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = { 2316 .master = &omap3xxx_l4_core_hwmod, 2317 .slave = &omap3xxx_es3plus_mmc2_hwmod, 2318 .clk = "mmchs2_ick", 2319 .addr = omap2430_mmc2_addr_space, 2320 .user = OCP_USER_MPU | OCP_USER_SDMA, 2321 .flags = OMAP_FIREWALL_L4 2322 }; 2323 2324 /* L4 CORE -> MMC3 interface */ 2325 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = { 2326 { 2327 .pa_start = 0x480ad000, 2328 .pa_end = 0x480ad1ff, 2329 .flags = ADDR_TYPE_RT, 2330 }, 2331 { } 2332 }; 2333 2334 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { 2335 .master = &omap3xxx_l4_core_hwmod, 2336 .slave = &omap3xxx_mmc3_hwmod, 2337 .clk = "mmchs3_ick", 2338 .addr = omap3xxx_mmc3_addr_space, 2339 .user = OCP_USER_MPU | OCP_USER_SDMA, 2340 .flags = OMAP_FIREWALL_L4 2341 }; 2342 2343 /* L4 CORE -> UART1 interface */ 2344 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = { 2345 { 2346 .pa_start = OMAP3_UART1_BASE, 2347 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1, 2348 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 2349 }, 2350 { } 2351 }; 2352 2353 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { 2354 .master = &omap3xxx_l4_core_hwmod, 2355 .slave = &omap3xxx_uart1_hwmod, 2356 .clk = "uart1_ick", 2357 .addr = omap3xxx_uart1_addr_space, 2358 .user = OCP_USER_MPU | OCP_USER_SDMA, 2359 }; 2360 2361 /* L4 CORE -> UART2 interface */ 2362 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = { 2363 { 2364 .pa_start = OMAP3_UART2_BASE, 2365 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1, 2366 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 2367 }, 2368 { } 2369 }; 2370 2371 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { 2372 .master = &omap3xxx_l4_core_hwmod, 2373 .slave = &omap3xxx_uart2_hwmod, 2374 .clk = "uart2_ick", 2375 .addr = omap3xxx_uart2_addr_space, 2376 .user = OCP_USER_MPU | OCP_USER_SDMA, 2377 }; 2378 2379 /* L4 PER -> UART3 interface */ 2380 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = { 2381 { 2382 .pa_start = OMAP3_UART3_BASE, 2383 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1, 2384 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 2385 }, 2386 { } 2387 }; 2388 2389 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { 2390 .master = &omap3xxx_l4_per_hwmod, 2391 .slave = &omap3xxx_uart3_hwmod, 2392 .clk = "uart3_ick", 2393 .addr = omap3xxx_uart3_addr_space, 2394 .user = OCP_USER_MPU | OCP_USER_SDMA, 2395 }; 2396 2397 /* L4 PER -> UART4 interface */ 2398 static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = { 2399 { 2400 .pa_start = OMAP3_UART4_BASE, 2401 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1, 2402 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 2403 }, 2404 { } 2405 }; 2406 2407 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = { 2408 .master = &omap3xxx_l4_per_hwmod, 2409 .slave = &omap36xx_uart4_hwmod, 2410 .clk = "uart4_ick", 2411 .addr = omap36xx_uart4_addr_space, 2412 .user = OCP_USER_MPU | OCP_USER_SDMA, 2413 }; 2414 2415 /* AM35xx: L4 CORE -> UART4 interface */ 2416 static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = { 2417 { 2418 .pa_start = OMAP3_UART4_AM35XX_BASE, 2419 .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1, 2420 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 2421 }, 2422 { } 2423 }; 2424 2425 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = { 2426 .master = &omap3xxx_l4_core_hwmod, 2427 .slave = &am35xx_uart4_hwmod, 2428 .clk = "uart4_ick", 2429 .addr = am35xx_uart4_addr_space, 2430 .user = OCP_USER_MPU | OCP_USER_SDMA, 2431 }; 2432 2433 /* L4 CORE -> I2C1 interface */ 2434 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { 2435 .master = &omap3xxx_l4_core_hwmod, 2436 .slave = &omap3xxx_i2c1_hwmod, 2437 .clk = "i2c1_ick", 2438 .addr = omap2_i2c1_addr_space, 2439 .fw = { 2440 .omap2 = { 2441 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, 2442 .l4_prot_group = 7, 2443 .flags = OMAP_FIREWALL_L4, 2444 } 2445 }, 2446 .user = OCP_USER_MPU | OCP_USER_SDMA, 2447 }; 2448 2449 /* L4 CORE -> I2C2 interface */ 2450 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { 2451 .master = &omap3xxx_l4_core_hwmod, 2452 .slave = &omap3xxx_i2c2_hwmod, 2453 .clk = "i2c2_ick", 2454 .addr = omap2_i2c2_addr_space, 2455 .fw = { 2456 .omap2 = { 2457 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, 2458 .l4_prot_group = 7, 2459 .flags = OMAP_FIREWALL_L4, 2460 } 2461 }, 2462 .user = OCP_USER_MPU | OCP_USER_SDMA, 2463 }; 2464 2465 /* L4 CORE -> I2C3 interface */ 2466 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = { 2467 { 2468 .pa_start = 0x48060000, 2469 .pa_end = 0x48060000 + SZ_128 - 1, 2470 .flags = ADDR_TYPE_RT, 2471 }, 2472 { } 2473 }; 2474 2475 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { 2476 .master = &omap3xxx_l4_core_hwmod, 2477 .slave = &omap3xxx_i2c3_hwmod, 2478 .clk = "i2c3_ick", 2479 .addr = omap3xxx_i2c3_addr_space, 2480 .fw = { 2481 .omap2 = { 2482 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, 2483 .l4_prot_group = 7, 2484 .flags = OMAP_FIREWALL_L4, 2485 } 2486 }, 2487 .user = OCP_USER_MPU | OCP_USER_SDMA, 2488 }; 2489 2490 /* L4 CORE -> SR1 interface */ 2491 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = { 2492 { 2493 .pa_start = OMAP34XX_SR1_BASE, 2494 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1, 2495 .flags = ADDR_TYPE_RT, 2496 }, 2497 { } 2498 }; 2499 2500 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = { 2501 .master = &omap3xxx_l4_core_hwmod, 2502 .slave = &omap34xx_sr1_hwmod, 2503 .clk = "sr_l4_ick", 2504 .addr = omap3_sr1_addr_space, 2505 .user = OCP_USER_MPU, 2506 }; 2507 2508 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = { 2509 .master = &omap3xxx_l4_core_hwmod, 2510 .slave = &omap36xx_sr1_hwmod, 2511 .clk = "sr_l4_ick", 2512 .addr = omap3_sr1_addr_space, 2513 .user = OCP_USER_MPU, 2514 }; 2515 2516 /* L4 CORE -> SR1 interface */ 2517 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = { 2518 { 2519 .pa_start = OMAP34XX_SR2_BASE, 2520 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1, 2521 .flags = ADDR_TYPE_RT, 2522 }, 2523 { } 2524 }; 2525 2526 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = { 2527 .master = &omap3xxx_l4_core_hwmod, 2528 .slave = &omap34xx_sr2_hwmod, 2529 .clk = "sr_l4_ick", 2530 .addr = omap3_sr2_addr_space, 2531 .user = OCP_USER_MPU, 2532 }; 2533 2534 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = { 2535 .master = &omap3xxx_l4_core_hwmod, 2536 .slave = &omap36xx_sr2_hwmod, 2537 .clk = "sr_l4_ick", 2538 .addr = omap3_sr2_addr_space, 2539 .user = OCP_USER_MPU, 2540 }; 2541 2542 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = { 2543 { 2544 .pa_start = OMAP34XX_HSUSB_OTG_BASE, 2545 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1, 2546 .flags = ADDR_TYPE_RT 2547 }, 2548 { } 2549 }; 2550 2551 /* l4_core -> usbhsotg */ 2552 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { 2553 .master = &omap3xxx_l4_core_hwmod, 2554 .slave = &omap3xxx_usbhsotg_hwmod, 2555 .clk = "l4_ick", 2556 .addr = omap3xxx_usbhsotg_addrs, 2557 .user = OCP_USER_MPU, 2558 }; 2559 2560 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = { 2561 { 2562 .pa_start = AM35XX_IPSS_USBOTGSS_BASE, 2563 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1, 2564 .flags = ADDR_TYPE_RT 2565 }, 2566 { } 2567 }; 2568 2569 /* l4_core -> usbhsotg */ 2570 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { 2571 .master = &omap3xxx_l4_core_hwmod, 2572 .slave = &am35xx_usbhsotg_hwmod, 2573 .clk = "hsotgusb_ick", 2574 .addr = am35xx_usbhsotg_addrs, 2575 .user = OCP_USER_MPU, 2576 }; 2577 2578 /* L4_WKUP -> L4_SEC interface */ 2579 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = { 2580 .master = &omap3xxx_l4_wkup_hwmod, 2581 .slave = &omap3xxx_l4_sec_hwmod, 2582 .user = OCP_USER_MPU | OCP_USER_SDMA, 2583 }; 2584 2585 /* IVA2 <- L3 interface */ 2586 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = { 2587 .master = &omap3xxx_l3_main_hwmod, 2588 .slave = &omap3xxx_iva_hwmod, 2589 .clk = "core_l3_ick", 2590 .user = OCP_USER_MPU | OCP_USER_SDMA, 2591 }; 2592 2593 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = { 2594 { 2595 .pa_start = 0x48318000, 2596 .pa_end = 0x48318000 + SZ_1K - 1, 2597 .flags = ADDR_TYPE_RT 2598 }, 2599 { } 2600 }; 2601 2602 /* l4_wkup -> timer1 */ 2603 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = { 2604 .master = &omap3xxx_l4_wkup_hwmod, 2605 .slave = &omap3xxx_timer1_hwmod, 2606 .clk = "gpt1_ick", 2607 .addr = omap3xxx_timer1_addrs, 2608 .user = OCP_USER_MPU | OCP_USER_SDMA, 2609 }; 2610 2611 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = { 2612 { 2613 .pa_start = 0x49032000, 2614 .pa_end = 0x49032000 + SZ_1K - 1, 2615 .flags = ADDR_TYPE_RT 2616 }, 2617 { } 2618 }; 2619 2620 /* l4_per -> timer2 */ 2621 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = { 2622 .master = &omap3xxx_l4_per_hwmod, 2623 .slave = &omap3xxx_timer2_hwmod, 2624 .clk = "gpt2_ick", 2625 .addr = omap3xxx_timer2_addrs, 2626 .user = OCP_USER_MPU | OCP_USER_SDMA, 2627 }; 2628 2629 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = { 2630 { 2631 .pa_start = 0x49034000, 2632 .pa_end = 0x49034000 + SZ_1K - 1, 2633 .flags = ADDR_TYPE_RT 2634 }, 2635 { } 2636 }; 2637 2638 /* l4_per -> timer3 */ 2639 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = { 2640 .master = &omap3xxx_l4_per_hwmod, 2641 .slave = &omap3xxx_timer3_hwmod, 2642 .clk = "gpt3_ick", 2643 .addr = omap3xxx_timer3_addrs, 2644 .user = OCP_USER_MPU | OCP_USER_SDMA, 2645 }; 2646 2647 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = { 2648 { 2649 .pa_start = 0x49036000, 2650 .pa_end = 0x49036000 + SZ_1K - 1, 2651 .flags = ADDR_TYPE_RT 2652 }, 2653 { } 2654 }; 2655 2656 /* l4_per -> timer4 */ 2657 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = { 2658 .master = &omap3xxx_l4_per_hwmod, 2659 .slave = &omap3xxx_timer4_hwmod, 2660 .clk = "gpt4_ick", 2661 .addr = omap3xxx_timer4_addrs, 2662 .user = OCP_USER_MPU | OCP_USER_SDMA, 2663 }; 2664 2665 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = { 2666 { 2667 .pa_start = 0x49038000, 2668 .pa_end = 0x49038000 + SZ_1K - 1, 2669 .flags = ADDR_TYPE_RT 2670 }, 2671 { } 2672 }; 2673 2674 /* l4_per -> timer5 */ 2675 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = { 2676 .master = &omap3xxx_l4_per_hwmod, 2677 .slave = &omap3xxx_timer5_hwmod, 2678 .clk = "gpt5_ick", 2679 .addr = omap3xxx_timer5_addrs, 2680 .user = OCP_USER_MPU | OCP_USER_SDMA, 2681 }; 2682 2683 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = { 2684 { 2685 .pa_start = 0x4903A000, 2686 .pa_end = 0x4903A000 + SZ_1K - 1, 2687 .flags = ADDR_TYPE_RT 2688 }, 2689 { } 2690 }; 2691 2692 /* l4_per -> timer6 */ 2693 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = { 2694 .master = &omap3xxx_l4_per_hwmod, 2695 .slave = &omap3xxx_timer6_hwmod, 2696 .clk = "gpt6_ick", 2697 .addr = omap3xxx_timer6_addrs, 2698 .user = OCP_USER_MPU | OCP_USER_SDMA, 2699 }; 2700 2701 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = { 2702 { 2703 .pa_start = 0x4903C000, 2704 .pa_end = 0x4903C000 + SZ_1K - 1, 2705 .flags = ADDR_TYPE_RT 2706 }, 2707 { } 2708 }; 2709 2710 /* l4_per -> timer7 */ 2711 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = { 2712 .master = &omap3xxx_l4_per_hwmod, 2713 .slave = &omap3xxx_timer7_hwmod, 2714 .clk = "gpt7_ick", 2715 .addr = omap3xxx_timer7_addrs, 2716 .user = OCP_USER_MPU | OCP_USER_SDMA, 2717 }; 2718 2719 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = { 2720 { 2721 .pa_start = 0x4903E000, 2722 .pa_end = 0x4903E000 + SZ_1K - 1, 2723 .flags = ADDR_TYPE_RT 2724 }, 2725 { } 2726 }; 2727 2728 /* l4_per -> timer8 */ 2729 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = { 2730 .master = &omap3xxx_l4_per_hwmod, 2731 .slave = &omap3xxx_timer8_hwmod, 2732 .clk = "gpt8_ick", 2733 .addr = omap3xxx_timer8_addrs, 2734 .user = OCP_USER_MPU | OCP_USER_SDMA, 2735 }; 2736 2737 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = { 2738 { 2739 .pa_start = 0x49040000, 2740 .pa_end = 0x49040000 + SZ_1K - 1, 2741 .flags = ADDR_TYPE_RT 2742 }, 2743 { } 2744 }; 2745 2746 /* l4_per -> timer9 */ 2747 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = { 2748 .master = &omap3xxx_l4_per_hwmod, 2749 .slave = &omap3xxx_timer9_hwmod, 2750 .clk = "gpt9_ick", 2751 .addr = omap3xxx_timer9_addrs, 2752 .user = OCP_USER_MPU | OCP_USER_SDMA, 2753 }; 2754 2755 /* l4_core -> timer10 */ 2756 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = { 2757 .master = &omap3xxx_l4_core_hwmod, 2758 .slave = &omap3xxx_timer10_hwmod, 2759 .clk = "gpt10_ick", 2760 .addr = omap2_timer10_addrs, 2761 .user = OCP_USER_MPU | OCP_USER_SDMA, 2762 }; 2763 2764 /* l4_core -> timer11 */ 2765 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { 2766 .master = &omap3xxx_l4_core_hwmod, 2767 .slave = &omap3xxx_timer11_hwmod, 2768 .clk = "gpt11_ick", 2769 .addr = omap2_timer11_addrs, 2770 .user = OCP_USER_MPU | OCP_USER_SDMA, 2771 }; 2772 2773 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = { 2774 { 2775 .pa_start = 0x48304000, 2776 .pa_end = 0x48304000 + SZ_1K - 1, 2777 .flags = ADDR_TYPE_RT 2778 }, 2779 { } 2780 }; 2781 2782 /* l4_core -> timer12 */ 2783 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = { 2784 .master = &omap3xxx_l4_sec_hwmod, 2785 .slave = &omap3xxx_timer12_hwmod, 2786 .clk = "gpt12_ick", 2787 .addr = omap3xxx_timer12_addrs, 2788 .user = OCP_USER_MPU | OCP_USER_SDMA, 2789 }; 2790 2791 /* l4_wkup -> wd_timer2 */ 2792 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { 2793 { 2794 .pa_start = 0x48314000, 2795 .pa_end = 0x4831407f, 2796 .flags = ADDR_TYPE_RT 2797 }, 2798 { } 2799 }; 2800 2801 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { 2802 .master = &omap3xxx_l4_wkup_hwmod, 2803 .slave = &omap3xxx_wd_timer2_hwmod, 2804 .clk = "wdt2_ick", 2805 .addr = omap3xxx_wd_timer2_addrs, 2806 .user = OCP_USER_MPU | OCP_USER_SDMA, 2807 }; 2808 2809 /* l4_core -> dss */ 2810 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { 2811 .master = &omap3xxx_l4_core_hwmod, 2812 .slave = &omap3430es1_dss_core_hwmod, 2813 .clk = "dss_ick", 2814 .addr = omap2_dss_addrs, 2815 .fw = { 2816 .omap2 = { 2817 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, 2818 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 2819 .flags = OMAP_FIREWALL_L4, 2820 } 2821 }, 2822 .user = OCP_USER_MPU | OCP_USER_SDMA, 2823 }; 2824 2825 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = { 2826 .master = &omap3xxx_l4_core_hwmod, 2827 .slave = &omap3xxx_dss_core_hwmod, 2828 .clk = "dss_ick", 2829 .addr = omap2_dss_addrs, 2830 .fw = { 2831 .omap2 = { 2832 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, 2833 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 2834 .flags = OMAP_FIREWALL_L4, 2835 } 2836 }, 2837 .user = OCP_USER_MPU | OCP_USER_SDMA, 2838 }; 2839 2840 /* l4_core -> dss_dispc */ 2841 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { 2842 .master = &omap3xxx_l4_core_hwmod, 2843 .slave = &omap3xxx_dss_dispc_hwmod, 2844 .clk = "dss_ick", 2845 .addr = omap2_dss_dispc_addrs, 2846 .fw = { 2847 .omap2 = { 2848 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, 2849 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 2850 .flags = OMAP_FIREWALL_L4, 2851 } 2852 }, 2853 .user = OCP_USER_MPU | OCP_USER_SDMA, 2854 }; 2855 2856 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = { 2857 { 2858 .pa_start = 0x4804FC00, 2859 .pa_end = 0x4804FFFF, 2860 .flags = ADDR_TYPE_RT 2861 }, 2862 { } 2863 }; 2864 2865 /* l4_core -> dss_dsi1 */ 2866 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { 2867 .master = &omap3xxx_l4_core_hwmod, 2868 .slave = &omap3xxx_dss_dsi1_hwmod, 2869 .clk = "dss_ick", 2870 .addr = omap3xxx_dss_dsi1_addrs, 2871 .fw = { 2872 .omap2 = { 2873 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, 2874 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 2875 .flags = OMAP_FIREWALL_L4, 2876 } 2877 }, 2878 .user = OCP_USER_MPU | OCP_USER_SDMA, 2879 }; 2880 2881 /* l4_core -> dss_rfbi */ 2882 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { 2883 .master = &omap3xxx_l4_core_hwmod, 2884 .slave = &omap3xxx_dss_rfbi_hwmod, 2885 .clk = "dss_ick", 2886 .addr = omap2_dss_rfbi_addrs, 2887 .fw = { 2888 .omap2 = { 2889 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, 2890 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP , 2891 .flags = OMAP_FIREWALL_L4, 2892 } 2893 }, 2894 .user = OCP_USER_MPU | OCP_USER_SDMA, 2895 }; 2896 2897 /* l4_core -> dss_venc */ 2898 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { 2899 .master = &omap3xxx_l4_core_hwmod, 2900 .slave = &omap3xxx_dss_venc_hwmod, 2901 .clk = "dss_ick", 2902 .addr = omap2_dss_venc_addrs, 2903 .fw = { 2904 .omap2 = { 2905 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, 2906 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 2907 .flags = OMAP_FIREWALL_L4, 2908 } 2909 }, 2910 .flags = OCPIF_SWSUP_IDLE, 2911 .user = OCP_USER_MPU | OCP_USER_SDMA, 2912 }; 2913 2914 /* l4_wkup -> gpio1 */ 2915 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = { 2916 { 2917 .pa_start = 0x48310000, 2918 .pa_end = 0x483101ff, 2919 .flags = ADDR_TYPE_RT 2920 }, 2921 { } 2922 }; 2923 2924 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { 2925 .master = &omap3xxx_l4_wkup_hwmod, 2926 .slave = &omap3xxx_gpio1_hwmod, 2927 .addr = omap3xxx_gpio1_addrs, 2928 .user = OCP_USER_MPU | OCP_USER_SDMA, 2929 }; 2930 2931 /* l4_per -> gpio2 */ 2932 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = { 2933 { 2934 .pa_start = 0x49050000, 2935 .pa_end = 0x490501ff, 2936 .flags = ADDR_TYPE_RT 2937 }, 2938 { } 2939 }; 2940 2941 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { 2942 .master = &omap3xxx_l4_per_hwmod, 2943 .slave = &omap3xxx_gpio2_hwmod, 2944 .addr = omap3xxx_gpio2_addrs, 2945 .user = OCP_USER_MPU | OCP_USER_SDMA, 2946 }; 2947 2948 /* l4_per -> gpio3 */ 2949 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = { 2950 { 2951 .pa_start = 0x49052000, 2952 .pa_end = 0x490521ff, 2953 .flags = ADDR_TYPE_RT 2954 }, 2955 { } 2956 }; 2957 2958 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { 2959 .master = &omap3xxx_l4_per_hwmod, 2960 .slave = &omap3xxx_gpio3_hwmod, 2961 .addr = omap3xxx_gpio3_addrs, 2962 .user = OCP_USER_MPU | OCP_USER_SDMA, 2963 }; 2964 2965 /* 2966 * 'mmu' class 2967 * The memory management unit performs virtual to physical address translation 2968 * for its requestors. 2969 */ 2970 2971 static struct omap_hwmod_class_sysconfig mmu_sysc = { 2972 .rev_offs = 0x000, 2973 .sysc_offs = 0x010, 2974 .syss_offs = 0x014, 2975 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 2976 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), 2977 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 2978 .sysc_fields = &omap_hwmod_sysc_type1, 2979 }; 2980 2981 static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = { 2982 .name = "mmu", 2983 .sysc = &mmu_sysc, 2984 }; 2985 2986 /* mmu isp */ 2987 2988 static struct omap_mmu_dev_attr mmu_isp_dev_attr = { 2989 .da_start = 0x0, 2990 .da_end = 0xfffff000, 2991 .nr_tlb_entries = 8, 2992 }; 2993 2994 static struct omap_hwmod omap3xxx_mmu_isp_hwmod; 2995 static struct omap_hwmod_irq_info omap3xxx_mmu_isp_irqs[] = { 2996 { .irq = 24 }, 2997 { .irq = -1 } 2998 }; 2999 3000 static struct omap_hwmod_addr_space omap3xxx_mmu_isp_addrs[] = { 3001 { 3002 .pa_start = 0x480bd400, 3003 .pa_end = 0x480bd47f, 3004 .flags = ADDR_TYPE_RT, 3005 }, 3006 { } 3007 }; 3008 3009 /* l4_core -> mmu isp */ 3010 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = { 3011 .master = &omap3xxx_l4_core_hwmod, 3012 .slave = &omap3xxx_mmu_isp_hwmod, 3013 .addr = omap3xxx_mmu_isp_addrs, 3014 .user = OCP_USER_MPU | OCP_USER_SDMA, 3015 }; 3016 3017 static struct omap_hwmod omap3xxx_mmu_isp_hwmod = { 3018 .name = "mmu_isp", 3019 .class = &omap3xxx_mmu_hwmod_class, 3020 .mpu_irqs = omap3xxx_mmu_isp_irqs, 3021 .main_clk = "cam_ick", 3022 .dev_attr = &mmu_isp_dev_attr, 3023 .flags = HWMOD_NO_IDLEST, 3024 }; 3025 3026 #ifdef CONFIG_OMAP_IOMMU_IVA2 3027 3028 /* mmu iva */ 3029 3030 static struct omap_mmu_dev_attr mmu_iva_dev_attr = { 3031 .da_start = 0x11000000, 3032 .da_end = 0xfffff000, 3033 .nr_tlb_entries = 32, 3034 }; 3035 3036 static struct omap_hwmod omap3xxx_mmu_iva_hwmod; 3037 static struct omap_hwmod_irq_info omap3xxx_mmu_iva_irqs[] = { 3038 { .irq = 28 }, 3039 { .irq = -1 } 3040 }; 3041 3042 static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = { 3043 { .name = "mmu", .rst_shift = 1, .st_shift = 9 }, 3044 }; 3045 3046 static struct omap_hwmod_addr_space omap3xxx_mmu_iva_addrs[] = { 3047 { 3048 .pa_start = 0x5d000000, 3049 .pa_end = 0x5d00007f, 3050 .flags = ADDR_TYPE_RT, 3051 }, 3052 { } 3053 }; 3054 3055 /* l3_main -> iva mmu */ 3056 static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = { 3057 .master = &omap3xxx_l3_main_hwmod, 3058 .slave = &omap3xxx_mmu_iva_hwmod, 3059 .addr = omap3xxx_mmu_iva_addrs, 3060 .user = OCP_USER_MPU | OCP_USER_SDMA, 3061 }; 3062 3063 static struct omap_hwmod omap3xxx_mmu_iva_hwmod = { 3064 .name = "mmu_iva", 3065 .class = &omap3xxx_mmu_hwmod_class, 3066 .mpu_irqs = omap3xxx_mmu_iva_irqs, 3067 .rst_lines = omap3xxx_mmu_iva_resets, 3068 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_mmu_iva_resets), 3069 .main_clk = "iva2_ck", 3070 .prcm = { 3071 .omap2 = { 3072 .module_offs = OMAP3430_IVA2_MOD, 3073 }, 3074 }, 3075 .dev_attr = &mmu_iva_dev_attr, 3076 .flags = HWMOD_NO_IDLEST, 3077 }; 3078 3079 #endif 3080 3081 /* l4_per -> gpio4 */ 3082 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = { 3083 { 3084 .pa_start = 0x49054000, 3085 .pa_end = 0x490541ff, 3086 .flags = ADDR_TYPE_RT 3087 }, 3088 { } 3089 }; 3090 3091 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { 3092 .master = &omap3xxx_l4_per_hwmod, 3093 .slave = &omap3xxx_gpio4_hwmod, 3094 .addr = omap3xxx_gpio4_addrs, 3095 .user = OCP_USER_MPU | OCP_USER_SDMA, 3096 }; 3097 3098 /* l4_per -> gpio5 */ 3099 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = { 3100 { 3101 .pa_start = 0x49056000, 3102 .pa_end = 0x490561ff, 3103 .flags = ADDR_TYPE_RT 3104 }, 3105 { } 3106 }; 3107 3108 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { 3109 .master = &omap3xxx_l4_per_hwmod, 3110 .slave = &omap3xxx_gpio5_hwmod, 3111 .addr = omap3xxx_gpio5_addrs, 3112 .user = OCP_USER_MPU | OCP_USER_SDMA, 3113 }; 3114 3115 /* l4_per -> gpio6 */ 3116 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = { 3117 { 3118 .pa_start = 0x49058000, 3119 .pa_end = 0x490581ff, 3120 .flags = ADDR_TYPE_RT 3121 }, 3122 { } 3123 }; 3124 3125 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { 3126 .master = &omap3xxx_l4_per_hwmod, 3127 .slave = &omap3xxx_gpio6_hwmod, 3128 .addr = omap3xxx_gpio6_addrs, 3129 .user = OCP_USER_MPU | OCP_USER_SDMA, 3130 }; 3131 3132 /* dma_system -> L3 */ 3133 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = { 3134 .master = &omap3xxx_dma_system_hwmod, 3135 .slave = &omap3xxx_l3_main_hwmod, 3136 .clk = "core_l3_ick", 3137 .user = OCP_USER_MPU | OCP_USER_SDMA, 3138 }; 3139 3140 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { 3141 { 3142 .pa_start = 0x48056000, 3143 .pa_end = 0x48056fff, 3144 .flags = ADDR_TYPE_RT 3145 }, 3146 { } 3147 }; 3148 3149 /* l4_cfg -> dma_system */ 3150 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = { 3151 .master = &omap3xxx_l4_core_hwmod, 3152 .slave = &omap3xxx_dma_system_hwmod, 3153 .clk = "core_l4_ick", 3154 .addr = omap3xxx_dma_system_addrs, 3155 .user = OCP_USER_MPU | OCP_USER_SDMA, 3156 }; 3157 3158 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = { 3159 { 3160 .name = "mpu", 3161 .pa_start = 0x48074000, 3162 .pa_end = 0x480740ff, 3163 .flags = ADDR_TYPE_RT 3164 }, 3165 { } 3166 }; 3167 3168 /* l4_core -> mcbsp1 */ 3169 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = { 3170 .master = &omap3xxx_l4_core_hwmod, 3171 .slave = &omap3xxx_mcbsp1_hwmod, 3172 .clk = "mcbsp1_ick", 3173 .addr = omap3xxx_mcbsp1_addrs, 3174 .user = OCP_USER_MPU | OCP_USER_SDMA, 3175 }; 3176 3177 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = { 3178 { 3179 .name = "mpu", 3180 .pa_start = 0x49022000, 3181 .pa_end = 0x490220ff, 3182 .flags = ADDR_TYPE_RT 3183 }, 3184 { } 3185 }; 3186 3187 /* l4_per -> mcbsp2 */ 3188 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = { 3189 .master = &omap3xxx_l4_per_hwmod, 3190 .slave = &omap3xxx_mcbsp2_hwmod, 3191 .clk = "mcbsp2_ick", 3192 .addr = omap3xxx_mcbsp2_addrs, 3193 .user = OCP_USER_MPU | OCP_USER_SDMA, 3194 }; 3195 3196 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = { 3197 { 3198 .name = "mpu", 3199 .pa_start = 0x49024000, 3200 .pa_end = 0x490240ff, 3201 .flags = ADDR_TYPE_RT 3202 }, 3203 { } 3204 }; 3205 3206 /* l4_per -> mcbsp3 */ 3207 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = { 3208 .master = &omap3xxx_l4_per_hwmod, 3209 .slave = &omap3xxx_mcbsp3_hwmod, 3210 .clk = "mcbsp3_ick", 3211 .addr = omap3xxx_mcbsp3_addrs, 3212 .user = OCP_USER_MPU | OCP_USER_SDMA, 3213 }; 3214 3215 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = { 3216 { 3217 .name = "mpu", 3218 .pa_start = 0x49026000, 3219 .pa_end = 0x490260ff, 3220 .flags = ADDR_TYPE_RT 3221 }, 3222 { } 3223 }; 3224 3225 /* l4_per -> mcbsp4 */ 3226 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = { 3227 .master = &omap3xxx_l4_per_hwmod, 3228 .slave = &omap3xxx_mcbsp4_hwmod, 3229 .clk = "mcbsp4_ick", 3230 .addr = omap3xxx_mcbsp4_addrs, 3231 .user = OCP_USER_MPU | OCP_USER_SDMA, 3232 }; 3233 3234 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = { 3235 { 3236 .name = "mpu", 3237 .pa_start = 0x48096000, 3238 .pa_end = 0x480960ff, 3239 .flags = ADDR_TYPE_RT 3240 }, 3241 { } 3242 }; 3243 3244 /* l4_core -> mcbsp5 */ 3245 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = { 3246 .master = &omap3xxx_l4_core_hwmod, 3247 .slave = &omap3xxx_mcbsp5_hwmod, 3248 .clk = "mcbsp5_ick", 3249 .addr = omap3xxx_mcbsp5_addrs, 3250 .user = OCP_USER_MPU | OCP_USER_SDMA, 3251 }; 3252 3253 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = { 3254 { 3255 .name = "sidetone", 3256 .pa_start = 0x49028000, 3257 .pa_end = 0x490280ff, 3258 .flags = ADDR_TYPE_RT 3259 }, 3260 { } 3261 }; 3262 3263 /* l4_per -> mcbsp2_sidetone */ 3264 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = { 3265 .master = &omap3xxx_l4_per_hwmod, 3266 .slave = &omap3xxx_mcbsp2_sidetone_hwmod, 3267 .clk = "mcbsp2_ick", 3268 .addr = omap3xxx_mcbsp2_sidetone_addrs, 3269 .user = OCP_USER_MPU, 3270 }; 3271 3272 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = { 3273 { 3274 .name = "sidetone", 3275 .pa_start = 0x4902A000, 3276 .pa_end = 0x4902A0ff, 3277 .flags = ADDR_TYPE_RT 3278 }, 3279 { } 3280 }; 3281 3282 /* l4_per -> mcbsp3_sidetone */ 3283 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = { 3284 .master = &omap3xxx_l4_per_hwmod, 3285 .slave = &omap3xxx_mcbsp3_sidetone_hwmod, 3286 .clk = "mcbsp3_ick", 3287 .addr = omap3xxx_mcbsp3_sidetone_addrs, 3288 .user = OCP_USER_MPU, 3289 }; 3290 3291 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = { 3292 { 3293 .pa_start = 0x48094000, 3294 .pa_end = 0x480941ff, 3295 .flags = ADDR_TYPE_RT, 3296 }, 3297 { } 3298 }; 3299 3300 /* l4_core -> mailbox */ 3301 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = { 3302 .master = &omap3xxx_l4_core_hwmod, 3303 .slave = &omap3xxx_mailbox_hwmod, 3304 .addr = omap3xxx_mailbox_addrs, 3305 .user = OCP_USER_MPU | OCP_USER_SDMA, 3306 }; 3307 3308 /* l4 core -> mcspi1 interface */ 3309 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { 3310 .master = &omap3xxx_l4_core_hwmod, 3311 .slave = &omap34xx_mcspi1, 3312 .clk = "mcspi1_ick", 3313 .addr = omap2_mcspi1_addr_space, 3314 .user = OCP_USER_MPU | OCP_USER_SDMA, 3315 }; 3316 3317 /* l4 core -> mcspi2 interface */ 3318 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { 3319 .master = &omap3xxx_l4_core_hwmod, 3320 .slave = &omap34xx_mcspi2, 3321 .clk = "mcspi2_ick", 3322 .addr = omap2_mcspi2_addr_space, 3323 .user = OCP_USER_MPU | OCP_USER_SDMA, 3324 }; 3325 3326 /* l4 core -> mcspi3 interface */ 3327 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { 3328 .master = &omap3xxx_l4_core_hwmod, 3329 .slave = &omap34xx_mcspi3, 3330 .clk = "mcspi3_ick", 3331 .addr = omap2430_mcspi3_addr_space, 3332 .user = OCP_USER_MPU | OCP_USER_SDMA, 3333 }; 3334 3335 /* l4 core -> mcspi4 interface */ 3336 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = { 3337 { 3338 .pa_start = 0x480ba000, 3339 .pa_end = 0x480ba0ff, 3340 .flags = ADDR_TYPE_RT, 3341 }, 3342 { } 3343 }; 3344 3345 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { 3346 .master = &omap3xxx_l4_core_hwmod, 3347 .slave = &omap34xx_mcspi4, 3348 .clk = "mcspi4_ick", 3349 .addr = omap34xx_mcspi4_addr_space, 3350 .user = OCP_USER_MPU | OCP_USER_SDMA, 3351 }; 3352 3353 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = { 3354 .master = &omap3xxx_usb_host_hs_hwmod, 3355 .slave = &omap3xxx_l3_main_hwmod, 3356 .clk = "core_l3_ick", 3357 .user = OCP_USER_MPU, 3358 }; 3359 3360 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = { 3361 { 3362 .name = "uhh", 3363 .pa_start = 0x48064000, 3364 .pa_end = 0x480643ff, 3365 .flags = ADDR_TYPE_RT 3366 }, 3367 { 3368 .name = "ohci", 3369 .pa_start = 0x48064400, 3370 .pa_end = 0x480647ff, 3371 }, 3372 { 3373 .name = "ehci", 3374 .pa_start = 0x48064800, 3375 .pa_end = 0x48064cff, 3376 }, 3377 {} 3378 }; 3379 3380 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = { 3381 .master = &omap3xxx_l4_core_hwmod, 3382 .slave = &omap3xxx_usb_host_hs_hwmod, 3383 .clk = "usbhost_ick", 3384 .addr = omap3xxx_usb_host_hs_addrs, 3385 .user = OCP_USER_MPU | OCP_USER_SDMA, 3386 }; 3387 3388 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = { 3389 { 3390 .name = "tll", 3391 .pa_start = 0x48062000, 3392 .pa_end = 0x48062fff, 3393 .flags = ADDR_TYPE_RT 3394 }, 3395 {} 3396 }; 3397 3398 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = { 3399 .master = &omap3xxx_l4_core_hwmod, 3400 .slave = &omap3xxx_usb_tll_hs_hwmod, 3401 .clk = "usbtll_ick", 3402 .addr = omap3xxx_usb_tll_hs_addrs, 3403 .user = OCP_USER_MPU | OCP_USER_SDMA, 3404 }; 3405 3406 /* l4_core -> hdq1w interface */ 3407 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = { 3408 .master = &omap3xxx_l4_core_hwmod, 3409 .slave = &omap3xxx_hdq1w_hwmod, 3410 .clk = "hdq_ick", 3411 .addr = omap2_hdq1w_addr_space, 3412 .user = OCP_USER_MPU | OCP_USER_SDMA, 3413 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, 3414 }; 3415 3416 /* l4_wkup -> 32ksync_counter */ 3417 static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = { 3418 { 3419 .pa_start = 0x48320000, 3420 .pa_end = 0x4832001f, 3421 .flags = ADDR_TYPE_RT 3422 }, 3423 { } 3424 }; 3425 3426 static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = { 3427 { 3428 .pa_start = 0x6e000000, 3429 .pa_end = 0x6e000fff, 3430 .flags = ADDR_TYPE_RT 3431 }, 3432 { } 3433 }; 3434 3435 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = { 3436 .master = &omap3xxx_l4_wkup_hwmod, 3437 .slave = &omap3xxx_counter_32k_hwmod, 3438 .clk = "omap_32ksync_ick", 3439 .addr = omap3xxx_counter_32k_addrs, 3440 .user = OCP_USER_MPU | OCP_USER_SDMA, 3441 }; 3442 3443 /* am35xx has Davinci MDIO & EMAC */ 3444 static struct omap_hwmod_class am35xx_mdio_class = { 3445 .name = "davinci_mdio", 3446 }; 3447 3448 static struct omap_hwmod am35xx_mdio_hwmod = { 3449 .name = "davinci_mdio", 3450 .class = &am35xx_mdio_class, 3451 .flags = HWMOD_NO_IDLEST, 3452 }; 3453 3454 /* 3455 * XXX Should be connected to an IPSS hwmod, not the L3 directly; 3456 * but this will probably require some additional hwmod core support, 3457 * so is left as a future to-do item. 3458 */ 3459 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = { 3460 .master = &am35xx_mdio_hwmod, 3461 .slave = &omap3xxx_l3_main_hwmod, 3462 .clk = "emac_fck", 3463 .user = OCP_USER_MPU, 3464 }; 3465 3466 static struct omap_hwmod_addr_space am35xx_mdio_addrs[] = { 3467 { 3468 .pa_start = AM35XX_IPSS_MDIO_BASE, 3469 .pa_end = AM35XX_IPSS_MDIO_BASE + SZ_4K - 1, 3470 .flags = ADDR_TYPE_RT, 3471 }, 3472 { } 3473 }; 3474 3475 /* l4_core -> davinci mdio */ 3476 /* 3477 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly; 3478 * but this will probably require some additional hwmod core support, 3479 * so is left as a future to-do item. 3480 */ 3481 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = { 3482 .master = &omap3xxx_l4_core_hwmod, 3483 .slave = &am35xx_mdio_hwmod, 3484 .clk = "emac_fck", 3485 .addr = am35xx_mdio_addrs, 3486 .user = OCP_USER_MPU, 3487 }; 3488 3489 static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = { 3490 { .name = "rxthresh", .irq = 67 + OMAP_INTC_START, }, 3491 { .name = "rx_pulse", .irq = 68 + OMAP_INTC_START, }, 3492 { .name = "tx_pulse", .irq = 69 + OMAP_INTC_START }, 3493 { .name = "misc_pulse", .irq = 70 + OMAP_INTC_START }, 3494 { .irq = -1 }, 3495 }; 3496 3497 static struct omap_hwmod_class am35xx_emac_class = { 3498 .name = "davinci_emac", 3499 }; 3500 3501 static struct omap_hwmod am35xx_emac_hwmod = { 3502 .name = "davinci_emac", 3503 .mpu_irqs = am35xx_emac_mpu_irqs, 3504 .class = &am35xx_emac_class, 3505 /* 3506 * According to Mark Greer, the MPU will not return from WFI 3507 * when the EMAC signals an interrupt. 3508 * http://www.spinics.net/lists/arm-kernel/msg174734.html 3509 */ 3510 .flags = (HWMOD_NO_IDLEST | HWMOD_BLOCK_WFI), 3511 }; 3512 3513 /* l3_core -> davinci emac interface */ 3514 /* 3515 * XXX Should be connected to an IPSS hwmod, not the L3 directly; 3516 * but this will probably require some additional hwmod core support, 3517 * so is left as a future to-do item. 3518 */ 3519 static struct omap_hwmod_ocp_if am35xx_emac__l3 = { 3520 .master = &am35xx_emac_hwmod, 3521 .slave = &omap3xxx_l3_main_hwmod, 3522 .clk = "emac_ick", 3523 .user = OCP_USER_MPU, 3524 }; 3525 3526 static struct omap_hwmod_addr_space am35xx_emac_addrs[] = { 3527 { 3528 .pa_start = AM35XX_IPSS_EMAC_BASE, 3529 .pa_end = AM35XX_IPSS_EMAC_BASE + 0x30000 - 1, 3530 .flags = ADDR_TYPE_RT, 3531 }, 3532 { } 3533 }; 3534 3535 /* l4_core -> davinci emac */ 3536 /* 3537 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly; 3538 * but this will probably require some additional hwmod core support, 3539 * so is left as a future to-do item. 3540 */ 3541 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = { 3542 .master = &omap3xxx_l4_core_hwmod, 3543 .slave = &am35xx_emac_hwmod, 3544 .clk = "emac_ick", 3545 .addr = am35xx_emac_addrs, 3546 .user = OCP_USER_MPU, 3547 }; 3548 3549 static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = { 3550 .master = &omap3xxx_l3_main_hwmod, 3551 .slave = &omap3xxx_gpmc_hwmod, 3552 .clk = "core_l3_ick", 3553 .addr = omap3xxx_gpmc_addrs, 3554 .user = OCP_USER_MPU | OCP_USER_SDMA, 3555 }; 3556 3557 /* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */ 3558 static struct omap_hwmod_sysc_fields omap3_sham_sysc_fields = { 3559 .sidle_shift = 4, 3560 .srst_shift = 1, 3561 .autoidle_shift = 0, 3562 }; 3563 3564 static struct omap_hwmod_class_sysconfig omap3_sham_sysc = { 3565 .rev_offs = 0x5c, 3566 .sysc_offs = 0x60, 3567 .syss_offs = 0x64, 3568 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 3569 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 3570 .sysc_fields = &omap3_sham_sysc_fields, 3571 }; 3572 3573 static struct omap_hwmod_class omap3xxx_sham_class = { 3574 .name = "sham", 3575 .sysc = &omap3_sham_sysc, 3576 }; 3577 3578 static struct omap_hwmod_irq_info omap3_sham_mpu_irqs[] = { 3579 { .irq = 49 + OMAP_INTC_START, }, 3580 { .irq = -1 } 3581 }; 3582 3583 static struct omap_hwmod_dma_info omap3_sham_sdma_reqs[] = { 3584 { .name = "rx", .dma_req = OMAP34XX_DMA_SHA1MD5_RX, }, 3585 { .dma_req = -1 } 3586 }; 3587 3588 static struct omap_hwmod omap3xxx_sham_hwmod = { 3589 .name = "sham", 3590 .mpu_irqs = omap3_sham_mpu_irqs, 3591 .sdma_reqs = omap3_sham_sdma_reqs, 3592 .main_clk = "sha12_ick", 3593 .prcm = { 3594 .omap2 = { 3595 .module_offs = CORE_MOD, 3596 .prcm_reg_id = 1, 3597 .module_bit = OMAP3430_EN_SHA12_SHIFT, 3598 .idlest_reg_id = 1, 3599 .idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT, 3600 }, 3601 }, 3602 .class = &omap3xxx_sham_class, 3603 }; 3604 3605 static struct omap_hwmod_addr_space omap3xxx_sham_addrs[] = { 3606 { 3607 .pa_start = 0x480c3000, 3608 .pa_end = 0x480c3000 + 0x64 - 1, 3609 .flags = ADDR_TYPE_RT 3610 }, 3611 { } 3612 }; 3613 3614 static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = { 3615 .master = &omap3xxx_l4_core_hwmod, 3616 .slave = &omap3xxx_sham_hwmod, 3617 .clk = "sha12_ick", 3618 .addr = omap3xxx_sham_addrs, 3619 .user = OCP_USER_MPU | OCP_USER_SDMA, 3620 }; 3621 3622 /* l4_core -> AES */ 3623 static struct omap_hwmod_sysc_fields omap3xxx_aes_sysc_fields = { 3624 .sidle_shift = 6, 3625 .srst_shift = 1, 3626 .autoidle_shift = 0, 3627 }; 3628 3629 static struct omap_hwmod_class_sysconfig omap3_aes_sysc = { 3630 .rev_offs = 0x44, 3631 .sysc_offs = 0x48, 3632 .syss_offs = 0x4c, 3633 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 3634 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 3635 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 3636 .sysc_fields = &omap3xxx_aes_sysc_fields, 3637 }; 3638 3639 static struct omap_hwmod_class omap3xxx_aes_class = { 3640 .name = "aes", 3641 .sysc = &omap3_aes_sysc, 3642 }; 3643 3644 static struct omap_hwmod_dma_info omap3_aes_sdma_reqs[] = { 3645 { .name = "tx", .dma_req = OMAP34XX_DMA_AES2_TX, }, 3646 { .name = "rx", .dma_req = OMAP34XX_DMA_AES2_RX, }, 3647 { .dma_req = -1 } 3648 }; 3649 3650 static struct omap_hwmod omap3xxx_aes_hwmod = { 3651 .name = "aes", 3652 .sdma_reqs = omap3_aes_sdma_reqs, 3653 .main_clk = "aes2_ick", 3654 .prcm = { 3655 .omap2 = { 3656 .module_offs = CORE_MOD, 3657 .prcm_reg_id = 1, 3658 .module_bit = OMAP3430_EN_AES2_SHIFT, 3659 .idlest_reg_id = 1, 3660 .idlest_idle_bit = OMAP3430_ST_AES2_SHIFT, 3661 }, 3662 }, 3663 .class = &omap3xxx_aes_class, 3664 }; 3665 3666 static struct omap_hwmod_addr_space omap3xxx_aes_addrs[] = { 3667 { 3668 .pa_start = 0x480c5000, 3669 .pa_end = 0x480c5000 + 0x50 - 1, 3670 .flags = ADDR_TYPE_RT 3671 }, 3672 { } 3673 }; 3674 3675 static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = { 3676 .master = &omap3xxx_l4_core_hwmod, 3677 .slave = &omap3xxx_aes_hwmod, 3678 .clk = "aes2_ick", 3679 .addr = omap3xxx_aes_addrs, 3680 .user = OCP_USER_MPU | OCP_USER_SDMA, 3681 }; 3682 3683 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { 3684 &omap3xxx_l3_main__l4_core, 3685 &omap3xxx_l3_main__l4_per, 3686 &omap3xxx_mpu__l3_main, 3687 &omap3xxx_l3_main__l4_debugss, 3688 &omap3xxx_l4_core__l4_wkup, 3689 &omap3xxx_l4_core__mmc3, 3690 &omap3_l4_core__uart1, 3691 &omap3_l4_core__uart2, 3692 &omap3_l4_per__uart3, 3693 &omap3_l4_core__i2c1, 3694 &omap3_l4_core__i2c2, 3695 &omap3_l4_core__i2c3, 3696 &omap3xxx_l4_wkup__l4_sec, 3697 &omap3xxx_l4_wkup__timer1, 3698 &omap3xxx_l4_per__timer2, 3699 &omap3xxx_l4_per__timer3, 3700 &omap3xxx_l4_per__timer4, 3701 &omap3xxx_l4_per__timer5, 3702 &omap3xxx_l4_per__timer6, 3703 &omap3xxx_l4_per__timer7, 3704 &omap3xxx_l4_per__timer8, 3705 &omap3xxx_l4_per__timer9, 3706 &omap3xxx_l4_core__timer10, 3707 &omap3xxx_l4_core__timer11, 3708 &omap3xxx_l4_wkup__wd_timer2, 3709 &omap3xxx_l4_wkup__gpio1, 3710 &omap3xxx_l4_per__gpio2, 3711 &omap3xxx_l4_per__gpio3, 3712 &omap3xxx_l4_per__gpio4, 3713 &omap3xxx_l4_per__gpio5, 3714 &omap3xxx_l4_per__gpio6, 3715 &omap3xxx_dma_system__l3, 3716 &omap3xxx_l4_core__dma_system, 3717 &omap3xxx_l4_core__mcbsp1, 3718 &omap3xxx_l4_per__mcbsp2, 3719 &omap3xxx_l4_per__mcbsp3, 3720 &omap3xxx_l4_per__mcbsp4, 3721 &omap3xxx_l4_core__mcbsp5, 3722 &omap3xxx_l4_per__mcbsp2_sidetone, 3723 &omap3xxx_l4_per__mcbsp3_sidetone, 3724 &omap34xx_l4_core__mcspi1, 3725 &omap34xx_l4_core__mcspi2, 3726 &omap34xx_l4_core__mcspi3, 3727 &omap34xx_l4_core__mcspi4, 3728 &omap3xxx_l4_wkup__counter_32k, 3729 &omap3xxx_l3_main__gpmc, 3730 NULL, 3731 }; 3732 3733 /* GP-only hwmod links */ 3734 static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = { 3735 &omap3xxx_l4_sec__timer12, 3736 &omap3xxx_l4_core__sham, 3737 &omap3xxx_l4_core__aes, 3738 NULL 3739 }; 3740 3741 static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = { 3742 &omap3xxx_l4_sec__timer12, 3743 &omap3xxx_l4_core__sham, 3744 &omap3xxx_l4_core__aes, 3745 NULL 3746 }; 3747 3748 static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = { 3749 &omap3xxx_l4_sec__timer12, 3750 /* 3751 * Apparently the SHA/MD5 and AES accelerator IP blocks are 3752 * only present on some AM35xx chips, and no one knows which 3753 * ones. See 3754 * http://www.spinics.net/lists/arm-kernel/msg215466.html So 3755 * if you need these IP blocks on an AM35xx, try uncommenting 3756 * the following lines. 3757 */ 3758 /* &omap3xxx_l4_core__sham, */ 3759 /* &omap3xxx_l4_core__aes, */ 3760 NULL 3761 }; 3762 3763 /* 3430ES1-only hwmod links */ 3764 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = { 3765 &omap3430es1_dss__l3, 3766 &omap3430es1_l4_core__dss, 3767 NULL 3768 }; 3769 3770 /* 3430ES2+-only hwmod links */ 3771 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = { 3772 &omap3xxx_dss__l3, 3773 &omap3xxx_l4_core__dss, 3774 &omap3xxx_usbhsotg__l3, 3775 &omap3xxx_l4_core__usbhsotg, 3776 &omap3xxx_usb_host_hs__l3_main_2, 3777 &omap3xxx_l4_core__usb_host_hs, 3778 &omap3xxx_l4_core__usb_tll_hs, 3779 NULL 3780 }; 3781 3782 /* <= 3430ES3-only hwmod links */ 3783 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = { 3784 &omap3xxx_l4_core__pre_es3_mmc1, 3785 &omap3xxx_l4_core__pre_es3_mmc2, 3786 NULL 3787 }; 3788 3789 /* 3430ES3+-only hwmod links */ 3790 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = { 3791 &omap3xxx_l4_core__es3plus_mmc1, 3792 &omap3xxx_l4_core__es3plus_mmc2, 3793 NULL 3794 }; 3795 3796 /* 34xx-only hwmod links (all ES revisions) */ 3797 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = { 3798 &omap3xxx_l3__iva, 3799 &omap34xx_l4_core__sr1, 3800 &omap34xx_l4_core__sr2, 3801 &omap3xxx_l4_core__mailbox, 3802 &omap3xxx_l4_core__hdq1w, 3803 &omap3xxx_sad2d__l3, 3804 &omap3xxx_l4_core__mmu_isp, 3805 #ifdef CONFIG_OMAP_IOMMU_IVA2 3806 &omap3xxx_l3_main__mmu_iva, 3807 #endif 3808 NULL 3809 }; 3810 3811 /* 36xx-only hwmod links (all ES revisions) */ 3812 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = { 3813 &omap3xxx_l3__iva, 3814 &omap36xx_l4_per__uart4, 3815 &omap3xxx_dss__l3, 3816 &omap3xxx_l4_core__dss, 3817 &omap36xx_l4_core__sr1, 3818 &omap36xx_l4_core__sr2, 3819 &omap3xxx_usbhsotg__l3, 3820 &omap3xxx_l4_core__usbhsotg, 3821 &omap3xxx_l4_core__mailbox, 3822 &omap3xxx_usb_host_hs__l3_main_2, 3823 &omap3xxx_l4_core__usb_host_hs, 3824 &omap3xxx_l4_core__usb_tll_hs, 3825 &omap3xxx_l4_core__es3plus_mmc1, 3826 &omap3xxx_l4_core__es3plus_mmc2, 3827 &omap3xxx_l4_core__hdq1w, 3828 &omap3xxx_sad2d__l3, 3829 &omap3xxx_l4_core__mmu_isp, 3830 #ifdef CONFIG_OMAP_IOMMU_IVA2 3831 &omap3xxx_l3_main__mmu_iva, 3832 #endif 3833 NULL 3834 }; 3835 3836 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = { 3837 &omap3xxx_dss__l3, 3838 &omap3xxx_l4_core__dss, 3839 &am35xx_usbhsotg__l3, 3840 &am35xx_l4_core__usbhsotg, 3841 &am35xx_l4_core__uart4, 3842 &omap3xxx_usb_host_hs__l3_main_2, 3843 &omap3xxx_l4_core__usb_host_hs, 3844 &omap3xxx_l4_core__usb_tll_hs, 3845 &omap3xxx_l4_core__es3plus_mmc1, 3846 &omap3xxx_l4_core__es3plus_mmc2, 3847 &omap3xxx_l4_core__hdq1w, 3848 &am35xx_mdio__l3, 3849 &am35xx_l4_core__mdio, 3850 &am35xx_emac__l3, 3851 &am35xx_l4_core__emac, 3852 NULL 3853 }; 3854 3855 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = { 3856 &omap3xxx_l4_core__dss_dispc, 3857 &omap3xxx_l4_core__dss_dsi1, 3858 &omap3xxx_l4_core__dss_rfbi, 3859 &omap3xxx_l4_core__dss_venc, 3860 NULL 3861 }; 3862 3863 int __init omap3xxx_hwmod_init(void) 3864 { 3865 int r; 3866 struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL; 3867 unsigned int rev; 3868 3869 omap_hwmod_init(); 3870 3871 /* Register hwmod links common to all OMAP3 */ 3872 r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs); 3873 if (r < 0) 3874 return r; 3875 3876 rev = omap_rev(); 3877 3878 /* 3879 * Register hwmod links common to individual OMAP3 families, all 3880 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx) 3881 * All possible revisions should be included in this conditional. 3882 */ 3883 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || 3884 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 || 3885 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { 3886 h = omap34xx_hwmod_ocp_ifs; 3887 h_gp = omap34xx_gp_hwmod_ocp_ifs; 3888 } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) { 3889 h = am35xx_hwmod_ocp_ifs; 3890 h_gp = am35xx_gp_hwmod_ocp_ifs; 3891 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 || 3892 rev == OMAP3630_REV_ES1_2) { 3893 h = omap36xx_hwmod_ocp_ifs; 3894 h_gp = omap36xx_gp_hwmod_ocp_ifs; 3895 } else { 3896 WARN(1, "OMAP3 hwmod family init: unknown chip type\n"); 3897 return -EINVAL; 3898 } 3899 3900 r = omap_hwmod_register_links(h); 3901 if (r < 0) 3902 return r; 3903 3904 /* Register GP-only hwmod links. */ 3905 if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) { 3906 r = omap_hwmod_register_links(h_gp); 3907 if (r < 0) 3908 return r; 3909 } 3910 3911 3912 /* 3913 * Register hwmod links specific to certain ES levels of a 3914 * particular family of silicon (e.g., 34xx ES1.0) 3915 */ 3916 h = NULL; 3917 if (rev == OMAP3430_REV_ES1_0) { 3918 h = omap3430es1_hwmod_ocp_ifs; 3919 } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 || 3920 rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || 3921 rev == OMAP3430_REV_ES3_1_2) { 3922 h = omap3430es2plus_hwmod_ocp_ifs; 3923 } 3924 3925 if (h) { 3926 r = omap_hwmod_register_links(h); 3927 if (r < 0) 3928 return r; 3929 } 3930 3931 h = NULL; 3932 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || 3933 rev == OMAP3430_REV_ES2_1) { 3934 h = omap3430_pre_es3_hwmod_ocp_ifs; 3935 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || 3936 rev == OMAP3430_REV_ES3_1_2) { 3937 h = omap3430_es3plus_hwmod_ocp_ifs; 3938 } 3939 3940 if (h) 3941 r = omap_hwmod_register_links(h); 3942 if (r < 0) 3943 return r; 3944 3945 /* 3946 * DSS code presumes that dss_core hwmod is handled first, 3947 * _before_ any other DSS related hwmods so register common 3948 * DSS hwmod links last to ensure that dss_core is already 3949 * registered. Otherwise some change things may happen, for 3950 * ex. if dispc is handled before dss_core and DSS is enabled 3951 * in bootloader DISPC will be reset with outputs enabled 3952 * which sometimes leads to unrecoverable L3 error. XXX The 3953 * long-term fix to this is to ensure hwmods are set up in 3954 * dependency order in the hwmod core code. 3955 */ 3956 r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs); 3957 3958 return r; 3959 } 3960