1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
4  *
5  * Copyright (C) 2009-2011 Nokia Corporation
6  * Copyright (C) 2012 Texas Instruments, Inc.
7  * Paul Walmsley
8  *
9  * The data in this file should be completely autogeneratable from
10  * the TI hardware database or other technical documentation.
11  *
12  * XXX these should be marked initdata for multi-OMAP kernels
13  */
14 
15 #include <linux/platform_data/i2c-omap.h>
16 #include <linux/power/smartreflex.h>
17 #include <linux/platform_data/hsmmc-omap.h>
18 
19 #include "l3_3xxx.h"
20 #include "l4_3xxx.h"
21 
22 #include "soc.h"
23 #include "omap_hwmod.h"
24 #include "omap_hwmod_common_data.h"
25 #include "prm-regbits-34xx.h"
26 #include "cm-regbits-34xx.h"
27 
28 #include "i2c.h"
29 #include "wd_timer.h"
30 #include "serial.h"
31 
32 /*
33  * OMAP3xxx hardware module integration data
34  *
35  * All of the data in this section should be autogeneratable from the
36  * TI hardware database or other technical documentation.  Data that
37  * is driver-specific or driver-kernel integration-specific belongs
38  * elsewhere.
39  */
40 
41 #define AM35XX_IPSS_USBOTGSS_BASE      0x5C040000
42 
43 /*
44  * IP blocks
45  */
46 
47 /* L3 */
48 
49 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
50 	.name		= "l3_main",
51 	.class		= &l3_hwmod_class,
52 	.flags		= HWMOD_NO_IDLEST,
53 };
54 
55 /* L4 CORE */
56 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
57 	.name		= "l4_core",
58 	.class		= &l4_hwmod_class,
59 	.flags		= HWMOD_NO_IDLEST,
60 };
61 
62 /* L4 PER */
63 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
64 	.name		= "l4_per",
65 	.class		= &l4_hwmod_class,
66 	.flags		= HWMOD_NO_IDLEST,
67 };
68 
69 /* L4 WKUP */
70 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
71 	.name		= "l4_wkup",
72 	.class		= &l4_hwmod_class,
73 	.flags		= HWMOD_NO_IDLEST,
74 };
75 
76 /* L4 SEC */
77 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
78 	.name		= "l4_sec",
79 	.class		= &l4_hwmod_class,
80 	.flags		= HWMOD_NO_IDLEST,
81 };
82 
83 /* MPU */
84 
85 static struct omap_hwmod omap3xxx_mpu_hwmod = {
86 	.name		= "mpu",
87 	.class		= &mpu_hwmod_class,
88 	.main_clk	= "arm_fck",
89 };
90 
91 /* IVA2 (IVA2) */
92 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
93 	{ .name = "logic", .rst_shift = 0, .st_shift = 8 },
94 	{ .name = "seq0", .rst_shift = 1, .st_shift = 9 },
95 	{ .name = "seq1", .rst_shift = 2, .st_shift = 10 },
96 };
97 
98 static struct omap_hwmod omap3xxx_iva_hwmod = {
99 	.name		= "iva",
100 	.class		= &iva_hwmod_class,
101 	.clkdm_name	= "iva2_clkdm",
102 	.rst_lines	= omap3xxx_iva_resets,
103 	.rst_lines_cnt	= ARRAY_SIZE(omap3xxx_iva_resets),
104 	.main_clk	= "iva2_ck",
105 	.prcm = {
106 		.omap2 = {
107 			.module_offs = OMAP3430_IVA2_MOD,
108 			.idlest_reg_id = 1,
109 			.idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
110 		},
111 	},
112 };
113 
114 /*
115  * 'debugss' class
116  * debug and emulation sub system
117  */
118 
119 static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = {
120 	.name	= "debugss",
121 };
122 
123 /* debugss */
124 static struct omap_hwmod omap3xxx_debugss_hwmod = {
125 	.name		= "debugss",
126 	.class		= &omap3xxx_debugss_hwmod_class,
127 	.clkdm_name	= "emu_clkdm",
128 	.main_clk	= "emu_src_ck",
129 	.flags		= HWMOD_NO_IDLEST,
130 };
131 
132 /* timer class */
133 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
134 	.rev_offs	= 0x0000,
135 	.sysc_offs	= 0x0010,
136 	.syss_offs	= 0x0014,
137 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
138 			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
139 			   SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
140 			   SYSS_HAS_RESET_STATUS),
141 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
142 	.sysc_fields	= &omap_hwmod_sysc_type1,
143 };
144 
145 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
146 	.name = "timer",
147 	.sysc = &omap3xxx_timer_sysc,
148 };
149 
150 /* timer3 */
151 static struct omap_hwmod omap3xxx_timer3_hwmod = {
152 	.name		= "timer3",
153 	.main_clk	= "gpt3_fck",
154 	.prcm		= {
155 		.omap2 = {
156 			.module_offs = OMAP3430_PER_MOD,
157 			.idlest_reg_id = 1,
158 			.idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
159 		},
160 	},
161 	.class		= &omap3xxx_timer_hwmod_class,
162 	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
163 };
164 
165 /* timer4 */
166 static struct omap_hwmod omap3xxx_timer4_hwmod = {
167 	.name		= "timer4",
168 	.main_clk	= "gpt4_fck",
169 	.prcm		= {
170 		.omap2 = {
171 			.module_offs = OMAP3430_PER_MOD,
172 			.idlest_reg_id = 1,
173 			.idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
174 		},
175 	},
176 	.class		= &omap3xxx_timer_hwmod_class,
177 	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
178 };
179 
180 /* timer5 */
181 static struct omap_hwmod omap3xxx_timer5_hwmod = {
182 	.name		= "timer5",
183 	.main_clk	= "gpt5_fck",
184 	.prcm		= {
185 		.omap2 = {
186 			.module_offs = OMAP3430_PER_MOD,
187 			.idlest_reg_id = 1,
188 			.idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
189 		},
190 	},
191 	.class		= &omap3xxx_timer_hwmod_class,
192 	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
193 };
194 
195 /* timer6 */
196 static struct omap_hwmod omap3xxx_timer6_hwmod = {
197 	.name		= "timer6",
198 	.main_clk	= "gpt6_fck",
199 	.prcm		= {
200 		.omap2 = {
201 			.module_offs = OMAP3430_PER_MOD,
202 			.idlest_reg_id = 1,
203 			.idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
204 		},
205 	},
206 	.class		= &omap3xxx_timer_hwmod_class,
207 	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
208 };
209 
210 /* timer7 */
211 static struct omap_hwmod omap3xxx_timer7_hwmod = {
212 	.name		= "timer7",
213 	.main_clk	= "gpt7_fck",
214 	.prcm		= {
215 		.omap2 = {
216 			.module_offs = OMAP3430_PER_MOD,
217 			.idlest_reg_id = 1,
218 			.idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
219 		},
220 	},
221 	.class		= &omap3xxx_timer_hwmod_class,
222 	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
223 };
224 
225 /* timer8 */
226 static struct omap_hwmod omap3xxx_timer8_hwmod = {
227 	.name		= "timer8",
228 	.main_clk	= "gpt8_fck",
229 	.prcm		= {
230 		.omap2 = {
231 			.module_offs = OMAP3430_PER_MOD,
232 			.idlest_reg_id = 1,
233 			.idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
234 		},
235 	},
236 	.class		= &omap3xxx_timer_hwmod_class,
237 	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
238 };
239 
240 /* timer9 */
241 static struct omap_hwmod omap3xxx_timer9_hwmod = {
242 	.name		= "timer9",
243 	.main_clk	= "gpt9_fck",
244 	.prcm		= {
245 		.omap2 = {
246 			.module_offs = OMAP3430_PER_MOD,
247 			.idlest_reg_id = 1,
248 			.idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
249 		},
250 	},
251 	.class		= &omap3xxx_timer_hwmod_class,
252 	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
253 };
254 
255 /* timer10 */
256 static struct omap_hwmod omap3xxx_timer10_hwmod = {
257 	.name		= "timer10",
258 	.main_clk	= "gpt10_fck",
259 	.prcm		= {
260 		.omap2 = {
261 			.module_offs = CORE_MOD,
262 			.idlest_reg_id = 1,
263 			.idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
264 		},
265 	},
266 	.class		= &omap3xxx_timer_hwmod_class,
267 	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
268 };
269 
270 /* timer11 */
271 static struct omap_hwmod omap3xxx_timer11_hwmod = {
272 	.name		= "timer11",
273 	.main_clk	= "gpt11_fck",
274 	.prcm		= {
275 		.omap2 = {
276 			.module_offs = CORE_MOD,
277 			.idlest_reg_id = 1,
278 			.idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
279 		},
280 	},
281 	.class		= &omap3xxx_timer_hwmod_class,
282 	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
283 };
284 
285 /*
286  * 'wd_timer' class
287  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
288  * overflow condition
289  */
290 
291 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
292 	.rev_offs	= 0x0000,
293 	.sysc_offs	= 0x0010,
294 	.syss_offs	= 0x0014,
295 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
296 			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
297 			   SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
298 			   SYSS_HAS_RESET_STATUS),
299 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
300 	.sysc_fields    = &omap_hwmod_sysc_type1,
301 };
302 
303 /* I2C common */
304 static struct omap_hwmod_class_sysconfig i2c_sysc = {
305 	.rev_offs	= 0x00,
306 	.sysc_offs	= 0x20,
307 	.syss_offs	= 0x10,
308 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
309 			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
310 			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
311 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
312 	.sysc_fields    = &omap_hwmod_sysc_type1,
313 };
314 
315 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
316 	.name		= "wd_timer",
317 	.sysc		= &omap3xxx_wd_timer_sysc,
318 	.pre_shutdown	= &omap2_wd_timer_disable,
319 	.reset		= &omap2_wd_timer_reset,
320 };
321 
322 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
323 	.name		= "wd_timer2",
324 	.class		= &omap3xxx_wd_timer_hwmod_class,
325 	.main_clk	= "wdt2_fck",
326 	.prcm		= {
327 		.omap2 = {
328 			.module_offs = WKUP_MOD,
329 			.idlest_reg_id = 1,
330 			.idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
331 		},
332 	},
333 	/*
334 	 * XXX: Use software supervised mode, HW supervised smartidle seems to
335 	 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
336 	 */
337 	.flags		= HWMOD_SWSUP_SIDLE,
338 };
339 
340 /* UART1 */
341 static struct omap_hwmod omap3xxx_uart1_hwmod = {
342 	.name		= "uart1",
343 	.main_clk	= "uart1_fck",
344 	.flags		= DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE,
345 	.prcm		= {
346 		.omap2 = {
347 			.module_offs = CORE_MOD,
348 			.idlest_reg_id = 1,
349 			.idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
350 		},
351 	},
352 	.class		= &omap2_uart_class,
353 };
354 
355 /* UART2 */
356 static struct omap_hwmod omap3xxx_uart2_hwmod = {
357 	.name		= "uart2",
358 	.main_clk	= "uart2_fck",
359 	.flags		= DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE,
360 	.prcm		= {
361 		.omap2 = {
362 			.module_offs = CORE_MOD,
363 			.idlest_reg_id = 1,
364 			.idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
365 		},
366 	},
367 	.class		= &omap2_uart_class,
368 };
369 
370 /* UART3 */
371 static struct omap_hwmod omap3xxx_uart3_hwmod = {
372 	.name		= "uart3",
373 	.main_clk	= "uart3_fck",
374 	.flags		= DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS |
375 				HWMOD_SWSUP_SIDLE,
376 	.prcm		= {
377 		.omap2 = {
378 			.module_offs = OMAP3430_PER_MOD,
379 			.idlest_reg_id = 1,
380 			.idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
381 		},
382 	},
383 	.class		= &omap2_uart_class,
384 };
385 
386 /* UART4 */
387 
388 
389 static struct omap_hwmod omap36xx_uart4_hwmod = {
390 	.name		= "uart4",
391 	.main_clk	= "uart4_fck",
392 	.flags		= DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE,
393 	.prcm		= {
394 		.omap2 = {
395 			.module_offs = OMAP3430_PER_MOD,
396 			.idlest_reg_id = 1,
397 			.idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
398 		},
399 	},
400 	.class		= &omap2_uart_class,
401 };
402 
403 
404 
405 /*
406  * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
407  * uart2_fck being enabled.  So we add uart1_fck as an optional clock,
408  * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET.  This really
409  * should not be needed.  The functional clock structure of the AM35xx
410  * UART4 is extremely unclear and opaque; it is unclear what the role
411  * of uart1/2_fck is for the UART4.  Any clarification from either
412  * empirical testing or the AM3505/3517 hardware designers would be
413  * most welcome.
414  */
415 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
416 	{ .role = "softreset_uart1_fck", .clk = "uart1_fck" },
417 };
418 
419 static struct omap_hwmod am35xx_uart4_hwmod = {
420 	.name		= "uart4",
421 	.main_clk	= "uart4_fck",
422 	.prcm		= {
423 		.omap2 = {
424 			.module_offs = CORE_MOD,
425 			.idlest_reg_id = 1,
426 			.idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
427 		},
428 	},
429 	.opt_clks	= am35xx_uart4_opt_clks,
430 	.opt_clks_cnt	= ARRAY_SIZE(am35xx_uart4_opt_clks),
431 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
432 	.class		= &omap2_uart_class,
433 };
434 
435 static struct omap_hwmod_class i2c_class = {
436 	.name	= "i2c",
437 	.sysc	= &i2c_sysc,
438 	.reset	= &omap_i2c_reset,
439 };
440 
441 /* dss */
442 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
443 	/*
444 	 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
445 	 * driver does not use these clocks.
446 	 */
447 	{ .role = "sys_clk", .clk = "dss2_alwon_fck" },
448 	{ .role = "tv_clk", .clk = "dss_tv_fck" },
449 	/* required only on OMAP3430 */
450 	{ .role = "tv_dac_clk", .clk = "dss_96m_fck" },
451 };
452 
453 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
454 	.name		= "dss_core",
455 	.class		= &omap2_dss_hwmod_class,
456 	.main_clk	= "dss1_alwon_fck", /* instead of dss_fck */
457 	.prcm		= {
458 		.omap2 = {
459 			.module_offs = OMAP3430_DSS_MOD,
460 			.idlest_reg_id = 1,
461 		},
462 	},
463 	.opt_clks	= dss_opt_clks,
464 	.opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
465 	.flags		= HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
466 };
467 
468 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
469 	.name		= "dss_core",
470 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
471 	.class		= &omap2_dss_hwmod_class,
472 	.main_clk	= "dss1_alwon_fck", /* instead of dss_fck */
473 	.prcm		= {
474 		.omap2 = {
475 			.module_offs = OMAP3430_DSS_MOD,
476 			.idlest_reg_id = 1,
477 			.idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
478 		},
479 	},
480 	.opt_clks	= dss_opt_clks,
481 	.opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
482 };
483 
484 /*
485  * 'dispc' class
486  * display controller
487  */
488 
489 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
490 	.rev_offs	= 0x0000,
491 	.sysc_offs	= 0x0010,
492 	.syss_offs	= 0x0014,
493 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
494 			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
495 			   SYSC_HAS_ENAWAKEUP),
496 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
497 			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
498 	.sysc_fields	= &omap_hwmod_sysc_type1,
499 };
500 
501 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
502 	.name	= "dispc",
503 	.sysc	= &omap3_dispc_sysc,
504 };
505 
506 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
507 	.name		= "dss_dispc",
508 	.class		= &omap3_dispc_hwmod_class,
509 	.main_clk	= "dss1_alwon_fck",
510 	.prcm		= {
511 		.omap2 = {
512 			.module_offs = OMAP3430_DSS_MOD,
513 		},
514 	},
515 	.flags		= HWMOD_NO_IDLEST,
516 	.dev_attr	= &omap2_3_dss_dispc_dev_attr,
517 };
518 
519 /*
520  * 'dsi' class
521  * display serial interface controller
522  */
523 
524 static struct omap_hwmod_class_sysconfig omap3xxx_dsi_sysc = {
525 	.rev_offs	= 0x0000,
526 	.sysc_offs	= 0x0010,
527 	.syss_offs	= 0x0014,
528 	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
529 			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
530 			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
531 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
532 	.sysc_fields	= &omap_hwmod_sysc_type1,
533 };
534 
535 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
536 	.name = "dsi",
537 	.sysc	= &omap3xxx_dsi_sysc,
538 };
539 
540 /* dss_dsi1 */
541 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
542 	{ .role = "sys_clk", .clk = "dss2_alwon_fck" },
543 };
544 
545 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
546 	.name		= "dss_dsi1",
547 	.class		= &omap3xxx_dsi_hwmod_class,
548 	.main_clk	= "dss1_alwon_fck",
549 	.prcm		= {
550 		.omap2 = {
551 			.module_offs = OMAP3430_DSS_MOD,
552 		},
553 	},
554 	.opt_clks	= dss_dsi1_opt_clks,
555 	.opt_clks_cnt	= ARRAY_SIZE(dss_dsi1_opt_clks),
556 	.flags		= HWMOD_NO_IDLEST,
557 };
558 
559 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
560 	{ .role = "ick", .clk = "dss_ick" },
561 };
562 
563 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
564 	.name		= "dss_rfbi",
565 	.class		= &omap2_rfbi_hwmod_class,
566 	.main_clk	= "dss1_alwon_fck",
567 	.prcm		= {
568 		.omap2 = {
569 			.module_offs = OMAP3430_DSS_MOD,
570 		},
571 	},
572 	.opt_clks	= dss_rfbi_opt_clks,
573 	.opt_clks_cnt	= ARRAY_SIZE(dss_rfbi_opt_clks),
574 	.flags		= HWMOD_NO_IDLEST,
575 };
576 
577 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
578 	/* required only on OMAP3430 */
579 	{ .role = "tv_dac_clk", .clk = "dss_96m_fck" },
580 };
581 
582 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
583 	.name		= "dss_venc",
584 	.class		= &omap2_venc_hwmod_class,
585 	.main_clk	= "dss_tv_fck",
586 	.prcm		= {
587 		.omap2 = {
588 			.module_offs = OMAP3430_DSS_MOD,
589 		},
590 	},
591 	.opt_clks	= dss_venc_opt_clks,
592 	.opt_clks_cnt	= ARRAY_SIZE(dss_venc_opt_clks),
593 	.flags		= HWMOD_NO_IDLEST,
594 };
595 
596 /* I2C1 */
597 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
598 	.name		= "i2c1",
599 	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
600 	.main_clk	= "i2c1_fck",
601 	.prcm		= {
602 		.omap2 = {
603 			.module_offs = CORE_MOD,
604 			.idlest_reg_id = 1,
605 			.idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
606 		},
607 	},
608 	.class		= &i2c_class,
609 };
610 
611 /* I2C2 */
612 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
613 	.name		= "i2c2",
614 	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
615 	.main_clk	= "i2c2_fck",
616 	.prcm		= {
617 		.omap2 = {
618 			.module_offs = CORE_MOD,
619 			.idlest_reg_id = 1,
620 			.idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
621 		},
622 	},
623 	.class		= &i2c_class,
624 };
625 
626 /* I2C3 */
627 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
628 	.name		= "i2c3",
629 	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
630 	.main_clk	= "i2c3_fck",
631 	.prcm		= {
632 		.omap2 = {
633 			.module_offs = CORE_MOD,
634 			.idlest_reg_id = 1,
635 			.idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
636 		},
637 	},
638 	.class		= &i2c_class,
639 };
640 
641 /*
642  * 'gpio' class
643  * general purpose io module
644  */
645 
646 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
647 	.rev_offs	= 0x0000,
648 	.sysc_offs	= 0x0010,
649 	.syss_offs	= 0x0014,
650 	.sysc_flags	= (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
651 			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
652 			   SYSS_HAS_RESET_STATUS),
653 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
654 	.sysc_fields    = &omap_hwmod_sysc_type1,
655 };
656 
657 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
658 	.name = "gpio",
659 	.sysc = &omap3xxx_gpio_sysc,
660 };
661 
662 /* gpio1 */
663 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
664 	{ .role = "dbclk", .clk = "gpio1_dbck", },
665 };
666 
667 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
668 	.name		= "gpio1",
669 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
670 	.main_clk	= "gpio1_ick",
671 	.opt_clks	= gpio1_opt_clks,
672 	.opt_clks_cnt	= ARRAY_SIZE(gpio1_opt_clks),
673 	.prcm		= {
674 		.omap2 = {
675 			.module_offs = WKUP_MOD,
676 			.idlest_reg_id = 1,
677 			.idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
678 		},
679 	},
680 	.class		= &omap3xxx_gpio_hwmod_class,
681 };
682 
683 /* gpio2 */
684 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
685 	{ .role = "dbclk", .clk = "gpio2_dbck", },
686 };
687 
688 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
689 	.name		= "gpio2",
690 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
691 	.main_clk	= "gpio2_ick",
692 	.opt_clks	= gpio2_opt_clks,
693 	.opt_clks_cnt	= ARRAY_SIZE(gpio2_opt_clks),
694 	.prcm		= {
695 		.omap2 = {
696 			.module_offs = OMAP3430_PER_MOD,
697 			.idlest_reg_id = 1,
698 			.idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
699 		},
700 	},
701 	.class		= &omap3xxx_gpio_hwmod_class,
702 };
703 
704 /* gpio3 */
705 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
706 	{ .role = "dbclk", .clk = "gpio3_dbck", },
707 };
708 
709 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
710 	.name		= "gpio3",
711 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
712 	.main_clk	= "gpio3_ick",
713 	.opt_clks	= gpio3_opt_clks,
714 	.opt_clks_cnt	= ARRAY_SIZE(gpio3_opt_clks),
715 	.prcm		= {
716 		.omap2 = {
717 			.module_offs = OMAP3430_PER_MOD,
718 			.idlest_reg_id = 1,
719 			.idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
720 		},
721 	},
722 	.class		= &omap3xxx_gpio_hwmod_class,
723 };
724 
725 /* gpio4 */
726 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
727 	{ .role = "dbclk", .clk = "gpio4_dbck", },
728 };
729 
730 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
731 	.name		= "gpio4",
732 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
733 	.main_clk	= "gpio4_ick",
734 	.opt_clks	= gpio4_opt_clks,
735 	.opt_clks_cnt	= ARRAY_SIZE(gpio4_opt_clks),
736 	.prcm		= {
737 		.omap2 = {
738 			.module_offs = OMAP3430_PER_MOD,
739 			.idlest_reg_id = 1,
740 			.idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
741 		},
742 	},
743 	.class		= &omap3xxx_gpio_hwmod_class,
744 };
745 
746 /* gpio5 */
747 
748 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
749 	{ .role = "dbclk", .clk = "gpio5_dbck", },
750 };
751 
752 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
753 	.name		= "gpio5",
754 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
755 	.main_clk	= "gpio5_ick",
756 	.opt_clks	= gpio5_opt_clks,
757 	.opt_clks_cnt	= ARRAY_SIZE(gpio5_opt_clks),
758 	.prcm		= {
759 		.omap2 = {
760 			.module_offs = OMAP3430_PER_MOD,
761 			.idlest_reg_id = 1,
762 			.idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
763 		},
764 	},
765 	.class		= &omap3xxx_gpio_hwmod_class,
766 };
767 
768 /* gpio6 */
769 
770 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
771 	{ .role = "dbclk", .clk = "gpio6_dbck", },
772 };
773 
774 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
775 	.name		= "gpio6",
776 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
777 	.main_clk	= "gpio6_ick",
778 	.opt_clks	= gpio6_opt_clks,
779 	.opt_clks_cnt	= ARRAY_SIZE(gpio6_opt_clks),
780 	.prcm		= {
781 		.omap2 = {
782 			.module_offs = OMAP3430_PER_MOD,
783 			.idlest_reg_id = 1,
784 			.idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
785 		},
786 	},
787 	.class		= &omap3xxx_gpio_hwmod_class,
788 };
789 
790 /*
791  * 'mcbsp' class
792  * multi channel buffered serial port controller
793  */
794 
795 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
796 	.rev_offs	= -ENODEV,
797 	.sysc_offs	= 0x008c,
798 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
799 			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
800 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
801 	.sysc_fields	= &omap_hwmod_sysc_type1,
802 };
803 
804 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
805 	.name = "mcbsp",
806 	.sysc = &omap3xxx_mcbsp_sysc,
807 };
808 
809 /* McBSP functional clock mapping */
810 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
811 	{ .role = "pad_fck", .clk = "mcbsp_clks" },
812 	{ .role = "prcm_fck", .clk = "core_96m_fck" },
813 };
814 
815 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
816 	{ .role = "pad_fck", .clk = "mcbsp_clks" },
817 	{ .role = "prcm_fck", .clk = "per_96m_fck" },
818 };
819 
820 /* mcbsp1 */
821 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
822 	.name		= "mcbsp1",
823 	.class		= &omap3xxx_mcbsp_hwmod_class,
824 	.main_clk	= "mcbsp1_fck",
825 	.prcm		= {
826 		.omap2 = {
827 			.module_offs = CORE_MOD,
828 			.idlest_reg_id = 1,
829 			.idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
830 		},
831 	},
832 	.opt_clks	= mcbsp15_opt_clks,
833 	.opt_clks_cnt	= ARRAY_SIZE(mcbsp15_opt_clks),
834 };
835 
836 /* mcbsp2 */
837 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
838 	.name		= "mcbsp2",
839 	.class		= &omap3xxx_mcbsp_hwmod_class,
840 	.main_clk	= "mcbsp2_fck",
841 	.prcm		= {
842 		.omap2 = {
843 			.module_offs = OMAP3430_PER_MOD,
844 			.idlest_reg_id = 1,
845 			.idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
846 		},
847 	},
848 	.opt_clks	= mcbsp234_opt_clks,
849 	.opt_clks_cnt	= ARRAY_SIZE(mcbsp234_opt_clks),
850 };
851 
852 /* mcbsp3 */
853 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
854 	.name		= "mcbsp3",
855 	.class		= &omap3xxx_mcbsp_hwmod_class,
856 	.main_clk	= "mcbsp3_fck",
857 	.prcm		= {
858 		.omap2 = {
859 			.module_offs = OMAP3430_PER_MOD,
860 			.idlest_reg_id = 1,
861 			.idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
862 		},
863 	},
864 	.opt_clks	= mcbsp234_opt_clks,
865 	.opt_clks_cnt	= ARRAY_SIZE(mcbsp234_opt_clks),
866 };
867 
868 /* mcbsp4 */
869 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
870 	.name		= "mcbsp4",
871 	.class		= &omap3xxx_mcbsp_hwmod_class,
872 	.main_clk	= "mcbsp4_fck",
873 	.prcm		= {
874 		.omap2 = {
875 			.module_offs = OMAP3430_PER_MOD,
876 			.idlest_reg_id = 1,
877 			.idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
878 		},
879 	},
880 	.opt_clks	= mcbsp234_opt_clks,
881 	.opt_clks_cnt	= ARRAY_SIZE(mcbsp234_opt_clks),
882 };
883 
884 /* mcbsp5 */
885 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
886 	.name		= "mcbsp5",
887 	.class		= &omap3xxx_mcbsp_hwmod_class,
888 	.main_clk	= "mcbsp5_fck",
889 	.prcm		= {
890 		.omap2 = {
891 			.module_offs = CORE_MOD,
892 			.idlest_reg_id = 1,
893 			.idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
894 		},
895 	},
896 	.opt_clks	= mcbsp15_opt_clks,
897 	.opt_clks_cnt	= ARRAY_SIZE(mcbsp15_opt_clks),
898 };
899 
900 /* 'mcbsp sidetone' class */
901 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
902 	.rev_offs	= -ENODEV,
903 	.sysc_offs	= 0x0010,
904 	.sysc_flags	= SYSC_HAS_AUTOIDLE,
905 	.sysc_fields	= &omap_hwmod_sysc_type1,
906 };
907 
908 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
909 	.name = "mcbsp_sidetone",
910 	.sysc = &omap3xxx_mcbsp_sidetone_sysc,
911 };
912 
913 /* mcbsp2_sidetone */
914 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
915 	.name		= "mcbsp2_sidetone",
916 	.class		= &omap3xxx_mcbsp_sidetone_hwmod_class,
917 	.main_clk	= "mcbsp2_ick",
918 	.flags		= HWMOD_NO_IDLEST,
919 };
920 
921 /* mcbsp3_sidetone */
922 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
923 	.name		= "mcbsp3_sidetone",
924 	.class		= &omap3xxx_mcbsp_sidetone_hwmod_class,
925 	.main_clk	= "mcbsp3_ick",
926 	.flags		= HWMOD_NO_IDLEST,
927 };
928 
929 /* SR common */
930 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
931 	.rev_offs	= -ENODEV,
932 	.sysc_offs	= 0x24,
933 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
934 	.sysc_fields	= &omap34xx_sr_sysc_fields,
935 };
936 
937 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
938 	.name = "smartreflex",
939 	.sysc = &omap34xx_sr_sysc,
940 };
941 
942 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
943 	.rev_offs	= -ENODEV,
944 	.sysc_offs	= 0x38,
945 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
946 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
947 			SYSC_NO_CACHE),
948 	.sysc_fields	= &omap36xx_sr_sysc_fields,
949 };
950 
951 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
952 	.name = "smartreflex",
953 	.sysc = &omap36xx_sr_sysc,
954 };
955 
956 /* SR1 */
957 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
958 	.sensor_voltdm_name   = "mpu_iva",
959 };
960 
961 
962 static struct omap_hwmod omap34xx_sr1_hwmod = {
963 	.name		= "smartreflex_mpu_iva",
964 	.class		= &omap34xx_smartreflex_hwmod_class,
965 	.main_clk	= "sr1_fck",
966 	.prcm		= {
967 		.omap2 = {
968 			.module_offs = WKUP_MOD,
969 			.idlest_reg_id = 1,
970 			.idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
971 		},
972 	},
973 	.dev_attr	= &sr1_dev_attr,
974 	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
975 };
976 
977 static struct omap_hwmod omap36xx_sr1_hwmod = {
978 	.name		= "smartreflex_mpu_iva",
979 	.class		= &omap36xx_smartreflex_hwmod_class,
980 	.main_clk	= "sr1_fck",
981 	.prcm		= {
982 		.omap2 = {
983 			.module_offs = WKUP_MOD,
984 			.idlest_reg_id = 1,
985 			.idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
986 		},
987 	},
988 	.dev_attr	= &sr1_dev_attr,
989 };
990 
991 /* SR2 */
992 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
993 	.sensor_voltdm_name	= "core",
994 };
995 
996 
997 static struct omap_hwmod omap34xx_sr2_hwmod = {
998 	.name		= "smartreflex_core",
999 	.class		= &omap34xx_smartreflex_hwmod_class,
1000 	.main_clk	= "sr2_fck",
1001 	.prcm		= {
1002 		.omap2 = {
1003 			.module_offs = WKUP_MOD,
1004 			.idlest_reg_id = 1,
1005 			.idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1006 		},
1007 	},
1008 	.dev_attr	= &sr2_dev_attr,
1009 	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
1010 };
1011 
1012 static struct omap_hwmod omap36xx_sr2_hwmod = {
1013 	.name		= "smartreflex_core",
1014 	.class		= &omap36xx_smartreflex_hwmod_class,
1015 	.main_clk	= "sr2_fck",
1016 	.prcm		= {
1017 		.omap2 = {
1018 			.module_offs = WKUP_MOD,
1019 			.idlest_reg_id = 1,
1020 			.idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1021 		},
1022 	},
1023 	.dev_attr	= &sr2_dev_attr,
1024 };
1025 
1026 /*
1027  * 'mailbox' class
1028  * mailbox module allowing communication between the on-chip processors
1029  * using a queued mailbox-interrupt mechanism.
1030  */
1031 
1032 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1033 	.rev_offs	= 0x000,
1034 	.sysc_offs	= 0x010,
1035 	.syss_offs	= 0x014,
1036 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1037 				SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1038 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1039 	.sysc_fields	= &omap_hwmod_sysc_type1,
1040 };
1041 
1042 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1043 	.name = "mailbox",
1044 	.sysc = &omap3xxx_mailbox_sysc,
1045 };
1046 
1047 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1048 	.name		= "mailbox",
1049 	.class		= &omap3xxx_mailbox_hwmod_class,
1050 	.main_clk	= "mailboxes_ick",
1051 	.prcm		= {
1052 		.omap2 = {
1053 			.module_offs = CORE_MOD,
1054 			.idlest_reg_id = 1,
1055 			.idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1056 		},
1057 	},
1058 };
1059 
1060 /*
1061  * 'mcspi' class
1062  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1063  * bus
1064  */
1065 
1066 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1067 	.rev_offs	= 0x0000,
1068 	.sysc_offs	= 0x0010,
1069 	.syss_offs	= 0x0014,
1070 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1071 				SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1072 				SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1073 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1074 	.sysc_fields    = &omap_hwmod_sysc_type1,
1075 };
1076 
1077 static struct omap_hwmod_class omap34xx_mcspi_class = {
1078 	.name = "mcspi",
1079 	.sysc = &omap34xx_mcspi_sysc,
1080 };
1081 
1082 /* mcspi1 */
1083 static struct omap_hwmod omap34xx_mcspi1 = {
1084 	.name		= "mcspi1",
1085 	.main_clk	= "mcspi1_fck",
1086 	.prcm		= {
1087 		.omap2 = {
1088 			.module_offs = CORE_MOD,
1089 			.idlest_reg_id = 1,
1090 			.idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1091 		},
1092 	},
1093 	.class		= &omap34xx_mcspi_class,
1094 };
1095 
1096 /* mcspi2 */
1097 static struct omap_hwmod omap34xx_mcspi2 = {
1098 	.name		= "mcspi2",
1099 	.main_clk	= "mcspi2_fck",
1100 	.prcm		= {
1101 		.omap2 = {
1102 			.module_offs = CORE_MOD,
1103 			.idlest_reg_id = 1,
1104 			.idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1105 		},
1106 	},
1107 	.class		= &omap34xx_mcspi_class,
1108 };
1109 
1110 /* mcspi3 */
1111 static struct omap_hwmod omap34xx_mcspi3 = {
1112 	.name		= "mcspi3",
1113 	.main_clk	= "mcspi3_fck",
1114 	.prcm		= {
1115 		.omap2 = {
1116 			.module_offs = CORE_MOD,
1117 			.idlest_reg_id = 1,
1118 			.idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1119 		},
1120 	},
1121 	.class		= &omap34xx_mcspi_class,
1122 };
1123 
1124 /* mcspi4 */
1125 static struct omap_hwmod omap34xx_mcspi4 = {
1126 	.name		= "mcspi4",
1127 	.main_clk	= "mcspi4_fck",
1128 	.prcm		= {
1129 		.omap2 = {
1130 			.module_offs = CORE_MOD,
1131 			.idlest_reg_id = 1,
1132 			.idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1133 		},
1134 	},
1135 	.class		= &omap34xx_mcspi_class,
1136 };
1137 
1138 /* usbhsotg */
1139 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1140 	.rev_offs	= 0x0400,
1141 	.sysc_offs	= 0x0404,
1142 	.syss_offs	= 0x0408,
1143 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1144 			  SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1145 			  SYSC_HAS_AUTOIDLE),
1146 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1147 			  MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1148 	.sysc_fields	= &omap_hwmod_sysc_type1,
1149 };
1150 
1151 static struct omap_hwmod_class usbotg_class = {
1152 	.name = "usbotg",
1153 	.sysc = &omap3xxx_usbhsotg_sysc,
1154 };
1155 
1156 /* usb_otg_hs */
1157 
1158 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1159 	.name		= "usb_otg_hs",
1160 	.main_clk	= "hsotgusb_ick",
1161 	.prcm		= {
1162 		.omap2 = {
1163 			.module_offs = CORE_MOD,
1164 			.idlest_reg_id = 1,
1165 			.idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1166 		},
1167 	},
1168 	.class		= &usbotg_class,
1169 
1170 	/*
1171 	 * Erratum ID: i479  idle_req / idle_ack mechanism potentially
1172 	 * broken when autoidle is enabled
1173 	 * workaround is to disable the autoidle bit at module level.
1174 	 *
1175 	 * Enabling the device in any other MIDLEMODE setting but force-idle
1176 	 * causes core_pwrdm not enter idle states at least on OMAP3630.
1177 	 * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY
1178 	 * signal when MIDLEMODE is set to force-idle.
1179 	 */
1180 	.flags		= HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE |
1181 			  HWMOD_FORCE_MSTANDBY | HWMOD_RECONFIG_IO_CHAIN,
1182 };
1183 
1184 /* usb_otg_hs */
1185 
1186 static struct omap_hwmod_class am35xx_usbotg_class = {
1187 	.name = "am35xx_usbotg",
1188 };
1189 
1190 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1191 	.name		= "am35x_otg_hs",
1192 	.main_clk	= "hsotgusb_fck",
1193 	.class		= &am35xx_usbotg_class,
1194 	.flags		= HWMOD_NO_IDLEST,
1195 };
1196 
1197 /* MMC/SD/SDIO common */
1198 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1199 	.rev_offs	= 0x1fc,
1200 	.sysc_offs	= 0x10,
1201 	.syss_offs	= 0x14,
1202 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1203 			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1204 			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1205 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1206 	.sysc_fields    = &omap_hwmod_sysc_type1,
1207 };
1208 
1209 static struct omap_hwmod_class omap34xx_mmc_class = {
1210 	.name = "mmc",
1211 	.sysc = &omap34xx_mmc_sysc,
1212 };
1213 
1214 /* MMC/SD/SDIO1 */
1215 
1216 
1217 
1218 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1219 	{ .role = "dbck", .clk = "omap_32k_fck", },
1220 };
1221 
1222 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1223 	.flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1224 };
1225 
1226 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1227 static struct omap_hsmmc_dev_attr mmc1_pre_es3_dev_attr = {
1228 	.flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1229 		  OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1230 };
1231 
1232 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1233 	.name		= "mmc1",
1234 	.opt_clks	= omap34xx_mmc1_opt_clks,
1235 	.opt_clks_cnt	= ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1236 	.main_clk	= "mmchs1_fck",
1237 	.prcm		= {
1238 		.omap2 = {
1239 			.module_offs = CORE_MOD,
1240 			.idlest_reg_id = 1,
1241 			.idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1242 		},
1243 	},
1244 	.dev_attr	= &mmc1_pre_es3_dev_attr,
1245 	.class		= &omap34xx_mmc_class,
1246 };
1247 
1248 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1249 	.name		= "mmc1",
1250 	.opt_clks	= omap34xx_mmc1_opt_clks,
1251 	.opt_clks_cnt	= ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1252 	.main_clk	= "mmchs1_fck",
1253 	.prcm		= {
1254 		.omap2 = {
1255 			.module_offs = CORE_MOD,
1256 			.idlest_reg_id = 1,
1257 			.idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1258 		},
1259 	},
1260 	.dev_attr	= &mmc1_dev_attr,
1261 	.class		= &omap34xx_mmc_class,
1262 };
1263 
1264 /* MMC/SD/SDIO2 */
1265 
1266 
1267 
1268 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1269 	{ .role = "dbck", .clk = "omap_32k_fck", },
1270 };
1271 
1272 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1273 static struct omap_hsmmc_dev_attr mmc2_pre_es3_dev_attr = {
1274 	.flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1275 };
1276 
1277 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1278 	.name		= "mmc2",
1279 	.opt_clks	= omap34xx_mmc2_opt_clks,
1280 	.opt_clks_cnt	= ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1281 	.main_clk	= "mmchs2_fck",
1282 	.prcm		= {
1283 		.omap2 = {
1284 			.module_offs = CORE_MOD,
1285 			.idlest_reg_id = 1,
1286 			.idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1287 		},
1288 	},
1289 	.dev_attr	= &mmc2_pre_es3_dev_attr,
1290 	.class		= &omap34xx_mmc_class,
1291 };
1292 
1293 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1294 	.name		= "mmc2",
1295 	.opt_clks	= omap34xx_mmc2_opt_clks,
1296 	.opt_clks_cnt	= ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1297 	.main_clk	= "mmchs2_fck",
1298 	.prcm		= {
1299 		.omap2 = {
1300 			.module_offs = CORE_MOD,
1301 			.idlest_reg_id = 1,
1302 			.idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1303 		},
1304 	},
1305 	.class		= &omap34xx_mmc_class,
1306 };
1307 
1308 /* MMC/SD/SDIO3 */
1309 
1310 
1311 
1312 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1313 	{ .role = "dbck", .clk = "omap_32k_fck", },
1314 };
1315 
1316 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1317 	.name		= "mmc3",
1318 	.opt_clks	= omap34xx_mmc3_opt_clks,
1319 	.opt_clks_cnt	= ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1320 	.main_clk	= "mmchs3_fck",
1321 	.prcm		= {
1322 		.omap2 = {
1323 			.module_offs = CORE_MOD,
1324 			.idlest_reg_id = 1,
1325 			.idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1326 		},
1327 	},
1328 	.class		= &omap34xx_mmc_class,
1329 };
1330 
1331 /*
1332  * 'usb_host_hs' class
1333  * high-speed multi-port usb host controller
1334  */
1335 
1336 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1337 	.rev_offs	= 0x0000,
1338 	.sysc_offs	= 0x0010,
1339 	.syss_offs	= 0x0014,
1340 	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1341 			   SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1342 			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1343 			   SYSS_HAS_RESET_STATUS),
1344 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1345 			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1346 	.sysc_fields	= &omap_hwmod_sysc_type1,
1347 };
1348 
1349 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1350 	.name = "usb_host_hs",
1351 	.sysc = &omap3xxx_usb_host_hs_sysc,
1352 };
1353 
1354 
1355 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1356 	.name		= "usb_host_hs",
1357 	.class		= &omap3xxx_usb_host_hs_hwmod_class,
1358 	.clkdm_name	= "usbhost_clkdm",
1359 	.main_clk	= "usbhost_48m_fck",
1360 	.prcm = {
1361 		.omap2 = {
1362 			.module_offs = OMAP3430ES2_USBHOST_MOD,
1363 			.idlest_reg_id = 1,
1364 			.idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1365 		},
1366 	},
1367 
1368 	/*
1369 	 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1370 	 * id: i660
1371 	 *
1372 	 * Description:
1373 	 * In the following configuration :
1374 	 * - USBHOST module is set to smart-idle mode
1375 	 * - PRCM asserts idle_req to the USBHOST module ( This typically
1376 	 *   happens when the system is going to a low power mode : all ports
1377 	 *   have been suspended, the master part of the USBHOST module has
1378 	 *   entered the standby state, and SW has cut the functional clocks)
1379 	 * - an USBHOST interrupt occurs before the module is able to answer
1380 	 *   idle_ack, typically a remote wakeup IRQ.
1381 	 * Then the USB HOST module will enter a deadlock situation where it
1382 	 * is no more accessible nor functional.
1383 	 *
1384 	 * Workaround:
1385 	 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1386 	 */
1387 
1388 	/*
1389 	 * Errata: USB host EHCI may stall when entering smart-standby mode
1390 	 * Id: i571
1391 	 *
1392 	 * Description:
1393 	 * When the USBHOST module is set to smart-standby mode, and when it is
1394 	 * ready to enter the standby state (i.e. all ports are suspended and
1395 	 * all attached devices are in suspend mode), then it can wrongly assert
1396 	 * the Mstandby signal too early while there are still some residual OCP
1397 	 * transactions ongoing. If this condition occurs, the internal state
1398 	 * machine may go to an undefined state and the USB link may be stuck
1399 	 * upon the next resume.
1400 	 *
1401 	 * Workaround:
1402 	 * Don't use smart standby; use only force standby,
1403 	 * hence HWMOD_SWSUP_MSTANDBY
1404 	 */
1405 
1406 	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1407 };
1408 
1409 /*
1410  * 'usb_tll_hs' class
1411  * usb_tll_hs module is the adapter on the usb_host_hs ports
1412  */
1413 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
1414 	.rev_offs	= 0x0000,
1415 	.sysc_offs	= 0x0010,
1416 	.syss_offs	= 0x0014,
1417 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1418 			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1419 			   SYSC_HAS_AUTOIDLE),
1420 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1421 	.sysc_fields	= &omap_hwmod_sysc_type1,
1422 };
1423 
1424 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
1425 	.name = "usb_tll_hs",
1426 	.sysc = &omap3xxx_usb_tll_hs_sysc,
1427 };
1428 
1429 
1430 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
1431 	.name		= "usb_tll_hs",
1432 	.class		= &omap3xxx_usb_tll_hs_hwmod_class,
1433 	.clkdm_name	= "core_l4_clkdm",
1434 	.main_clk	= "usbtll_fck",
1435 	.prcm = {
1436 		.omap2 = {
1437 			.module_offs = CORE_MOD,
1438 			.idlest_reg_id = 3,
1439 			.idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
1440 		},
1441 	},
1442 };
1443 
1444 static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
1445 	.name		= "hdq1w",
1446 	.main_clk	= "hdq_fck",
1447 	.prcm		= {
1448 		.omap2 = {
1449 			.module_offs = CORE_MOD,
1450 			.idlest_reg_id = 1,
1451 			.idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
1452 		},
1453 	},
1454 	.class		= &omap2_hdq1w_class,
1455 };
1456 
1457 /* SAD2D */
1458 static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = {
1459 	{ .name = "rst_modem_pwron_sw", .rst_shift = 0 },
1460 	{ .name = "rst_modem_sw", .rst_shift = 1 },
1461 };
1462 
1463 static struct omap_hwmod_class omap3xxx_sad2d_class = {
1464 	.name			= "sad2d",
1465 };
1466 
1467 static struct omap_hwmod omap3xxx_sad2d_hwmod = {
1468 	.name		= "sad2d",
1469 	.rst_lines	= omap3xxx_sad2d_resets,
1470 	.rst_lines_cnt	= ARRAY_SIZE(omap3xxx_sad2d_resets),
1471 	.main_clk	= "sad2d_ick",
1472 	.prcm		= {
1473 		.omap2 = {
1474 			.module_offs = CORE_MOD,
1475 			.idlest_reg_id = 1,
1476 			.idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT,
1477 		},
1478 	},
1479 	.class		= &omap3xxx_sad2d_class,
1480 };
1481 
1482 /*
1483  * 'gpmc' class
1484  * general purpose memory controller
1485  */
1486 
1487 static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
1488 	.rev_offs	= 0x0000,
1489 	.sysc_offs	= 0x0010,
1490 	.syss_offs	= 0x0014,
1491 	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1492 			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1493 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1494 	.sysc_fields	= &omap_hwmod_sysc_type1,
1495 };
1496 
1497 static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
1498 	.name	= "gpmc",
1499 	.sysc	= &omap3xxx_gpmc_sysc,
1500 };
1501 
1502 static struct omap_hwmod omap3xxx_gpmc_hwmod = {
1503 	.name		= "gpmc",
1504 	.class		= &omap3xxx_gpmc_hwmod_class,
1505 	.clkdm_name	= "core_l3_clkdm",
1506 	.main_clk	= "gpmc_fck",
1507 	/* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
1508 	.flags		= HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
1509 };
1510 
1511 /*
1512  * interfaces
1513  */
1514 
1515 /* L3 -> L4_CORE interface */
1516 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
1517 	.master	= &omap3xxx_l3_main_hwmod,
1518 	.slave	= &omap3xxx_l4_core_hwmod,
1519 	.user	= OCP_USER_MPU | OCP_USER_SDMA,
1520 };
1521 
1522 /* L3 -> L4_PER interface */
1523 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
1524 	.master = &omap3xxx_l3_main_hwmod,
1525 	.slave	= &omap3xxx_l4_per_hwmod,
1526 	.user	= OCP_USER_MPU | OCP_USER_SDMA,
1527 };
1528 
1529 
1530 /* MPU -> L3 interface */
1531 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
1532 	.master   = &omap3xxx_mpu_hwmod,
1533 	.slave    = &omap3xxx_l3_main_hwmod,
1534 	.user	= OCP_USER_MPU,
1535 };
1536 
1537 
1538 /* l3 -> debugss */
1539 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
1540 	.master		= &omap3xxx_l3_main_hwmod,
1541 	.slave		= &omap3xxx_debugss_hwmod,
1542 	.user		= OCP_USER_MPU,
1543 };
1544 
1545 /* DSS -> l3 */
1546 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
1547 	.master		= &omap3430es1_dss_core_hwmod,
1548 	.slave		= &omap3xxx_l3_main_hwmod,
1549 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1550 };
1551 
1552 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
1553 	.master		= &omap3xxx_dss_core_hwmod,
1554 	.slave		= &omap3xxx_l3_main_hwmod,
1555 	.fw = {
1556 		.omap2 = {
1557 			.l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
1558 			.flags	= OMAP_FIREWALL_L3,
1559 		},
1560 	},
1561 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1562 };
1563 
1564 /* l3_core -> usbhsotg interface */
1565 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
1566 	.master		= &omap3xxx_usbhsotg_hwmod,
1567 	.slave		= &omap3xxx_l3_main_hwmod,
1568 	.clk		= "core_l3_ick",
1569 	.user		= OCP_USER_MPU,
1570 };
1571 
1572 /* l3_core -> am35xx_usbhsotg interface */
1573 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
1574 	.master		= &am35xx_usbhsotg_hwmod,
1575 	.slave		= &omap3xxx_l3_main_hwmod,
1576 	.clk		= "hsotgusb_ick",
1577 	.user		= OCP_USER_MPU,
1578 };
1579 
1580 /* l3_core -> sad2d interface */
1581 static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = {
1582 	.master		= &omap3xxx_sad2d_hwmod,
1583 	.slave		= &omap3xxx_l3_main_hwmod,
1584 	.clk		= "core_l3_ick",
1585 	.user		= OCP_USER_MPU,
1586 };
1587 
1588 /* L4_CORE -> L4_WKUP interface */
1589 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
1590 	.master	= &omap3xxx_l4_core_hwmod,
1591 	.slave	= &omap3xxx_l4_wkup_hwmod,
1592 	.user	= OCP_USER_MPU | OCP_USER_SDMA,
1593 };
1594 
1595 /* L4 CORE -> MMC1 interface */
1596 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
1597 	.master		= &omap3xxx_l4_core_hwmod,
1598 	.slave		= &omap3xxx_pre_es3_mmc1_hwmod,
1599 	.clk		= "mmchs1_ick",
1600 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1601 	.flags		= OMAP_FIREWALL_L4,
1602 };
1603 
1604 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
1605 	.master		= &omap3xxx_l4_core_hwmod,
1606 	.slave		= &omap3xxx_es3plus_mmc1_hwmod,
1607 	.clk		= "mmchs1_ick",
1608 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1609 	.flags		= OMAP_FIREWALL_L4,
1610 };
1611 
1612 /* L4 CORE -> MMC2 interface */
1613 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
1614 	.master		= &omap3xxx_l4_core_hwmod,
1615 	.slave		= &omap3xxx_pre_es3_mmc2_hwmod,
1616 	.clk		= "mmchs2_ick",
1617 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1618 	.flags		= OMAP_FIREWALL_L4,
1619 };
1620 
1621 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
1622 	.master		= &omap3xxx_l4_core_hwmod,
1623 	.slave		= &omap3xxx_es3plus_mmc2_hwmod,
1624 	.clk		= "mmchs2_ick",
1625 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1626 	.flags		= OMAP_FIREWALL_L4,
1627 };
1628 
1629 /* L4 CORE -> MMC3 interface */
1630 
1631 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
1632 	.master		= &omap3xxx_l4_core_hwmod,
1633 	.slave		= &omap3xxx_mmc3_hwmod,
1634 	.clk		= "mmchs3_ick",
1635 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1636 	.flags		= OMAP_FIREWALL_L4,
1637 };
1638 
1639 /* L4 CORE -> UART1 interface */
1640 
1641 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
1642 	.master		= &omap3xxx_l4_core_hwmod,
1643 	.slave		= &omap3xxx_uart1_hwmod,
1644 	.clk		= "uart1_ick",
1645 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1646 };
1647 
1648 /* L4 CORE -> UART2 interface */
1649 
1650 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
1651 	.master		= &omap3xxx_l4_core_hwmod,
1652 	.slave		= &omap3xxx_uart2_hwmod,
1653 	.clk		= "uart2_ick",
1654 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1655 };
1656 
1657 /* L4 PER -> UART3 interface */
1658 
1659 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
1660 	.master		= &omap3xxx_l4_per_hwmod,
1661 	.slave		= &omap3xxx_uart3_hwmod,
1662 	.clk		= "uart3_ick",
1663 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1664 };
1665 
1666 /* L4 PER -> UART4 interface */
1667 
1668 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
1669 	.master		= &omap3xxx_l4_per_hwmod,
1670 	.slave		= &omap36xx_uart4_hwmod,
1671 	.clk		= "uart4_ick",
1672 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1673 };
1674 
1675 /* AM35xx: L4 CORE -> UART4 interface */
1676 
1677 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
1678 	.master		= &omap3xxx_l4_core_hwmod,
1679 	.slave		= &am35xx_uart4_hwmod,
1680 	.clk		= "uart4_ick",
1681 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1682 };
1683 
1684 /* L4 CORE -> I2C1 interface */
1685 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
1686 	.master		= &omap3xxx_l4_core_hwmod,
1687 	.slave		= &omap3xxx_i2c1_hwmod,
1688 	.clk		= "i2c1_ick",
1689 	.fw = {
1690 		.omap2 = {
1691 			.l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
1692 			.l4_prot_group = 7,
1693 			.flags	= OMAP_FIREWALL_L4,
1694 		},
1695 	},
1696 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1697 };
1698 
1699 /* L4 CORE -> I2C2 interface */
1700 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
1701 	.master		= &omap3xxx_l4_core_hwmod,
1702 	.slave		= &omap3xxx_i2c2_hwmod,
1703 	.clk		= "i2c2_ick",
1704 	.fw = {
1705 		.omap2 = {
1706 			.l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
1707 			.l4_prot_group = 7,
1708 			.flags = OMAP_FIREWALL_L4,
1709 		},
1710 	},
1711 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1712 };
1713 
1714 /* L4 CORE -> I2C3 interface */
1715 
1716 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
1717 	.master		= &omap3xxx_l4_core_hwmod,
1718 	.slave		= &omap3xxx_i2c3_hwmod,
1719 	.clk		= "i2c3_ick",
1720 	.fw = {
1721 		.omap2 = {
1722 			.l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
1723 			.l4_prot_group = 7,
1724 			.flags = OMAP_FIREWALL_L4,
1725 		},
1726 	},
1727 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1728 };
1729 
1730 /* L4 CORE -> SR1 interface */
1731 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
1732 	.master		= &omap3xxx_l4_core_hwmod,
1733 	.slave		= &omap34xx_sr1_hwmod,
1734 	.clk		= "sr_l4_ick",
1735 	.user		= OCP_USER_MPU,
1736 };
1737 
1738 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
1739 	.master		= &omap3xxx_l4_core_hwmod,
1740 	.slave		= &omap36xx_sr1_hwmod,
1741 	.clk		= "sr_l4_ick",
1742 	.user		= OCP_USER_MPU,
1743 };
1744 
1745 /* L4 CORE -> SR2 interface */
1746 
1747 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
1748 	.master		= &omap3xxx_l4_core_hwmod,
1749 	.slave		= &omap34xx_sr2_hwmod,
1750 	.clk		= "sr_l4_ick",
1751 	.user		= OCP_USER_MPU,
1752 };
1753 
1754 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
1755 	.master		= &omap3xxx_l4_core_hwmod,
1756 	.slave		= &omap36xx_sr2_hwmod,
1757 	.clk		= "sr_l4_ick",
1758 	.user		= OCP_USER_MPU,
1759 };
1760 
1761 
1762 /* l4_core -> usbhsotg  */
1763 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
1764 	.master		= &omap3xxx_l4_core_hwmod,
1765 	.slave		= &omap3xxx_usbhsotg_hwmod,
1766 	.clk		= "l4_ick",
1767 	.user		= OCP_USER_MPU,
1768 };
1769 
1770 
1771 /* l4_core -> usbhsotg  */
1772 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
1773 	.master		= &omap3xxx_l4_core_hwmod,
1774 	.slave		= &am35xx_usbhsotg_hwmod,
1775 	.clk		= "hsotgusb_ick",
1776 	.user		= OCP_USER_MPU,
1777 };
1778 
1779 /* L4_WKUP -> L4_SEC interface */
1780 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
1781 	.master = &omap3xxx_l4_wkup_hwmod,
1782 	.slave	= &omap3xxx_l4_sec_hwmod,
1783 	.user	= OCP_USER_MPU | OCP_USER_SDMA,
1784 };
1785 
1786 /* IVA2 <- L3 interface */
1787 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
1788 	.master		= &omap3xxx_l3_main_hwmod,
1789 	.slave		= &omap3xxx_iva_hwmod,
1790 	.clk		= "core_l3_ick",
1791 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1792 };
1793 
1794 /* l4_per -> timer3 */
1795 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
1796 	.master		= &omap3xxx_l4_per_hwmod,
1797 	.slave		= &omap3xxx_timer3_hwmod,
1798 	.clk		= "gpt3_ick",
1799 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1800 };
1801 
1802 
1803 /* l4_per -> timer4 */
1804 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
1805 	.master		= &omap3xxx_l4_per_hwmod,
1806 	.slave		= &omap3xxx_timer4_hwmod,
1807 	.clk		= "gpt4_ick",
1808 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1809 };
1810 
1811 
1812 /* l4_per -> timer5 */
1813 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
1814 	.master		= &omap3xxx_l4_per_hwmod,
1815 	.slave		= &omap3xxx_timer5_hwmod,
1816 	.clk		= "gpt5_ick",
1817 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1818 };
1819 
1820 
1821 /* l4_per -> timer6 */
1822 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
1823 	.master		= &omap3xxx_l4_per_hwmod,
1824 	.slave		= &omap3xxx_timer6_hwmod,
1825 	.clk		= "gpt6_ick",
1826 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1827 };
1828 
1829 
1830 /* l4_per -> timer7 */
1831 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
1832 	.master		= &omap3xxx_l4_per_hwmod,
1833 	.slave		= &omap3xxx_timer7_hwmod,
1834 	.clk		= "gpt7_ick",
1835 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1836 };
1837 
1838 
1839 /* l4_per -> timer8 */
1840 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
1841 	.master		= &omap3xxx_l4_per_hwmod,
1842 	.slave		= &omap3xxx_timer8_hwmod,
1843 	.clk		= "gpt8_ick",
1844 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1845 };
1846 
1847 
1848 /* l4_per -> timer9 */
1849 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
1850 	.master		= &omap3xxx_l4_per_hwmod,
1851 	.slave		= &omap3xxx_timer9_hwmod,
1852 	.clk		= "gpt9_ick",
1853 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1854 };
1855 
1856 /* l4_core -> timer10 */
1857 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1858 	.master		= &omap3xxx_l4_core_hwmod,
1859 	.slave		= &omap3xxx_timer10_hwmod,
1860 	.clk		= "gpt10_ick",
1861 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1862 };
1863 
1864 /* l4_core -> timer11 */
1865 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1866 	.master		= &omap3xxx_l4_core_hwmod,
1867 	.slave		= &omap3xxx_timer11_hwmod,
1868 	.clk		= "gpt11_ick",
1869 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1870 };
1871 
1872 /* l4_wkup -> wd_timer2 */
1873 
1874 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1875 	.master		= &omap3xxx_l4_wkup_hwmod,
1876 	.slave		= &omap3xxx_wd_timer2_hwmod,
1877 	.clk		= "wdt2_ick",
1878 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1879 };
1880 
1881 /* l4_core -> dss */
1882 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1883 	.master		= &omap3xxx_l4_core_hwmod,
1884 	.slave		= &omap3430es1_dss_core_hwmod,
1885 	.clk		= "dss_ick",
1886 	.fw = {
1887 		.omap2 = {
1888 			.l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1889 			.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1890 			.flags	= OMAP_FIREWALL_L4,
1891 		},
1892 	},
1893 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1894 };
1895 
1896 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1897 	.master		= &omap3xxx_l4_core_hwmod,
1898 	.slave		= &omap3xxx_dss_core_hwmod,
1899 	.clk		= "dss_ick",
1900 	.fw = {
1901 		.omap2 = {
1902 			.l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1903 			.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1904 			.flags	= OMAP_FIREWALL_L4,
1905 		},
1906 	},
1907 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1908 };
1909 
1910 /* l4_core -> dss_dispc */
1911 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1912 	.master		= &omap3xxx_l4_core_hwmod,
1913 	.slave		= &omap3xxx_dss_dispc_hwmod,
1914 	.clk		= "dss_ick",
1915 	.fw = {
1916 		.omap2 = {
1917 			.l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1918 			.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1919 			.flags	= OMAP_FIREWALL_L4,
1920 		},
1921 	},
1922 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1923 };
1924 
1925 /* l4_core -> dss_dsi1 */
1926 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1927 	.master		= &omap3xxx_l4_core_hwmod,
1928 	.slave		= &omap3xxx_dss_dsi1_hwmod,
1929 	.clk		= "dss_ick",
1930 	.fw = {
1931 		.omap2 = {
1932 			.l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1933 			.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1934 			.flags	= OMAP_FIREWALL_L4,
1935 		},
1936 	},
1937 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1938 };
1939 
1940 /* l4_core -> dss_rfbi */
1941 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1942 	.master		= &omap3xxx_l4_core_hwmod,
1943 	.slave		= &omap3xxx_dss_rfbi_hwmod,
1944 	.clk		= "dss_ick",
1945 	.fw = {
1946 		.omap2 = {
1947 			.l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1948 			.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1949 			.flags	= OMAP_FIREWALL_L4,
1950 		},
1951 	},
1952 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1953 };
1954 
1955 /* l4_core -> dss_venc */
1956 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1957 	.master		= &omap3xxx_l4_core_hwmod,
1958 	.slave		= &omap3xxx_dss_venc_hwmod,
1959 	.clk		= "dss_ick",
1960 	.fw = {
1961 		.omap2 = {
1962 			.l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1963 			.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1964 			.flags	= OMAP_FIREWALL_L4,
1965 		},
1966 	},
1967 	.flags		= OCPIF_SWSUP_IDLE,
1968 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1969 };
1970 
1971 /* l4_wkup -> gpio1 */
1972 
1973 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1974 	.master		= &omap3xxx_l4_wkup_hwmod,
1975 	.slave		= &omap3xxx_gpio1_hwmod,
1976 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1977 };
1978 
1979 /* l4_per -> gpio2 */
1980 
1981 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1982 	.master		= &omap3xxx_l4_per_hwmod,
1983 	.slave		= &omap3xxx_gpio2_hwmod,
1984 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1985 };
1986 
1987 /* l4_per -> gpio3 */
1988 
1989 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1990 	.master		= &omap3xxx_l4_per_hwmod,
1991 	.slave		= &omap3xxx_gpio3_hwmod,
1992 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1993 };
1994 
1995 /*
1996  * 'mmu' class
1997  * The memory management unit performs virtual to physical address translation
1998  * for its requestors.
1999  */
2000 
2001 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2002 	.rev_offs	= 0x000,
2003 	.sysc_offs	= 0x010,
2004 	.syss_offs	= 0x014,
2005 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2006 			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2007 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2008 	.sysc_fields	= &omap_hwmod_sysc_type1,
2009 };
2010 
2011 static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
2012 	.name = "mmu",
2013 	.sysc = &mmu_sysc,
2014 };
2015 
2016 /* mmu isp */
2017 static struct omap_hwmod omap3xxx_mmu_isp_hwmod;
2018 
2019 /* l4_core -> mmu isp */
2020 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = {
2021 	.master		= &omap3xxx_l4_core_hwmod,
2022 	.slave		= &omap3xxx_mmu_isp_hwmod,
2023 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2024 };
2025 
2026 static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
2027 	.name		= "mmu_isp",
2028 	.class		= &omap3xxx_mmu_hwmod_class,
2029 	.main_clk	= "cam_ick",
2030 	.flags		= HWMOD_NO_IDLEST,
2031 };
2032 
2033 /* mmu iva */
2034 
2035 static struct omap_hwmod omap3xxx_mmu_iva_hwmod;
2036 
2037 static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = {
2038 	{ .name = "mmu", .rst_shift = 1, .st_shift = 9 },
2039 };
2040 
2041 /* l3_main -> iva mmu */
2042 static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = {
2043 	.master		= &omap3xxx_l3_main_hwmod,
2044 	.slave		= &omap3xxx_mmu_iva_hwmod,
2045 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2046 };
2047 
2048 static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
2049 	.name		= "mmu_iva",
2050 	.class		= &omap3xxx_mmu_hwmod_class,
2051 	.clkdm_name	= "iva2_clkdm",
2052 	.rst_lines	= omap3xxx_mmu_iva_resets,
2053 	.rst_lines_cnt	= ARRAY_SIZE(omap3xxx_mmu_iva_resets),
2054 	.main_clk	= "iva2_ck",
2055 	.prcm = {
2056 		.omap2 = {
2057 			.module_offs = OMAP3430_IVA2_MOD,
2058 			.idlest_reg_id = 1,
2059 			.idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
2060 		},
2061 	},
2062 	.flags		= HWMOD_NO_IDLEST,
2063 };
2064 
2065 /* l4_per -> gpio4 */
2066 
2067 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
2068 	.master		= &omap3xxx_l4_per_hwmod,
2069 	.slave		= &omap3xxx_gpio4_hwmod,
2070 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2071 };
2072 
2073 /* l4_per -> gpio5 */
2074 
2075 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
2076 	.master		= &omap3xxx_l4_per_hwmod,
2077 	.slave		= &omap3xxx_gpio5_hwmod,
2078 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2079 };
2080 
2081 /* l4_per -> gpio6 */
2082 
2083 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2084 	.master		= &omap3xxx_l4_per_hwmod,
2085 	.slave		= &omap3xxx_gpio6_hwmod,
2086 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2087 };
2088 
2089 /* l4_core -> mcbsp1 */
2090 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2091 	.master		= &omap3xxx_l4_core_hwmod,
2092 	.slave		= &omap3xxx_mcbsp1_hwmod,
2093 	.clk		= "mcbsp1_ick",
2094 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2095 };
2096 
2097 
2098 /* l4_per -> mcbsp2 */
2099 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2100 	.master		= &omap3xxx_l4_per_hwmod,
2101 	.slave		= &omap3xxx_mcbsp2_hwmod,
2102 	.clk		= "mcbsp2_ick",
2103 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2104 };
2105 
2106 
2107 /* l4_per -> mcbsp3 */
2108 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2109 	.master		= &omap3xxx_l4_per_hwmod,
2110 	.slave		= &omap3xxx_mcbsp3_hwmod,
2111 	.clk		= "mcbsp3_ick",
2112 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2113 };
2114 
2115 
2116 /* l4_per -> mcbsp4 */
2117 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2118 	.master		= &omap3xxx_l4_per_hwmod,
2119 	.slave		= &omap3xxx_mcbsp4_hwmod,
2120 	.clk		= "mcbsp4_ick",
2121 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2122 };
2123 
2124 
2125 /* l4_core -> mcbsp5 */
2126 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2127 	.master		= &omap3xxx_l4_core_hwmod,
2128 	.slave		= &omap3xxx_mcbsp5_hwmod,
2129 	.clk		= "mcbsp5_ick",
2130 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2131 };
2132 
2133 
2134 /* l4_per -> mcbsp2_sidetone */
2135 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2136 	.master		= &omap3xxx_l4_per_hwmod,
2137 	.slave		= &omap3xxx_mcbsp2_sidetone_hwmod,
2138 	.clk		= "mcbsp2_ick",
2139 	.user		= OCP_USER_MPU,
2140 };
2141 
2142 
2143 /* l4_per -> mcbsp3_sidetone */
2144 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2145 	.master		= &omap3xxx_l4_per_hwmod,
2146 	.slave		= &omap3xxx_mcbsp3_sidetone_hwmod,
2147 	.clk		= "mcbsp3_ick",
2148 	.user		= OCP_USER_MPU,
2149 };
2150 
2151 /* l4_core -> mailbox */
2152 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2153 	.master		= &omap3xxx_l4_core_hwmod,
2154 	.slave		= &omap3xxx_mailbox_hwmod,
2155 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2156 };
2157 
2158 /* l4 core -> mcspi1 interface */
2159 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2160 	.master		= &omap3xxx_l4_core_hwmod,
2161 	.slave		= &omap34xx_mcspi1,
2162 	.clk		= "mcspi1_ick",
2163 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2164 };
2165 
2166 /* l4 core -> mcspi2 interface */
2167 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2168 	.master		= &omap3xxx_l4_core_hwmod,
2169 	.slave		= &omap34xx_mcspi2,
2170 	.clk		= "mcspi2_ick",
2171 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2172 };
2173 
2174 /* l4 core -> mcspi3 interface */
2175 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2176 	.master		= &omap3xxx_l4_core_hwmod,
2177 	.slave		= &omap34xx_mcspi3,
2178 	.clk		= "mcspi3_ick",
2179 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2180 };
2181 
2182 /* l4 core -> mcspi4 interface */
2183 
2184 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2185 	.master		= &omap3xxx_l4_core_hwmod,
2186 	.slave		= &omap34xx_mcspi4,
2187 	.clk		= "mcspi4_ick",
2188 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2189 };
2190 
2191 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
2192 	.master		= &omap3xxx_usb_host_hs_hwmod,
2193 	.slave		= &omap3xxx_l3_main_hwmod,
2194 	.clk		= "core_l3_ick",
2195 	.user		= OCP_USER_MPU,
2196 };
2197 
2198 
2199 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
2200 	.master		= &omap3xxx_l4_core_hwmod,
2201 	.slave		= &omap3xxx_usb_host_hs_hwmod,
2202 	.clk		= "usbhost_ick",
2203 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2204 };
2205 
2206 
2207 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
2208 	.master		= &omap3xxx_l4_core_hwmod,
2209 	.slave		= &omap3xxx_usb_tll_hs_hwmod,
2210 	.clk		= "usbtll_ick",
2211 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2212 };
2213 
2214 /* l4_core -> hdq1w interface */
2215 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
2216 	.master		= &omap3xxx_l4_core_hwmod,
2217 	.slave		= &omap3xxx_hdq1w_hwmod,
2218 	.clk		= "hdq_ick",
2219 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2220 	.flags		= OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
2221 };
2222 
2223 /* am35xx has Davinci MDIO & EMAC */
2224 static struct omap_hwmod_class am35xx_mdio_class = {
2225 	.name = "davinci_mdio",
2226 };
2227 
2228 static struct omap_hwmod am35xx_mdio_hwmod = {
2229 	.name		= "davinci_mdio",
2230 	.class		= &am35xx_mdio_class,
2231 	.flags		= HWMOD_NO_IDLEST,
2232 };
2233 
2234 /*
2235  * XXX Should be connected to an IPSS hwmod, not the L3 directly;
2236  * but this will probably require some additional hwmod core support,
2237  * so is left as a future to-do item.
2238  */
2239 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
2240 	.master		= &am35xx_mdio_hwmod,
2241 	.slave		= &omap3xxx_l3_main_hwmod,
2242 	.clk		= "emac_fck",
2243 	.user		= OCP_USER_MPU,
2244 };
2245 
2246 /* l4_core -> davinci mdio  */
2247 /*
2248  * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
2249  * but this will probably require some additional hwmod core support,
2250  * so is left as a future to-do item.
2251  */
2252 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
2253 	.master		= &omap3xxx_l4_core_hwmod,
2254 	.slave		= &am35xx_mdio_hwmod,
2255 	.clk		= "emac_fck",
2256 	.user		= OCP_USER_MPU,
2257 };
2258 
2259 static struct omap_hwmod_class am35xx_emac_class = {
2260 	.name = "davinci_emac",
2261 };
2262 
2263 static struct omap_hwmod am35xx_emac_hwmod = {
2264 	.name		= "davinci_emac",
2265 	.class		= &am35xx_emac_class,
2266 	/*
2267 	 * According to Mark Greer, the MPU will not return from WFI
2268 	 * when the EMAC signals an interrupt.
2269 	 * http://www.spinics.net/lists/arm-kernel/msg174734.html
2270 	 */
2271 	.flags		= (HWMOD_NO_IDLEST | HWMOD_BLOCK_WFI),
2272 };
2273 
2274 /* l3_core -> davinci emac interface */
2275 /*
2276  * XXX Should be connected to an IPSS hwmod, not the L3 directly;
2277  * but this will probably require some additional hwmod core support,
2278  * so is left as a future to-do item.
2279  */
2280 static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
2281 	.master		= &am35xx_emac_hwmod,
2282 	.slave		= &omap3xxx_l3_main_hwmod,
2283 	.clk		= "emac_ick",
2284 	.user		= OCP_USER_MPU,
2285 };
2286 
2287 /* l4_core -> davinci emac  */
2288 /*
2289  * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
2290  * but this will probably require some additional hwmod core support,
2291  * so is left as a future to-do item.
2292  */
2293 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
2294 	.master		= &omap3xxx_l4_core_hwmod,
2295 	.slave		= &am35xx_emac_hwmod,
2296 	.clk		= "emac_ick",
2297 	.user		= OCP_USER_MPU,
2298 };
2299 
2300 static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
2301 	.master		= &omap3xxx_l3_main_hwmod,
2302 	.slave		= &omap3xxx_gpmc_hwmod,
2303 	.clk		= "core_l3_ick",
2304 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2305 };
2306 
2307 /* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */
2308 static struct omap_hwmod_class_sysconfig omap3_sham_sysc = {
2309 	.rev_offs	= 0x5c,
2310 	.sysc_offs	= 0x60,
2311 	.syss_offs	= 0x64,
2312 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2313 			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2314 	.sysc_fields	= &omap3_sham_sysc_fields,
2315 };
2316 
2317 static struct omap_hwmod_class omap3xxx_sham_class = {
2318 	.name	= "sham",
2319 	.sysc	= &omap3_sham_sysc,
2320 };
2321 
2322 
2323 
2324 static struct omap_hwmod omap3xxx_sham_hwmod = {
2325 	.name		= "sham",
2326 	.main_clk	= "sha12_ick",
2327 	.prcm		= {
2328 		.omap2 = {
2329 			.module_offs = CORE_MOD,
2330 			.idlest_reg_id = 1,
2331 			.idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT,
2332 		},
2333 	},
2334 	.class		= &omap3xxx_sham_class,
2335 };
2336 
2337 
2338 static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
2339 	.master		= &omap3xxx_l4_core_hwmod,
2340 	.slave		= &omap3xxx_sham_hwmod,
2341 	.clk		= "sha12_ick",
2342 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2343 };
2344 
2345 /* l4_core -> AES */
2346 static struct omap_hwmod_class_sysconfig omap3_aes_sysc = {
2347 	.rev_offs	= 0x44,
2348 	.sysc_offs	= 0x48,
2349 	.syss_offs	= 0x4c,
2350 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2351 			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2352 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2353 	.sysc_fields	= &omap3xxx_aes_sysc_fields,
2354 };
2355 
2356 static struct omap_hwmod_class omap3xxx_aes_class = {
2357 	.name	= "aes",
2358 	.sysc	= &omap3_aes_sysc,
2359 };
2360 
2361 
2362 static struct omap_hwmod omap3xxx_aes_hwmod = {
2363 	.name		= "aes",
2364 	.main_clk	= "aes2_ick",
2365 	.prcm		= {
2366 		.omap2 = {
2367 			.module_offs = CORE_MOD,
2368 			.idlest_reg_id = 1,
2369 			.idlest_idle_bit = OMAP3430_ST_AES2_SHIFT,
2370 		},
2371 	},
2372 	.class		= &omap3xxx_aes_class,
2373 };
2374 
2375 
2376 static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = {
2377 	.master		= &omap3xxx_l4_core_hwmod,
2378 	.slave		= &omap3xxx_aes_hwmod,
2379 	.clk		= "aes2_ick",
2380 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2381 };
2382 
2383 /*
2384  * 'ssi' class
2385  * synchronous serial interface (multichannel and full-duplex serial if)
2386  */
2387 
2388 static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = {
2389 	.rev_offs	= 0x0000,
2390 	.sysc_offs	= 0x0010,
2391 	.syss_offs	= 0x0014,
2392 	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_MIDLEMODE |
2393 			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2394 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2395 	.sysc_fields	= &omap_hwmod_sysc_type1,
2396 };
2397 
2398 static struct omap_hwmod_class omap3xxx_ssi_hwmod_class = {
2399 	.name	= "ssi",
2400 	.sysc	= &omap34xx_ssi_sysc,
2401 };
2402 
2403 static struct omap_hwmod omap3xxx_ssi_hwmod = {
2404 	.name		= "ssi",
2405 	.class		= &omap3xxx_ssi_hwmod_class,
2406 	.clkdm_name	= "core_l4_clkdm",
2407 	.main_clk	= "ssi_ssr_fck",
2408 	.prcm		= {
2409 		.omap2 = {
2410 			.module_offs		= CORE_MOD,
2411 			.idlest_reg_id		= 1,
2412 			.idlest_idle_bit	= OMAP3430ES2_ST_SSI_IDLE_SHIFT,
2413 		},
2414 	},
2415 };
2416 
2417 /* L4 CORE -> SSI */
2418 static struct omap_hwmod_ocp_if omap3xxx_l4_core__ssi = {
2419 	.master		= &omap3xxx_l4_core_hwmod,
2420 	.slave		= &omap3xxx_ssi_hwmod,
2421 	.clk		= "ssi_ick",
2422 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2423 };
2424 
2425 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
2426 	&omap3xxx_l3_main__l4_core,
2427 	&omap3xxx_l3_main__l4_per,
2428 	&omap3xxx_mpu__l3_main,
2429 	&omap3xxx_l3_main__l4_debugss,
2430 	&omap3xxx_l4_core__l4_wkup,
2431 	&omap3xxx_l4_core__mmc3,
2432 	&omap3_l4_core__uart1,
2433 	&omap3_l4_core__uart2,
2434 	&omap3_l4_per__uart3,
2435 	&omap3_l4_core__i2c1,
2436 	&omap3_l4_core__i2c2,
2437 	&omap3_l4_core__i2c3,
2438 	&omap3xxx_l4_wkup__l4_sec,
2439 	&omap3xxx_l4_per__timer3,
2440 	&omap3xxx_l4_per__timer4,
2441 	&omap3xxx_l4_per__timer5,
2442 	&omap3xxx_l4_per__timer6,
2443 	&omap3xxx_l4_per__timer7,
2444 	&omap3xxx_l4_per__timer8,
2445 	&omap3xxx_l4_per__timer9,
2446 	&omap3xxx_l4_core__timer10,
2447 	&omap3xxx_l4_core__timer11,
2448 	&omap3xxx_l4_wkup__wd_timer2,
2449 	&omap3xxx_l4_wkup__gpio1,
2450 	&omap3xxx_l4_per__gpio2,
2451 	&omap3xxx_l4_per__gpio3,
2452 	&omap3xxx_l4_per__gpio4,
2453 	&omap3xxx_l4_per__gpio5,
2454 	&omap3xxx_l4_per__gpio6,
2455 	&omap3xxx_l4_core__mcbsp1,
2456 	&omap3xxx_l4_per__mcbsp2,
2457 	&omap3xxx_l4_per__mcbsp3,
2458 	&omap3xxx_l4_per__mcbsp4,
2459 	&omap3xxx_l4_core__mcbsp5,
2460 	&omap3xxx_l4_per__mcbsp2_sidetone,
2461 	&omap3xxx_l4_per__mcbsp3_sidetone,
2462 	&omap34xx_l4_core__mcspi1,
2463 	&omap34xx_l4_core__mcspi2,
2464 	&omap34xx_l4_core__mcspi3,
2465 	&omap34xx_l4_core__mcspi4,
2466 	&omap3xxx_l3_main__gpmc,
2467 	NULL,
2468 };
2469 
2470 /* crypto hwmod links */
2471 static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = {
2472 	&omap3xxx_l4_core__sham,
2473 	NULL,
2474 };
2475 
2476 static struct omap_hwmod_ocp_if *omap34xx_aes_hwmod_ocp_ifs[] __initdata = {
2477 	&omap3xxx_l4_core__aes,
2478 	NULL,
2479 };
2480 
2481 static struct omap_hwmod_ocp_if *omap36xx_sham_hwmod_ocp_ifs[] __initdata = {
2482 	&omap3xxx_l4_core__sham,
2483 	NULL
2484 };
2485 
2486 static struct omap_hwmod_ocp_if *omap36xx_aes_hwmod_ocp_ifs[] __initdata = {
2487 	&omap3xxx_l4_core__aes,
2488 	NULL
2489 };
2490 
2491 /*
2492  * Apparently the SHA/MD5 and AES accelerator IP blocks are
2493  * only present on some AM35xx chips, and no one knows which
2494  * ones.  See
2495  * http://www.spinics.net/lists/arm-kernel/msg215466.html So
2496  * if you need these IP blocks on an AM35xx, try uncommenting
2497  * the following lines.
2498  */
2499 static struct omap_hwmod_ocp_if *am35xx_sham_hwmod_ocp_ifs[] __initdata = {
2500 	/* &omap3xxx_l4_core__sham, */
2501 	NULL
2502 };
2503 
2504 static struct omap_hwmod_ocp_if *am35xx_aes_hwmod_ocp_ifs[] __initdata = {
2505 	/* &omap3xxx_l4_core__aes, */
2506 	NULL,
2507 };
2508 
2509 /* 3430ES1-only hwmod links */
2510 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
2511 	&omap3430es1_dss__l3,
2512 	&omap3430es1_l4_core__dss,
2513 	NULL,
2514 };
2515 
2516 /* 3430ES2+-only hwmod links */
2517 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
2518 	&omap3xxx_dss__l3,
2519 	&omap3xxx_l4_core__dss,
2520 	&omap3xxx_usbhsotg__l3,
2521 	&omap3xxx_l4_core__usbhsotg,
2522 	&omap3xxx_usb_host_hs__l3_main_2,
2523 	&omap3xxx_l4_core__usb_host_hs,
2524 	&omap3xxx_l4_core__usb_tll_hs,
2525 	NULL,
2526 };
2527 
2528 /* <= 3430ES3-only hwmod links */
2529 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
2530 	&omap3xxx_l4_core__pre_es3_mmc1,
2531 	&omap3xxx_l4_core__pre_es3_mmc2,
2532 	NULL,
2533 };
2534 
2535 /* 3430ES3+-only hwmod links */
2536 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
2537 	&omap3xxx_l4_core__es3plus_mmc1,
2538 	&omap3xxx_l4_core__es3plus_mmc2,
2539 	NULL,
2540 };
2541 
2542 /* 34xx-only hwmod links (all ES revisions) */
2543 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
2544 	&omap3xxx_l3__iva,
2545 	&omap34xx_l4_core__sr1,
2546 	&omap34xx_l4_core__sr2,
2547 	&omap3xxx_l4_core__mailbox,
2548 	&omap3xxx_l4_core__hdq1w,
2549 	&omap3xxx_sad2d__l3,
2550 	&omap3xxx_l4_core__mmu_isp,
2551 	&omap3xxx_l3_main__mmu_iva,
2552 	&omap3xxx_l4_core__ssi,
2553 	NULL,
2554 };
2555 
2556 /* 36xx-only hwmod links (all ES revisions) */
2557 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
2558 	&omap3xxx_l3__iva,
2559 	&omap36xx_l4_per__uart4,
2560 	&omap3xxx_dss__l3,
2561 	&omap3xxx_l4_core__dss,
2562 	&omap36xx_l4_core__sr1,
2563 	&omap36xx_l4_core__sr2,
2564 	&omap3xxx_usbhsotg__l3,
2565 	&omap3xxx_l4_core__usbhsotg,
2566 	&omap3xxx_l4_core__mailbox,
2567 	&omap3xxx_usb_host_hs__l3_main_2,
2568 	&omap3xxx_l4_core__usb_host_hs,
2569 	&omap3xxx_l4_core__usb_tll_hs,
2570 	&omap3xxx_l4_core__es3plus_mmc1,
2571 	&omap3xxx_l4_core__es3plus_mmc2,
2572 	&omap3xxx_l4_core__hdq1w,
2573 	&omap3xxx_sad2d__l3,
2574 	&omap3xxx_l4_core__mmu_isp,
2575 	&omap3xxx_l3_main__mmu_iva,
2576 	&omap3xxx_l4_core__ssi,
2577 	NULL,
2578 };
2579 
2580 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
2581 	&omap3xxx_dss__l3,
2582 	&omap3xxx_l4_core__dss,
2583 	&am35xx_usbhsotg__l3,
2584 	&am35xx_l4_core__usbhsotg,
2585 	&am35xx_l4_core__uart4,
2586 	&omap3xxx_usb_host_hs__l3_main_2,
2587 	&omap3xxx_l4_core__usb_host_hs,
2588 	&omap3xxx_l4_core__usb_tll_hs,
2589 	&omap3xxx_l4_core__es3plus_mmc1,
2590 	&omap3xxx_l4_core__es3plus_mmc2,
2591 	&omap3xxx_l4_core__hdq1w,
2592 	&am35xx_mdio__l3,
2593 	&am35xx_l4_core__mdio,
2594 	&am35xx_emac__l3,
2595 	&am35xx_l4_core__emac,
2596 	NULL,
2597 };
2598 
2599 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
2600 	&omap3xxx_l4_core__dss_dispc,
2601 	&omap3xxx_l4_core__dss_dsi1,
2602 	&omap3xxx_l4_core__dss_rfbi,
2603 	&omap3xxx_l4_core__dss_venc,
2604 	NULL,
2605 };
2606 
2607 /**
2608  * omap3xxx_hwmod_is_hs_ip_block_usable - is a security IP block accessible?
2609  * @bus: struct device_node * for the top-level OMAP DT data
2610  * @dev_name: device name used in the DT file
2611  *
2612  * Determine whether a "secure" IP block @dev_name is usable by Linux.
2613  * There doesn't appear to be a 100% reliable way to determine this,
2614  * so we rely on heuristics.  If @bus is null, meaning there's no DT
2615  * data, then we only assume the IP block is accessible if the OMAP is
2616  * fused as a 'general-purpose' SoC.  If however DT data is present,
2617  * test to see if the IP block is described in the DT data and set to
2618  * 'status = "okay"'.  If so then we assume the ODM has configured the
2619  * OMAP firewalls to allow access to the IP block.
2620  *
2621  * Return: 0 if device named @dev_name is not likely to be accessible,
2622  * or 1 if it is likely to be accessible.
2623  */
2624 static bool __init omap3xxx_hwmod_is_hs_ip_block_usable(struct device_node *bus,
2625 							const char *dev_name)
2626 {
2627 	struct device_node *node;
2628 	bool available;
2629 
2630 	if (!bus)
2631 		return omap_type() == OMAP2_DEVICE_TYPE_GP;
2632 
2633 	node = of_get_child_by_name(bus, dev_name);
2634 	available = of_device_is_available(node);
2635 	of_node_put(node);
2636 
2637 	return available;
2638 }
2639 
2640 int __init omap3xxx_hwmod_init(void)
2641 {
2642 	int r;
2643 	struct omap_hwmod_ocp_if **h = NULL, **h_sham = NULL;
2644 	struct omap_hwmod_ocp_if **h_aes = NULL;
2645 	struct device_node *bus;
2646 	unsigned int rev;
2647 
2648 	omap_hwmod_init();
2649 
2650 	/* Register hwmod links common to all OMAP3 */
2651 	r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
2652 	if (r < 0)
2653 		return r;
2654 
2655 	rev = omap_rev();
2656 
2657 	/*
2658 	 * Register hwmod links common to individual OMAP3 families, all
2659 	 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
2660 	 * All possible revisions should be included in this conditional.
2661 	 */
2662 	if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
2663 	    rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
2664 	    rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
2665 		h = omap34xx_hwmod_ocp_ifs;
2666 		h_sham = omap34xx_sham_hwmod_ocp_ifs;
2667 		h_aes = omap34xx_aes_hwmod_ocp_ifs;
2668 	} else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
2669 		h = am35xx_hwmod_ocp_ifs;
2670 		h_sham = am35xx_sham_hwmod_ocp_ifs;
2671 		h_aes = am35xx_aes_hwmod_ocp_ifs;
2672 	} else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
2673 		   rev == OMAP3630_REV_ES1_2) {
2674 		h = omap36xx_hwmod_ocp_ifs;
2675 		h_sham = omap36xx_sham_hwmod_ocp_ifs;
2676 		h_aes = omap36xx_aes_hwmod_ocp_ifs;
2677 	} else {
2678 		WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
2679 		return -EINVAL;
2680 	}
2681 
2682 	r = omap_hwmod_register_links(h);
2683 	if (r < 0)
2684 		return r;
2685 
2686 	/*
2687 	 * Register crypto hwmod links only if they are not disabled in DT.
2688 	 * If DT information is missing, enable them only for GP devices.
2689 	 */
2690 
2691 	bus = of_find_node_by_name(NULL, "ocp");
2692 
2693 	if (h_sham && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "sham")) {
2694 		r = omap_hwmod_register_links(h_sham);
2695 		if (r < 0)
2696 			goto put_node;
2697 	}
2698 
2699 	if (h_aes && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "aes")) {
2700 		r = omap_hwmod_register_links(h_aes);
2701 		if (r < 0)
2702 			goto put_node;
2703 	}
2704 	of_node_put(bus);
2705 
2706 	/*
2707 	 * Register hwmod links specific to certain ES levels of a
2708 	 * particular family of silicon (e.g., 34xx ES1.0)
2709 	 */
2710 	h = NULL;
2711 	if (rev == OMAP3430_REV_ES1_0) {
2712 		h = omap3430es1_hwmod_ocp_ifs;
2713 	} else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
2714 		   rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
2715 		   rev == OMAP3430_REV_ES3_1_2) {
2716 		h = omap3430es2plus_hwmod_ocp_ifs;
2717 	}
2718 
2719 	if (h) {
2720 		r = omap_hwmod_register_links(h);
2721 		if (r < 0)
2722 			return r;
2723 	}
2724 
2725 	h = NULL;
2726 	if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
2727 	    rev == OMAP3430_REV_ES2_1) {
2728 		h = omap3430_pre_es3_hwmod_ocp_ifs;
2729 	} else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
2730 		   rev == OMAP3430_REV_ES3_1_2) {
2731 		h = omap3430_es3plus_hwmod_ocp_ifs;
2732 	}
2733 
2734 	if (h)
2735 		r = omap_hwmod_register_links(h);
2736 	if (r < 0)
2737 		return r;
2738 
2739 	/*
2740 	 * DSS code presumes that dss_core hwmod is handled first,
2741 	 * _before_ any other DSS related hwmods so register common
2742 	 * DSS hwmod links last to ensure that dss_core is already
2743 	 * registered.  Otherwise some change things may happen, for
2744 	 * ex. if dispc is handled before dss_core and DSS is enabled
2745 	 * in bootloader DISPC will be reset with outputs enabled
2746 	 * which sometimes leads to unrecoverable L3 error.  XXX The
2747 	 * long-term fix to this is to ensure hwmods are set up in
2748 	 * dependency order in the hwmod core code.
2749 	 */
2750 	r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
2751 
2752 	return r;
2753 
2754 put_node:
2755 	of_node_put(bus);
2756 	return r;
2757 }
2758