1 /* 2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips 3 * 4 * Copyright (C) 2009-2010 Nokia Corporation 5 * Paul Walmsley 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * The data in this file should be completely autogeneratable from 12 * the TI hardware database or other technical documentation. 13 * 14 * XXX these should be marked initdata for multi-OMAP kernels 15 */ 16 #include <plat/omap_hwmod.h> 17 #include <mach/irqs.h> 18 #include <plat/cpu.h> 19 #include <plat/dma.h> 20 #include <plat/serial.h> 21 22 #include "omap_hwmod_common_data.h" 23 24 #include "prm-regbits-34xx.h" 25 #include "cm-regbits-34xx.h" 26 27 /* 28 * OMAP3xxx hardware module integration data 29 * 30 * ALl of the data in this section should be autogeneratable from the 31 * TI hardware database or other technical documentation. Data that 32 * is driver-specific or driver-kernel integration-specific belongs 33 * elsewhere. 34 */ 35 36 static struct omap_hwmod omap3xxx_mpu_hwmod; 37 static struct omap_hwmod omap3xxx_iva_hwmod; 38 static struct omap_hwmod omap3xxx_l3_main_hwmod; 39 static struct omap_hwmod omap3xxx_l4_core_hwmod; 40 static struct omap_hwmod omap3xxx_l4_per_hwmod; 41 static struct omap_hwmod omap3xxx_wd_timer2_hwmod; 42 43 /* L3 -> L4_CORE interface */ 44 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { 45 .master = &omap3xxx_l3_main_hwmod, 46 .slave = &omap3xxx_l4_core_hwmod, 47 .user = OCP_USER_MPU | OCP_USER_SDMA, 48 }; 49 50 /* L3 -> L4_PER interface */ 51 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { 52 .master = &omap3xxx_l3_main_hwmod, 53 .slave = &omap3xxx_l4_per_hwmod, 54 .user = OCP_USER_MPU | OCP_USER_SDMA, 55 }; 56 57 /* MPU -> L3 interface */ 58 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { 59 .master = &omap3xxx_mpu_hwmod, 60 .slave = &omap3xxx_l3_main_hwmod, 61 .user = OCP_USER_MPU, 62 }; 63 64 /* Slave interfaces on the L3 interconnect */ 65 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = { 66 &omap3xxx_mpu__l3_main, 67 }; 68 69 /* Master interfaces on the L3 interconnect */ 70 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = { 71 &omap3xxx_l3_main__l4_core, 72 &omap3xxx_l3_main__l4_per, 73 }; 74 75 /* L3 */ 76 static struct omap_hwmod omap3xxx_l3_main_hwmod = { 77 .name = "l3_main", 78 .class = &l3_hwmod_class, 79 .masters = omap3xxx_l3_main_masters, 80 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters), 81 .slaves = omap3xxx_l3_main_slaves, 82 .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves), 83 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 84 .flags = HWMOD_NO_IDLEST, 85 }; 86 87 static struct omap_hwmod omap3xxx_l4_wkup_hwmod; 88 static struct omap_hwmod omap3xxx_uart1_hwmod; 89 static struct omap_hwmod omap3xxx_uart2_hwmod; 90 static struct omap_hwmod omap3xxx_uart3_hwmod; 91 static struct omap_hwmod omap3xxx_uart4_hwmod; 92 93 /* L4_CORE -> L4_WKUP interface */ 94 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { 95 .master = &omap3xxx_l4_core_hwmod, 96 .slave = &omap3xxx_l4_wkup_hwmod, 97 .user = OCP_USER_MPU | OCP_USER_SDMA, 98 }; 99 100 /* L4 CORE -> UART1 interface */ 101 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = { 102 { 103 .pa_start = OMAP3_UART1_BASE, 104 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1, 105 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 106 }, 107 }; 108 109 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { 110 .master = &omap3xxx_l4_core_hwmod, 111 .slave = &omap3xxx_uart1_hwmod, 112 .clk = "uart1_ick", 113 .addr = omap3xxx_uart1_addr_space, 114 .addr_cnt = ARRAY_SIZE(omap3xxx_uart1_addr_space), 115 .user = OCP_USER_MPU | OCP_USER_SDMA, 116 }; 117 118 /* L4 CORE -> UART2 interface */ 119 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = { 120 { 121 .pa_start = OMAP3_UART2_BASE, 122 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1, 123 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 124 }, 125 }; 126 127 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { 128 .master = &omap3xxx_l4_core_hwmod, 129 .slave = &omap3xxx_uart2_hwmod, 130 .clk = "uart2_ick", 131 .addr = omap3xxx_uart2_addr_space, 132 .addr_cnt = ARRAY_SIZE(omap3xxx_uart2_addr_space), 133 .user = OCP_USER_MPU | OCP_USER_SDMA, 134 }; 135 136 /* L4 PER -> UART3 interface */ 137 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = { 138 { 139 .pa_start = OMAP3_UART3_BASE, 140 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1, 141 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 142 }, 143 }; 144 145 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { 146 .master = &omap3xxx_l4_per_hwmod, 147 .slave = &omap3xxx_uart3_hwmod, 148 .clk = "uart3_ick", 149 .addr = omap3xxx_uart3_addr_space, 150 .addr_cnt = ARRAY_SIZE(omap3xxx_uart3_addr_space), 151 .user = OCP_USER_MPU | OCP_USER_SDMA, 152 }; 153 154 /* L4 PER -> UART4 interface */ 155 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = { 156 { 157 .pa_start = OMAP3_UART4_BASE, 158 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1, 159 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 160 }, 161 }; 162 163 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = { 164 .master = &omap3xxx_l4_per_hwmod, 165 .slave = &omap3xxx_uart4_hwmod, 166 .clk = "uart4_ick", 167 .addr = omap3xxx_uart4_addr_space, 168 .addr_cnt = ARRAY_SIZE(omap3xxx_uart4_addr_space), 169 .user = OCP_USER_MPU | OCP_USER_SDMA, 170 }; 171 172 /* Slave interfaces on the L4_CORE interconnect */ 173 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { 174 &omap3xxx_l3_main__l4_core, 175 }; 176 177 /* Master interfaces on the L4_CORE interconnect */ 178 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = { 179 &omap3xxx_l4_core__l4_wkup, 180 &omap3_l4_core__uart1, 181 &omap3_l4_core__uart2, 182 }; 183 184 /* L4 CORE */ 185 static struct omap_hwmod omap3xxx_l4_core_hwmod = { 186 .name = "l4_core", 187 .class = &l4_hwmod_class, 188 .masters = omap3xxx_l4_core_masters, 189 .masters_cnt = ARRAY_SIZE(omap3xxx_l4_core_masters), 190 .slaves = omap3xxx_l4_core_slaves, 191 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves), 192 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 193 .flags = HWMOD_NO_IDLEST, 194 }; 195 196 /* Slave interfaces on the L4_PER interconnect */ 197 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = { 198 &omap3xxx_l3_main__l4_per, 199 }; 200 201 /* Master interfaces on the L4_PER interconnect */ 202 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = { 203 &omap3_l4_per__uart3, 204 &omap3_l4_per__uart4, 205 }; 206 207 /* L4 PER */ 208 static struct omap_hwmod omap3xxx_l4_per_hwmod = { 209 .name = "l4_per", 210 .class = &l4_hwmod_class, 211 .masters = omap3xxx_l4_per_masters, 212 .masters_cnt = ARRAY_SIZE(omap3xxx_l4_per_masters), 213 .slaves = omap3xxx_l4_per_slaves, 214 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves), 215 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 216 .flags = HWMOD_NO_IDLEST, 217 }; 218 219 /* Slave interfaces on the L4_WKUP interconnect */ 220 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = { 221 &omap3xxx_l4_core__l4_wkup, 222 }; 223 224 /* Master interfaces on the L4_WKUP interconnect */ 225 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_masters[] = { 226 }; 227 228 /* L4 WKUP */ 229 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { 230 .name = "l4_wkup", 231 .class = &l4_hwmod_class, 232 .masters = omap3xxx_l4_wkup_masters, 233 .masters_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_masters), 234 .slaves = omap3xxx_l4_wkup_slaves, 235 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves), 236 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 237 .flags = HWMOD_NO_IDLEST, 238 }; 239 240 /* Master interfaces on the MPU device */ 241 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = { 242 &omap3xxx_mpu__l3_main, 243 }; 244 245 /* MPU */ 246 static struct omap_hwmod omap3xxx_mpu_hwmod = { 247 .name = "mpu", 248 .class = &mpu_hwmod_class, 249 .main_clk = "arm_fck", 250 .masters = omap3xxx_mpu_masters, 251 .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters), 252 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 253 }; 254 255 /* 256 * IVA2_2 interface data 257 */ 258 259 /* IVA2 <- L3 interface */ 260 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = { 261 .master = &omap3xxx_l3_main_hwmod, 262 .slave = &omap3xxx_iva_hwmod, 263 .clk = "iva2_ck", 264 .user = OCP_USER_MPU | OCP_USER_SDMA, 265 }; 266 267 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = { 268 &omap3xxx_l3__iva, 269 }; 270 271 /* 272 * IVA2 (IVA2) 273 */ 274 275 static struct omap_hwmod omap3xxx_iva_hwmod = { 276 .name = "iva", 277 .class = &iva_hwmod_class, 278 .masters = omap3xxx_iva_masters, 279 .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters), 280 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) 281 }; 282 283 /* l4_wkup -> wd_timer2 */ 284 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { 285 { 286 .pa_start = 0x48314000, 287 .pa_end = 0x4831407f, 288 .flags = ADDR_TYPE_RT 289 }, 290 }; 291 292 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { 293 .master = &omap3xxx_l4_wkup_hwmod, 294 .slave = &omap3xxx_wd_timer2_hwmod, 295 .clk = "wdt2_ick", 296 .addr = omap3xxx_wd_timer2_addrs, 297 .addr_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_addrs), 298 .user = OCP_USER_MPU | OCP_USER_SDMA, 299 }; 300 301 /* 302 * 'wd_timer' class 303 * 32-bit watchdog upward counter that generates a pulse on the reset pin on 304 * overflow condition 305 */ 306 307 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { 308 .rev_offs = 0x0000, 309 .sysc_offs = 0x0010, 310 .syss_offs = 0x0014, 311 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | 312 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 313 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY), 314 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 315 .sysc_fields = &omap_hwmod_sysc_type1, 316 }; 317 318 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { 319 .name = "wd_timer", 320 .sysc = &omap3xxx_wd_timer_sysc, 321 }; 322 323 /* wd_timer2 */ 324 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = { 325 &omap3xxx_l4_wkup__wd_timer2, 326 }; 327 328 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { 329 .name = "wd_timer2", 330 .class = &omap3xxx_wd_timer_hwmod_class, 331 .main_clk = "wdt2_fck", 332 .prcm = { 333 .omap2 = { 334 .prcm_reg_id = 1, 335 .module_bit = OMAP3430_EN_WDT2_SHIFT, 336 .module_offs = WKUP_MOD, 337 .idlest_reg_id = 1, 338 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, 339 }, 340 }, 341 .slaves = omap3xxx_wd_timer2_slaves, 342 .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves), 343 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 344 }; 345 346 /* UART common */ 347 348 static struct omap_hwmod_class_sysconfig uart_sysc = { 349 .rev_offs = 0x50, 350 .sysc_offs = 0x54, 351 .syss_offs = 0x58, 352 .sysc_flags = (SYSC_HAS_SIDLEMODE | 353 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 354 SYSC_HAS_AUTOIDLE), 355 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 356 .sysc_fields = &omap_hwmod_sysc_type1, 357 }; 358 359 static struct omap_hwmod_class uart_class = { 360 .name = "uart", 361 .sysc = &uart_sysc, 362 }; 363 364 /* UART1 */ 365 366 static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { 367 { .irq = INT_24XX_UART1_IRQ, }, 368 }; 369 370 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { 371 { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, 372 { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, 373 }; 374 375 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = { 376 &omap3_l4_core__uart1, 377 }; 378 379 static struct omap_hwmod omap3xxx_uart1_hwmod = { 380 .name = "uart1", 381 .mpu_irqs = uart1_mpu_irqs, 382 .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), 383 .sdma_reqs = uart1_sdma_reqs, 384 .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), 385 .main_clk = "uart1_fck", 386 .prcm = { 387 .omap2 = { 388 .module_offs = CORE_MOD, 389 .prcm_reg_id = 1, 390 .module_bit = OMAP3430_EN_UART1_SHIFT, 391 .idlest_reg_id = 1, 392 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, 393 }, 394 }, 395 .slaves = omap3xxx_uart1_slaves, 396 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves), 397 .class = &uart_class, 398 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 399 }; 400 401 /* UART2 */ 402 403 static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { 404 { .irq = INT_24XX_UART2_IRQ, }, 405 }; 406 407 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { 408 { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, 409 { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, 410 }; 411 412 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = { 413 &omap3_l4_core__uart2, 414 }; 415 416 static struct omap_hwmod omap3xxx_uart2_hwmod = { 417 .name = "uart2", 418 .mpu_irqs = uart2_mpu_irqs, 419 .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), 420 .sdma_reqs = uart2_sdma_reqs, 421 .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), 422 .main_clk = "uart2_fck", 423 .prcm = { 424 .omap2 = { 425 .module_offs = CORE_MOD, 426 .prcm_reg_id = 1, 427 .module_bit = OMAP3430_EN_UART2_SHIFT, 428 .idlest_reg_id = 1, 429 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, 430 }, 431 }, 432 .slaves = omap3xxx_uart2_slaves, 433 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves), 434 .class = &uart_class, 435 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 436 }; 437 438 /* UART3 */ 439 440 static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { 441 { .irq = INT_24XX_UART3_IRQ, }, 442 }; 443 444 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { 445 { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, 446 { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, 447 }; 448 449 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = { 450 &omap3_l4_per__uart3, 451 }; 452 453 static struct omap_hwmod omap3xxx_uart3_hwmod = { 454 .name = "uart3", 455 .mpu_irqs = uart3_mpu_irqs, 456 .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), 457 .sdma_reqs = uart3_sdma_reqs, 458 .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), 459 .main_clk = "uart3_fck", 460 .prcm = { 461 .omap2 = { 462 .module_offs = OMAP3430_PER_MOD, 463 .prcm_reg_id = 1, 464 .module_bit = OMAP3430_EN_UART3_SHIFT, 465 .idlest_reg_id = 1, 466 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, 467 }, 468 }, 469 .slaves = omap3xxx_uart3_slaves, 470 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves), 471 .class = &uart_class, 472 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 473 }; 474 475 /* UART4 */ 476 477 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { 478 { .irq = INT_36XX_UART4_IRQ, }, 479 }; 480 481 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { 482 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, }, 483 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, }, 484 }; 485 486 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = { 487 &omap3_l4_per__uart4, 488 }; 489 490 static struct omap_hwmod omap3xxx_uart4_hwmod = { 491 .name = "uart4", 492 .mpu_irqs = uart4_mpu_irqs, 493 .mpu_irqs_cnt = ARRAY_SIZE(uart4_mpu_irqs), 494 .sdma_reqs = uart4_sdma_reqs, 495 .sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs), 496 .main_clk = "uart4_fck", 497 .prcm = { 498 .omap2 = { 499 .module_offs = OMAP3430_PER_MOD, 500 .prcm_reg_id = 1, 501 .module_bit = OMAP3630_EN_UART4_SHIFT, 502 .idlest_reg_id = 1, 503 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, 504 }, 505 }, 506 .slaves = omap3xxx_uart4_slaves, 507 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves), 508 .class = &uart_class, 509 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), 510 }; 511 512 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { 513 &omap3xxx_l3_main_hwmod, 514 &omap3xxx_l4_core_hwmod, 515 &omap3xxx_l4_per_hwmod, 516 &omap3xxx_l4_wkup_hwmod, 517 &omap3xxx_mpu_hwmod, 518 &omap3xxx_iva_hwmod, 519 &omap3xxx_wd_timer2_hwmod, 520 &omap3xxx_uart1_hwmod, 521 &omap3xxx_uart2_hwmod, 522 &omap3xxx_uart3_hwmod, 523 &omap3xxx_uart4_hwmod, 524 NULL, 525 }; 526 527 int __init omap3xxx_hwmod_init(void) 528 { 529 return omap_hwmod_init(omap3xxx_hwmods); 530 } 531