1 /*
2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
3  *
4  * Copyright (C) 2009-2011 Nokia Corporation
5  * Copyright (C) 2012 Texas Instruments, Inc.
6  * Paul Walmsley
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  *
12  * The data in this file should be completely autogeneratable from
13  * the TI hardware database or other technical documentation.
14  *
15  * XXX these should be marked initdata for multi-OMAP kernels
16  */
17 #include <linux/power/smartreflex.h>
18 
19 #include <plat/omap_hwmod.h>
20 #include <mach/irqs.h>
21 #include <plat/cpu.h>
22 #include <plat/dma.h>
23 #include <plat/serial.h>
24 #include <plat/l3_3xxx.h>
25 #include <plat/l4_3xxx.h>
26 #include <plat/i2c.h>
27 #include <plat/gpio.h>
28 #include <plat/mmc.h>
29 #include <plat/mcbsp.h>
30 #include <plat/mcspi.h>
31 #include <plat/dmtimer.h>
32 
33 #include "omap_hwmod_common_data.h"
34 #include "prm-regbits-34xx.h"
35 #include "cm-regbits-34xx.h"
36 #include "wd_timer.h"
37 #include <mach/am35xx.h>
38 
39 /*
40  * OMAP3xxx hardware module integration data
41  *
42  * All of the data in this section should be autogeneratable from the
43  * TI hardware database or other technical documentation.  Data that
44  * is driver-specific or driver-kernel integration-specific belongs
45  * elsewhere.
46  */
47 
48 /*
49  * IP blocks
50  */
51 
52 /* L3 */
53 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
54 	{ .irq = INT_34XX_L3_DBG_IRQ },
55 	{ .irq = INT_34XX_L3_APP_IRQ },
56 	{ .irq = -1 }
57 };
58 
59 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
60 	.name		= "l3_main",
61 	.class		= &l3_hwmod_class,
62 	.mpu_irqs	= omap3xxx_l3_main_irqs,
63 	.flags		= HWMOD_NO_IDLEST,
64 };
65 
66 /* L4 CORE */
67 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
68 	.name		= "l4_core",
69 	.class		= &l4_hwmod_class,
70 	.flags		= HWMOD_NO_IDLEST,
71 };
72 
73 /* L4 PER */
74 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
75 	.name		= "l4_per",
76 	.class		= &l4_hwmod_class,
77 	.flags		= HWMOD_NO_IDLEST,
78 };
79 
80 /* L4 WKUP */
81 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
82 	.name		= "l4_wkup",
83 	.class		= &l4_hwmod_class,
84 	.flags		= HWMOD_NO_IDLEST,
85 };
86 
87 /* L4 SEC */
88 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
89 	.name		= "l4_sec",
90 	.class		= &l4_hwmod_class,
91 	.flags		= HWMOD_NO_IDLEST,
92 };
93 
94 /* MPU */
95 static struct omap_hwmod omap3xxx_mpu_hwmod = {
96 	.name		= "mpu",
97 	.class		= &mpu_hwmod_class,
98 	.main_clk	= "arm_fck",
99 };
100 
101 /* IVA2 (IVA2) */
102 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
103 	{ .name = "logic", .rst_shift = 0 },
104 	{ .name = "seq0", .rst_shift = 1 },
105 	{ .name = "seq1", .rst_shift = 2 },
106 };
107 
108 static struct omap_hwmod omap3xxx_iva_hwmod = {
109 	.name		= "iva",
110 	.class		= &iva_hwmod_class,
111 	.clkdm_name	= "iva2_clkdm",
112 	.rst_lines	= omap3xxx_iva_resets,
113 	.rst_lines_cnt	= ARRAY_SIZE(omap3xxx_iva_resets),
114 	.main_clk	= "iva2_ck",
115 };
116 
117 /* timer class */
118 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
119 	.rev_offs	= 0x0000,
120 	.sysc_offs	= 0x0010,
121 	.syss_offs	= 0x0014,
122 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
123 				SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
124 				SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
125 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
126 	.sysc_fields	= &omap_hwmod_sysc_type1,
127 };
128 
129 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
130 	.name = "timer",
131 	.sysc = &omap3xxx_timer_1ms_sysc,
132 };
133 
134 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
135 	.rev_offs	= 0x0000,
136 	.sysc_offs	= 0x0010,
137 	.syss_offs	= 0x0014,
138 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
139 			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
140 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
141 	.sysc_fields	= &omap_hwmod_sysc_type1,
142 };
143 
144 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
145 	.name = "timer",
146 	.sysc = &omap3xxx_timer_sysc,
147 };
148 
149 /* secure timers dev attribute */
150 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
151 	.timer_capability	= OMAP_TIMER_ALWON | OMAP_TIMER_SECURE,
152 };
153 
154 /* always-on timers dev attribute */
155 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
156 	.timer_capability	= OMAP_TIMER_ALWON,
157 };
158 
159 /* pwm timers dev attribute */
160 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
161 	.timer_capability	= OMAP_TIMER_HAS_PWM,
162 };
163 
164 /* timer1 */
165 static struct omap_hwmod omap3xxx_timer1_hwmod = {
166 	.name		= "timer1",
167 	.mpu_irqs	= omap2_timer1_mpu_irqs,
168 	.main_clk	= "gpt1_fck",
169 	.prcm		= {
170 		.omap2 = {
171 			.prcm_reg_id = 1,
172 			.module_bit = OMAP3430_EN_GPT1_SHIFT,
173 			.module_offs = WKUP_MOD,
174 			.idlest_reg_id = 1,
175 			.idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
176 		},
177 	},
178 	.dev_attr	= &capability_alwon_dev_attr,
179 	.class		= &omap3xxx_timer_1ms_hwmod_class,
180 };
181 
182 /* timer2 */
183 static struct omap_hwmod omap3xxx_timer2_hwmod = {
184 	.name		= "timer2",
185 	.mpu_irqs	= omap2_timer2_mpu_irqs,
186 	.main_clk	= "gpt2_fck",
187 	.prcm		= {
188 		.omap2 = {
189 			.prcm_reg_id = 1,
190 			.module_bit = OMAP3430_EN_GPT2_SHIFT,
191 			.module_offs = OMAP3430_PER_MOD,
192 			.idlest_reg_id = 1,
193 			.idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
194 		},
195 	},
196 	.class		= &omap3xxx_timer_1ms_hwmod_class,
197 };
198 
199 /* timer3 */
200 static struct omap_hwmod omap3xxx_timer3_hwmod = {
201 	.name		= "timer3",
202 	.mpu_irqs	= omap2_timer3_mpu_irqs,
203 	.main_clk	= "gpt3_fck",
204 	.prcm		= {
205 		.omap2 = {
206 			.prcm_reg_id = 1,
207 			.module_bit = OMAP3430_EN_GPT3_SHIFT,
208 			.module_offs = OMAP3430_PER_MOD,
209 			.idlest_reg_id = 1,
210 			.idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
211 		},
212 	},
213 	.class		= &omap3xxx_timer_hwmod_class,
214 };
215 
216 /* timer4 */
217 static struct omap_hwmod omap3xxx_timer4_hwmod = {
218 	.name		= "timer4",
219 	.mpu_irqs	= omap2_timer4_mpu_irqs,
220 	.main_clk	= "gpt4_fck",
221 	.prcm		= {
222 		.omap2 = {
223 			.prcm_reg_id = 1,
224 			.module_bit = OMAP3430_EN_GPT4_SHIFT,
225 			.module_offs = OMAP3430_PER_MOD,
226 			.idlest_reg_id = 1,
227 			.idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
228 		},
229 	},
230 	.class		= &omap3xxx_timer_hwmod_class,
231 };
232 
233 /* timer5 */
234 static struct omap_hwmod omap3xxx_timer5_hwmod = {
235 	.name		= "timer5",
236 	.mpu_irqs	= omap2_timer5_mpu_irqs,
237 	.main_clk	= "gpt5_fck",
238 	.prcm		= {
239 		.omap2 = {
240 			.prcm_reg_id = 1,
241 			.module_bit = OMAP3430_EN_GPT5_SHIFT,
242 			.module_offs = OMAP3430_PER_MOD,
243 			.idlest_reg_id = 1,
244 			.idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
245 		},
246 	},
247 	.class		= &omap3xxx_timer_hwmod_class,
248 };
249 
250 /* timer6 */
251 static struct omap_hwmod omap3xxx_timer6_hwmod = {
252 	.name		= "timer6",
253 	.mpu_irqs	= omap2_timer6_mpu_irqs,
254 	.main_clk	= "gpt6_fck",
255 	.prcm		= {
256 		.omap2 = {
257 			.prcm_reg_id = 1,
258 			.module_bit = OMAP3430_EN_GPT6_SHIFT,
259 			.module_offs = OMAP3430_PER_MOD,
260 			.idlest_reg_id = 1,
261 			.idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
262 		},
263 	},
264 	.class		= &omap3xxx_timer_hwmod_class,
265 };
266 
267 /* timer7 */
268 static struct omap_hwmod omap3xxx_timer7_hwmod = {
269 	.name		= "timer7",
270 	.mpu_irqs	= omap2_timer7_mpu_irqs,
271 	.main_clk	= "gpt7_fck",
272 	.prcm		= {
273 		.omap2 = {
274 			.prcm_reg_id = 1,
275 			.module_bit = OMAP3430_EN_GPT7_SHIFT,
276 			.module_offs = OMAP3430_PER_MOD,
277 			.idlest_reg_id = 1,
278 			.idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
279 		},
280 	},
281 	.class		= &omap3xxx_timer_hwmod_class,
282 };
283 
284 /* timer8 */
285 static struct omap_hwmod omap3xxx_timer8_hwmod = {
286 	.name		= "timer8",
287 	.mpu_irqs	= omap2_timer8_mpu_irqs,
288 	.main_clk	= "gpt8_fck",
289 	.prcm		= {
290 		.omap2 = {
291 			.prcm_reg_id = 1,
292 			.module_bit = OMAP3430_EN_GPT8_SHIFT,
293 			.module_offs = OMAP3430_PER_MOD,
294 			.idlest_reg_id = 1,
295 			.idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
296 		},
297 	},
298 	.dev_attr	= &capability_pwm_dev_attr,
299 	.class		= &omap3xxx_timer_hwmod_class,
300 };
301 
302 /* timer9 */
303 static struct omap_hwmod omap3xxx_timer9_hwmod = {
304 	.name		= "timer9",
305 	.mpu_irqs	= omap2_timer9_mpu_irqs,
306 	.main_clk	= "gpt9_fck",
307 	.prcm		= {
308 		.omap2 = {
309 			.prcm_reg_id = 1,
310 			.module_bit = OMAP3430_EN_GPT9_SHIFT,
311 			.module_offs = OMAP3430_PER_MOD,
312 			.idlest_reg_id = 1,
313 			.idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
314 		},
315 	},
316 	.dev_attr	= &capability_pwm_dev_attr,
317 	.class		= &omap3xxx_timer_hwmod_class,
318 };
319 
320 /* timer10 */
321 static struct omap_hwmod omap3xxx_timer10_hwmod = {
322 	.name		= "timer10",
323 	.mpu_irqs	= omap2_timer10_mpu_irqs,
324 	.main_clk	= "gpt10_fck",
325 	.prcm		= {
326 		.omap2 = {
327 			.prcm_reg_id = 1,
328 			.module_bit = OMAP3430_EN_GPT10_SHIFT,
329 			.module_offs = CORE_MOD,
330 			.idlest_reg_id = 1,
331 			.idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
332 		},
333 	},
334 	.dev_attr	= &capability_pwm_dev_attr,
335 	.class		= &omap3xxx_timer_1ms_hwmod_class,
336 };
337 
338 /* timer11 */
339 static struct omap_hwmod omap3xxx_timer11_hwmod = {
340 	.name		= "timer11",
341 	.mpu_irqs	= omap2_timer11_mpu_irqs,
342 	.main_clk	= "gpt11_fck",
343 	.prcm		= {
344 		.omap2 = {
345 			.prcm_reg_id = 1,
346 			.module_bit = OMAP3430_EN_GPT11_SHIFT,
347 			.module_offs = CORE_MOD,
348 			.idlest_reg_id = 1,
349 			.idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
350 		},
351 	},
352 	.dev_attr	= &capability_pwm_dev_attr,
353 	.class		= &omap3xxx_timer_hwmod_class,
354 };
355 
356 /* timer12 */
357 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
358 	{ .irq = 95, },
359 	{ .irq = -1 }
360 };
361 
362 static struct omap_hwmod omap3xxx_timer12_hwmod = {
363 	.name		= "timer12",
364 	.mpu_irqs	= omap3xxx_timer12_mpu_irqs,
365 	.main_clk	= "gpt12_fck",
366 	.prcm		= {
367 		.omap2 = {
368 			.prcm_reg_id = 1,
369 			.module_bit = OMAP3430_EN_GPT12_SHIFT,
370 			.module_offs = WKUP_MOD,
371 			.idlest_reg_id = 1,
372 			.idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
373 		},
374 	},
375 	.dev_attr	= &capability_secure_dev_attr,
376 	.class		= &omap3xxx_timer_hwmod_class,
377 };
378 
379 /*
380  * 'wd_timer' class
381  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
382  * overflow condition
383  */
384 
385 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
386 	.rev_offs	= 0x0000,
387 	.sysc_offs	= 0x0010,
388 	.syss_offs	= 0x0014,
389 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
390 			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
391 			   SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
392 			   SYSS_HAS_RESET_STATUS),
393 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
394 	.sysc_fields    = &omap_hwmod_sysc_type1,
395 };
396 
397 /* I2C common */
398 static struct omap_hwmod_class_sysconfig i2c_sysc = {
399 	.rev_offs	= 0x00,
400 	.sysc_offs	= 0x20,
401 	.syss_offs	= 0x10,
402 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
403 			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
404 			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
405 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
406 	.clockact	= CLOCKACT_TEST_ICLK,
407 	.sysc_fields    = &omap_hwmod_sysc_type1,
408 };
409 
410 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
411 	.name		= "wd_timer",
412 	.sysc		= &omap3xxx_wd_timer_sysc,
413 	.pre_shutdown	= &omap2_wd_timer_disable,
414 	.reset		= &omap2_wd_timer_reset,
415 };
416 
417 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
418 	.name		= "wd_timer2",
419 	.class		= &omap3xxx_wd_timer_hwmod_class,
420 	.main_clk	= "wdt2_fck",
421 	.prcm		= {
422 		.omap2 = {
423 			.prcm_reg_id = 1,
424 			.module_bit = OMAP3430_EN_WDT2_SHIFT,
425 			.module_offs = WKUP_MOD,
426 			.idlest_reg_id = 1,
427 			.idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
428 		},
429 	},
430 	/*
431 	 * XXX: Use software supervised mode, HW supervised smartidle seems to
432 	 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
433 	 */
434 	.flags		= HWMOD_SWSUP_SIDLE,
435 };
436 
437 /* UART1 */
438 static struct omap_hwmod omap3xxx_uart1_hwmod = {
439 	.name		= "uart1",
440 	.mpu_irqs	= omap2_uart1_mpu_irqs,
441 	.sdma_reqs	= omap2_uart1_sdma_reqs,
442 	.main_clk	= "uart1_fck",
443 	.prcm		= {
444 		.omap2 = {
445 			.module_offs = CORE_MOD,
446 			.prcm_reg_id = 1,
447 			.module_bit = OMAP3430_EN_UART1_SHIFT,
448 			.idlest_reg_id = 1,
449 			.idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
450 		},
451 	},
452 	.class		= &omap2_uart_class,
453 };
454 
455 /* UART2 */
456 static struct omap_hwmod omap3xxx_uart2_hwmod = {
457 	.name		= "uart2",
458 	.mpu_irqs	= omap2_uart2_mpu_irqs,
459 	.sdma_reqs	= omap2_uart2_sdma_reqs,
460 	.main_clk	= "uart2_fck",
461 	.prcm		= {
462 		.omap2 = {
463 			.module_offs = CORE_MOD,
464 			.prcm_reg_id = 1,
465 			.module_bit = OMAP3430_EN_UART2_SHIFT,
466 			.idlest_reg_id = 1,
467 			.idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
468 		},
469 	},
470 	.class		= &omap2_uart_class,
471 };
472 
473 /* UART3 */
474 static struct omap_hwmod omap3xxx_uart3_hwmod = {
475 	.name		= "uart3",
476 	.mpu_irqs	= omap2_uart3_mpu_irqs,
477 	.sdma_reqs	= omap2_uart3_sdma_reqs,
478 	.main_clk	= "uart3_fck",
479 	.prcm		= {
480 		.omap2 = {
481 			.module_offs = OMAP3430_PER_MOD,
482 			.prcm_reg_id = 1,
483 			.module_bit = OMAP3430_EN_UART3_SHIFT,
484 			.idlest_reg_id = 1,
485 			.idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
486 		},
487 	},
488 	.class		= &omap2_uart_class,
489 };
490 
491 /* UART4 */
492 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
493 	{ .irq = INT_36XX_UART4_IRQ, },
494 	{ .irq = -1 }
495 };
496 
497 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
498 	{ .name = "rx",	.dma_req = OMAP36XX_DMA_UART4_RX, },
499 	{ .name = "tx",	.dma_req = OMAP36XX_DMA_UART4_TX, },
500 	{ .dma_req = -1 }
501 };
502 
503 static struct omap_hwmod omap36xx_uart4_hwmod = {
504 	.name		= "uart4",
505 	.mpu_irqs	= uart4_mpu_irqs,
506 	.sdma_reqs	= uart4_sdma_reqs,
507 	.main_clk	= "uart4_fck",
508 	.prcm		= {
509 		.omap2 = {
510 			.module_offs = OMAP3430_PER_MOD,
511 			.prcm_reg_id = 1,
512 			.module_bit = OMAP3630_EN_UART4_SHIFT,
513 			.idlest_reg_id = 1,
514 			.idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
515 		},
516 	},
517 	.class		= &omap2_uart_class,
518 };
519 
520 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
521 	{ .irq = INT_35XX_UART4_IRQ, },
522 	{ .irq = -1 }
523 };
524 
525 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
526 	{ .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
527 	{ .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
528 	{ .dma_req = -1 }
529 };
530 
531 /*
532  * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
533  * uart2_fck being enabled.  So we add uart1_fck as an optional clock,
534  * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET.  This really
535  * should not be needed.  The functional clock structure of the AM35xx
536  * UART4 is extremely unclear and opaque; it is unclear what the role
537  * of uart1/2_fck is for the UART4.  Any clarification from either
538  * empirical testing or the AM3505/3517 hardware designers would be
539  * most welcome.
540  */
541 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
542 	{ .role = "softreset_uart1_fck", .clk = "uart1_fck" },
543 };
544 
545 static struct omap_hwmod am35xx_uart4_hwmod = {
546 	.name		= "uart4",
547 	.mpu_irqs	= am35xx_uart4_mpu_irqs,
548 	.sdma_reqs	= am35xx_uart4_sdma_reqs,
549 	.main_clk	= "uart4_fck",
550 	.prcm		= {
551 		.omap2 = {
552 			.module_offs = CORE_MOD,
553 			.prcm_reg_id = 1,
554 			.module_bit = AM35XX_EN_UART4_SHIFT,
555 			.idlest_reg_id = 1,
556 			.idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
557 		},
558 	},
559 	.opt_clks	= am35xx_uart4_opt_clks,
560 	.opt_clks_cnt	= ARRAY_SIZE(am35xx_uart4_opt_clks),
561 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
562 	.class		= &omap2_uart_class,
563 };
564 
565 static struct omap_hwmod_class i2c_class = {
566 	.name	= "i2c",
567 	.sysc	= &i2c_sysc,
568 	.rev	= OMAP_I2C_IP_VERSION_1,
569 	.reset	= &omap_i2c_reset,
570 };
571 
572 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
573 	{ .name = "dispc", .dma_req = 5 },
574 	{ .name = "dsi1", .dma_req = 74 },
575 	{ .dma_req = -1 }
576 };
577 
578 /* dss */
579 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
580 	/*
581 	 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
582 	 * driver does not use these clocks.
583 	 */
584 	{ .role = "sys_clk", .clk = "dss2_alwon_fck" },
585 	{ .role = "tv_clk", .clk = "dss_tv_fck" },
586 	/* required only on OMAP3430 */
587 	{ .role = "tv_dac_clk", .clk = "dss_96m_fck" },
588 };
589 
590 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
591 	.name		= "dss_core",
592 	.class		= &omap2_dss_hwmod_class,
593 	.main_clk	= "dss1_alwon_fck", /* instead of dss_fck */
594 	.sdma_reqs	= omap3xxx_dss_sdma_chs,
595 	.prcm		= {
596 		.omap2 = {
597 			.prcm_reg_id = 1,
598 			.module_bit = OMAP3430_EN_DSS1_SHIFT,
599 			.module_offs = OMAP3430_DSS_MOD,
600 			.idlest_reg_id = 1,
601 			.idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
602 		},
603 	},
604 	.opt_clks	= dss_opt_clks,
605 	.opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
606 	.flags		= HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
607 };
608 
609 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
610 	.name		= "dss_core",
611 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
612 	.class		= &omap2_dss_hwmod_class,
613 	.main_clk	= "dss1_alwon_fck", /* instead of dss_fck */
614 	.sdma_reqs	= omap3xxx_dss_sdma_chs,
615 	.prcm		= {
616 		.omap2 = {
617 			.prcm_reg_id = 1,
618 			.module_bit = OMAP3430_EN_DSS1_SHIFT,
619 			.module_offs = OMAP3430_DSS_MOD,
620 			.idlest_reg_id = 1,
621 			.idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
622 			.idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
623 		},
624 	},
625 	.opt_clks	= dss_opt_clks,
626 	.opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
627 };
628 
629 /*
630  * 'dispc' class
631  * display controller
632  */
633 
634 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
635 	.rev_offs	= 0x0000,
636 	.sysc_offs	= 0x0010,
637 	.syss_offs	= 0x0014,
638 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
639 			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
640 			   SYSC_HAS_ENAWAKEUP),
641 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
642 			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
643 	.sysc_fields	= &omap_hwmod_sysc_type1,
644 };
645 
646 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
647 	.name	= "dispc",
648 	.sysc	= &omap3_dispc_sysc,
649 };
650 
651 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
652 	.name		= "dss_dispc",
653 	.class		= &omap3_dispc_hwmod_class,
654 	.mpu_irqs	= omap2_dispc_irqs,
655 	.main_clk	= "dss1_alwon_fck",
656 	.prcm		= {
657 		.omap2 = {
658 			.prcm_reg_id = 1,
659 			.module_bit = OMAP3430_EN_DSS1_SHIFT,
660 			.module_offs = OMAP3430_DSS_MOD,
661 		},
662 	},
663 	.flags		= HWMOD_NO_IDLEST,
664 	.dev_attr	= &omap2_3_dss_dispc_dev_attr
665 };
666 
667 /*
668  * 'dsi' class
669  * display serial interface controller
670  */
671 
672 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
673 	.name = "dsi",
674 };
675 
676 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
677 	{ .irq = 25 },
678 	{ .irq = -1 }
679 };
680 
681 /* dss_dsi1 */
682 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
683 	{ .role = "sys_clk", .clk = "dss2_alwon_fck" },
684 };
685 
686 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
687 	.name		= "dss_dsi1",
688 	.class		= &omap3xxx_dsi_hwmod_class,
689 	.mpu_irqs	= omap3xxx_dsi1_irqs,
690 	.main_clk	= "dss1_alwon_fck",
691 	.prcm		= {
692 		.omap2 = {
693 			.prcm_reg_id = 1,
694 			.module_bit = OMAP3430_EN_DSS1_SHIFT,
695 			.module_offs = OMAP3430_DSS_MOD,
696 		},
697 	},
698 	.opt_clks	= dss_dsi1_opt_clks,
699 	.opt_clks_cnt	= ARRAY_SIZE(dss_dsi1_opt_clks),
700 	.flags		= HWMOD_NO_IDLEST,
701 };
702 
703 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
704 	{ .role = "ick", .clk = "dss_ick" },
705 };
706 
707 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
708 	.name		= "dss_rfbi",
709 	.class		= &omap2_rfbi_hwmod_class,
710 	.main_clk	= "dss1_alwon_fck",
711 	.prcm		= {
712 		.omap2 = {
713 			.prcm_reg_id = 1,
714 			.module_bit = OMAP3430_EN_DSS1_SHIFT,
715 			.module_offs = OMAP3430_DSS_MOD,
716 		},
717 	},
718 	.opt_clks	= dss_rfbi_opt_clks,
719 	.opt_clks_cnt	= ARRAY_SIZE(dss_rfbi_opt_clks),
720 	.flags		= HWMOD_NO_IDLEST,
721 };
722 
723 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
724 	/* required only on OMAP3430 */
725 	{ .role = "tv_dac_clk", .clk = "dss_96m_fck" },
726 };
727 
728 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
729 	.name		= "dss_venc",
730 	.class		= &omap2_venc_hwmod_class,
731 	.main_clk	= "dss_tv_fck",
732 	.prcm		= {
733 		.omap2 = {
734 			.prcm_reg_id = 1,
735 			.module_bit = OMAP3430_EN_DSS1_SHIFT,
736 			.module_offs = OMAP3430_DSS_MOD,
737 		},
738 	},
739 	.opt_clks	= dss_venc_opt_clks,
740 	.opt_clks_cnt	= ARRAY_SIZE(dss_venc_opt_clks),
741 	.flags		= HWMOD_NO_IDLEST,
742 };
743 
744 /* I2C1 */
745 static struct omap_i2c_dev_attr i2c1_dev_attr = {
746 	.fifo_depth	= 8, /* bytes */
747 	.flags		= OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
748 			  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
749 			  OMAP_I2C_FLAG_BUS_SHIFT_2,
750 };
751 
752 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
753 	.name		= "i2c1",
754 	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
755 	.mpu_irqs	= omap2_i2c1_mpu_irqs,
756 	.sdma_reqs	= omap2_i2c1_sdma_reqs,
757 	.main_clk	= "i2c1_fck",
758 	.prcm		= {
759 		.omap2 = {
760 			.module_offs = CORE_MOD,
761 			.prcm_reg_id = 1,
762 			.module_bit = OMAP3430_EN_I2C1_SHIFT,
763 			.idlest_reg_id = 1,
764 			.idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
765 		},
766 	},
767 	.class		= &i2c_class,
768 	.dev_attr	= &i2c1_dev_attr,
769 };
770 
771 /* I2C2 */
772 static struct omap_i2c_dev_attr i2c2_dev_attr = {
773 	.fifo_depth	= 8, /* bytes */
774 	.flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
775 		 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
776 		 OMAP_I2C_FLAG_BUS_SHIFT_2,
777 };
778 
779 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
780 	.name		= "i2c2",
781 	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
782 	.mpu_irqs	= omap2_i2c2_mpu_irqs,
783 	.sdma_reqs	= omap2_i2c2_sdma_reqs,
784 	.main_clk	= "i2c2_fck",
785 	.prcm		= {
786 		.omap2 = {
787 			.module_offs = CORE_MOD,
788 			.prcm_reg_id = 1,
789 			.module_bit = OMAP3430_EN_I2C2_SHIFT,
790 			.idlest_reg_id = 1,
791 			.idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
792 		},
793 	},
794 	.class		= &i2c_class,
795 	.dev_attr	= &i2c2_dev_attr,
796 };
797 
798 /* I2C3 */
799 static struct omap_i2c_dev_attr i2c3_dev_attr = {
800 	.fifo_depth	= 64, /* bytes */
801 	.flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
802 		 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
803 		 OMAP_I2C_FLAG_BUS_SHIFT_2,
804 };
805 
806 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
807 	{ .irq = INT_34XX_I2C3_IRQ, },
808 	{ .irq = -1 }
809 };
810 
811 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
812 	{ .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
813 	{ .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
814 	{ .dma_req = -1 }
815 };
816 
817 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
818 	.name		= "i2c3",
819 	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
820 	.mpu_irqs	= i2c3_mpu_irqs,
821 	.sdma_reqs	= i2c3_sdma_reqs,
822 	.main_clk	= "i2c3_fck",
823 	.prcm		= {
824 		.omap2 = {
825 			.module_offs = CORE_MOD,
826 			.prcm_reg_id = 1,
827 			.module_bit = OMAP3430_EN_I2C3_SHIFT,
828 			.idlest_reg_id = 1,
829 			.idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
830 		},
831 	},
832 	.class		= &i2c_class,
833 	.dev_attr	= &i2c3_dev_attr,
834 };
835 
836 /*
837  * 'gpio' class
838  * general purpose io module
839  */
840 
841 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
842 	.rev_offs	= 0x0000,
843 	.sysc_offs	= 0x0010,
844 	.syss_offs	= 0x0014,
845 	.sysc_flags	= (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
846 			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
847 			   SYSS_HAS_RESET_STATUS),
848 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
849 	.sysc_fields    = &omap_hwmod_sysc_type1,
850 };
851 
852 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
853 	.name = "gpio",
854 	.sysc = &omap3xxx_gpio_sysc,
855 	.rev = 1,
856 };
857 
858 /* gpio_dev_attr */
859 static struct omap_gpio_dev_attr gpio_dev_attr = {
860 	.bank_width = 32,
861 	.dbck_flag = true,
862 };
863 
864 /* gpio1 */
865 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
866 	{ .role = "dbclk", .clk = "gpio1_dbck", },
867 };
868 
869 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
870 	.name		= "gpio1",
871 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
872 	.mpu_irqs	= omap2_gpio1_irqs,
873 	.main_clk	= "gpio1_ick",
874 	.opt_clks	= gpio1_opt_clks,
875 	.opt_clks_cnt	= ARRAY_SIZE(gpio1_opt_clks),
876 	.prcm		= {
877 		.omap2 = {
878 			.prcm_reg_id = 1,
879 			.module_bit = OMAP3430_EN_GPIO1_SHIFT,
880 			.module_offs = WKUP_MOD,
881 			.idlest_reg_id = 1,
882 			.idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
883 		},
884 	},
885 	.class		= &omap3xxx_gpio_hwmod_class,
886 	.dev_attr	= &gpio_dev_attr,
887 };
888 
889 /* gpio2 */
890 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
891 	{ .role = "dbclk", .clk = "gpio2_dbck", },
892 };
893 
894 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
895 	.name		= "gpio2",
896 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
897 	.mpu_irqs	= omap2_gpio2_irqs,
898 	.main_clk	= "gpio2_ick",
899 	.opt_clks	= gpio2_opt_clks,
900 	.opt_clks_cnt	= ARRAY_SIZE(gpio2_opt_clks),
901 	.prcm		= {
902 		.omap2 = {
903 			.prcm_reg_id = 1,
904 			.module_bit = OMAP3430_EN_GPIO2_SHIFT,
905 			.module_offs = OMAP3430_PER_MOD,
906 			.idlest_reg_id = 1,
907 			.idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
908 		},
909 	},
910 	.class		= &omap3xxx_gpio_hwmod_class,
911 	.dev_attr	= &gpio_dev_attr,
912 };
913 
914 /* gpio3 */
915 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
916 	{ .role = "dbclk", .clk = "gpio3_dbck", },
917 };
918 
919 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
920 	.name		= "gpio3",
921 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
922 	.mpu_irqs	= omap2_gpio3_irqs,
923 	.main_clk	= "gpio3_ick",
924 	.opt_clks	= gpio3_opt_clks,
925 	.opt_clks_cnt	= ARRAY_SIZE(gpio3_opt_clks),
926 	.prcm		= {
927 		.omap2 = {
928 			.prcm_reg_id = 1,
929 			.module_bit = OMAP3430_EN_GPIO3_SHIFT,
930 			.module_offs = OMAP3430_PER_MOD,
931 			.idlest_reg_id = 1,
932 			.idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
933 		},
934 	},
935 	.class		= &omap3xxx_gpio_hwmod_class,
936 	.dev_attr	= &gpio_dev_attr,
937 };
938 
939 /* gpio4 */
940 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
941 	{ .role = "dbclk", .clk = "gpio4_dbck", },
942 };
943 
944 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
945 	.name		= "gpio4",
946 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
947 	.mpu_irqs	= omap2_gpio4_irqs,
948 	.main_clk	= "gpio4_ick",
949 	.opt_clks	= gpio4_opt_clks,
950 	.opt_clks_cnt	= ARRAY_SIZE(gpio4_opt_clks),
951 	.prcm		= {
952 		.omap2 = {
953 			.prcm_reg_id = 1,
954 			.module_bit = OMAP3430_EN_GPIO4_SHIFT,
955 			.module_offs = OMAP3430_PER_MOD,
956 			.idlest_reg_id = 1,
957 			.idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
958 		},
959 	},
960 	.class		= &omap3xxx_gpio_hwmod_class,
961 	.dev_attr	= &gpio_dev_attr,
962 };
963 
964 /* gpio5 */
965 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
966 	{ .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
967 	{ .irq = -1 }
968 };
969 
970 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
971 	{ .role = "dbclk", .clk = "gpio5_dbck", },
972 };
973 
974 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
975 	.name		= "gpio5",
976 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
977 	.mpu_irqs	= omap3xxx_gpio5_irqs,
978 	.main_clk	= "gpio5_ick",
979 	.opt_clks	= gpio5_opt_clks,
980 	.opt_clks_cnt	= ARRAY_SIZE(gpio5_opt_clks),
981 	.prcm		= {
982 		.omap2 = {
983 			.prcm_reg_id = 1,
984 			.module_bit = OMAP3430_EN_GPIO5_SHIFT,
985 			.module_offs = OMAP3430_PER_MOD,
986 			.idlest_reg_id = 1,
987 			.idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
988 		},
989 	},
990 	.class		= &omap3xxx_gpio_hwmod_class,
991 	.dev_attr	= &gpio_dev_attr,
992 };
993 
994 /* gpio6 */
995 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
996 	{ .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
997 	{ .irq = -1 }
998 };
999 
1000 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1001 	{ .role = "dbclk", .clk = "gpio6_dbck", },
1002 };
1003 
1004 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1005 	.name		= "gpio6",
1006 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1007 	.mpu_irqs	= omap3xxx_gpio6_irqs,
1008 	.main_clk	= "gpio6_ick",
1009 	.opt_clks	= gpio6_opt_clks,
1010 	.opt_clks_cnt	= ARRAY_SIZE(gpio6_opt_clks),
1011 	.prcm		= {
1012 		.omap2 = {
1013 			.prcm_reg_id = 1,
1014 			.module_bit = OMAP3430_EN_GPIO6_SHIFT,
1015 			.module_offs = OMAP3430_PER_MOD,
1016 			.idlest_reg_id = 1,
1017 			.idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
1018 		},
1019 	},
1020 	.class		= &omap3xxx_gpio_hwmod_class,
1021 	.dev_attr	= &gpio_dev_attr,
1022 };
1023 
1024 /* dma attributes */
1025 static struct omap_dma_dev_attr dma_dev_attr = {
1026 	.dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1027 				IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1028 	.lch_count = 32,
1029 };
1030 
1031 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1032 	.rev_offs	= 0x0000,
1033 	.sysc_offs	= 0x002c,
1034 	.syss_offs	= 0x0028,
1035 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1036 			   SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1037 			   SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
1038 			   SYSS_HAS_RESET_STATUS),
1039 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1040 			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1041 	.sysc_fields	= &omap_hwmod_sysc_type1,
1042 };
1043 
1044 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1045 	.name = "dma",
1046 	.sysc = &omap3xxx_dma_sysc,
1047 };
1048 
1049 /* dma_system */
1050 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1051 	.name		= "dma",
1052 	.class		= &omap3xxx_dma_hwmod_class,
1053 	.mpu_irqs	= omap2_dma_system_irqs,
1054 	.main_clk	= "core_l3_ick",
1055 	.prcm = {
1056 		.omap2 = {
1057 			.module_offs		= CORE_MOD,
1058 			.prcm_reg_id		= 1,
1059 			.module_bit		= OMAP3430_ST_SDMA_SHIFT,
1060 			.idlest_reg_id		= 1,
1061 			.idlest_idle_bit	= OMAP3430_ST_SDMA_SHIFT,
1062 		},
1063 	},
1064 	.dev_attr	= &dma_dev_attr,
1065 	.flags		= HWMOD_NO_IDLEST,
1066 };
1067 
1068 /*
1069  * 'mcbsp' class
1070  * multi channel buffered serial port controller
1071  */
1072 
1073 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
1074 	.sysc_offs	= 0x008c,
1075 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1076 			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1077 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1078 	.sysc_fields	= &omap_hwmod_sysc_type1,
1079 	.clockact	= 0x2,
1080 };
1081 
1082 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1083 	.name = "mcbsp",
1084 	.sysc = &omap3xxx_mcbsp_sysc,
1085 	.rev  = MCBSP_CONFIG_TYPE3,
1086 };
1087 
1088 /* McBSP functional clock mapping */
1089 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
1090 	{ .role = "pad_fck", .clk = "mcbsp_clks" },
1091 	{ .role = "prcm_fck", .clk = "core_96m_fck" },
1092 };
1093 
1094 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
1095 	{ .role = "pad_fck", .clk = "mcbsp_clks" },
1096 	{ .role = "prcm_fck", .clk = "per_96m_fck" },
1097 };
1098 
1099 /* mcbsp1 */
1100 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1101 	{ .name = "common", .irq = 16 },
1102 	{ .name = "tx", .irq = 59 },
1103 	{ .name = "rx", .irq = 60 },
1104 	{ .irq = -1 }
1105 };
1106 
1107 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1108 	.name		= "mcbsp1",
1109 	.class		= &omap3xxx_mcbsp_hwmod_class,
1110 	.mpu_irqs	= omap3xxx_mcbsp1_irqs,
1111 	.sdma_reqs	= omap2_mcbsp1_sdma_reqs,
1112 	.main_clk	= "mcbsp1_fck",
1113 	.prcm		= {
1114 		.omap2 = {
1115 			.prcm_reg_id = 1,
1116 			.module_bit = OMAP3430_EN_MCBSP1_SHIFT,
1117 			.module_offs = CORE_MOD,
1118 			.idlest_reg_id = 1,
1119 			.idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1120 		},
1121 	},
1122 	.opt_clks	= mcbsp15_opt_clks,
1123 	.opt_clks_cnt	= ARRAY_SIZE(mcbsp15_opt_clks),
1124 };
1125 
1126 /* mcbsp2 */
1127 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
1128 	{ .name = "common", .irq = 17 },
1129 	{ .name = "tx", .irq = 62 },
1130 	{ .name = "rx", .irq = 63 },
1131 	{ .irq = -1 }
1132 };
1133 
1134 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1135 	.sidetone	= "mcbsp2_sidetone",
1136 };
1137 
1138 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1139 	.name		= "mcbsp2",
1140 	.class		= &omap3xxx_mcbsp_hwmod_class,
1141 	.mpu_irqs	= omap3xxx_mcbsp2_irqs,
1142 	.sdma_reqs	= omap2_mcbsp2_sdma_reqs,
1143 	.main_clk	= "mcbsp2_fck",
1144 	.prcm		= {
1145 		.omap2 = {
1146 			.prcm_reg_id = 1,
1147 			.module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1148 			.module_offs = OMAP3430_PER_MOD,
1149 			.idlest_reg_id = 1,
1150 			.idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1151 		},
1152 	},
1153 	.opt_clks	= mcbsp234_opt_clks,
1154 	.opt_clks_cnt	= ARRAY_SIZE(mcbsp234_opt_clks),
1155 	.dev_attr	= &omap34xx_mcbsp2_dev_attr,
1156 };
1157 
1158 /* mcbsp3 */
1159 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
1160 	{ .name = "common", .irq = 22 },
1161 	{ .name = "tx", .irq = 89 },
1162 	{ .name = "rx", .irq = 90 },
1163 	{ .irq = -1 }
1164 };
1165 
1166 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1167 	.sidetone	= "mcbsp3_sidetone",
1168 };
1169 
1170 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1171 	.name		= "mcbsp3",
1172 	.class		= &omap3xxx_mcbsp_hwmod_class,
1173 	.mpu_irqs	= omap3xxx_mcbsp3_irqs,
1174 	.sdma_reqs	= omap2_mcbsp3_sdma_reqs,
1175 	.main_clk	= "mcbsp3_fck",
1176 	.prcm		= {
1177 		.omap2 = {
1178 			.prcm_reg_id = 1,
1179 			.module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1180 			.module_offs = OMAP3430_PER_MOD,
1181 			.idlest_reg_id = 1,
1182 			.idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1183 		},
1184 	},
1185 	.opt_clks	= mcbsp234_opt_clks,
1186 	.opt_clks_cnt	= ARRAY_SIZE(mcbsp234_opt_clks),
1187 	.dev_attr	= &omap34xx_mcbsp3_dev_attr,
1188 };
1189 
1190 /* mcbsp4 */
1191 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
1192 	{ .name = "common", .irq = 23 },
1193 	{ .name = "tx", .irq = 54 },
1194 	{ .name = "rx", .irq = 55 },
1195 	{ .irq = -1 }
1196 };
1197 
1198 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
1199 	{ .name = "rx", .dma_req = 20 },
1200 	{ .name = "tx", .dma_req = 19 },
1201 	{ .dma_req = -1 }
1202 };
1203 
1204 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1205 	.name		= "mcbsp4",
1206 	.class		= &omap3xxx_mcbsp_hwmod_class,
1207 	.mpu_irqs	= omap3xxx_mcbsp4_irqs,
1208 	.sdma_reqs	= omap3xxx_mcbsp4_sdma_chs,
1209 	.main_clk	= "mcbsp4_fck",
1210 	.prcm		= {
1211 		.omap2 = {
1212 			.prcm_reg_id = 1,
1213 			.module_bit = OMAP3430_EN_MCBSP4_SHIFT,
1214 			.module_offs = OMAP3430_PER_MOD,
1215 			.idlest_reg_id = 1,
1216 			.idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1217 		},
1218 	},
1219 	.opt_clks	= mcbsp234_opt_clks,
1220 	.opt_clks_cnt	= ARRAY_SIZE(mcbsp234_opt_clks),
1221 };
1222 
1223 /* mcbsp5 */
1224 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
1225 	{ .name = "common", .irq = 27 },
1226 	{ .name = "tx", .irq = 81 },
1227 	{ .name = "rx", .irq = 82 },
1228 	{ .irq = -1 }
1229 };
1230 
1231 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
1232 	{ .name = "rx", .dma_req = 22 },
1233 	{ .name = "tx", .dma_req = 21 },
1234 	{ .dma_req = -1 }
1235 };
1236 
1237 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1238 	.name		= "mcbsp5",
1239 	.class		= &omap3xxx_mcbsp_hwmod_class,
1240 	.mpu_irqs	= omap3xxx_mcbsp5_irqs,
1241 	.sdma_reqs	= omap3xxx_mcbsp5_sdma_chs,
1242 	.main_clk	= "mcbsp5_fck",
1243 	.prcm		= {
1244 		.omap2 = {
1245 			.prcm_reg_id = 1,
1246 			.module_bit = OMAP3430_EN_MCBSP5_SHIFT,
1247 			.module_offs = CORE_MOD,
1248 			.idlest_reg_id = 1,
1249 			.idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
1250 		},
1251 	},
1252 	.opt_clks	= mcbsp15_opt_clks,
1253 	.opt_clks_cnt	= ARRAY_SIZE(mcbsp15_opt_clks),
1254 };
1255 
1256 /* 'mcbsp sidetone' class */
1257 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
1258 	.sysc_offs	= 0x0010,
1259 	.sysc_flags	= SYSC_HAS_AUTOIDLE,
1260 	.sysc_fields	= &omap_hwmod_sysc_type1,
1261 };
1262 
1263 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1264 	.name = "mcbsp_sidetone",
1265 	.sysc = &omap3xxx_mcbsp_sidetone_sysc,
1266 };
1267 
1268 /* mcbsp2_sidetone */
1269 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
1270 	{ .name = "irq", .irq = 4 },
1271 	{ .irq = -1 }
1272 };
1273 
1274 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1275 	.name		= "mcbsp2_sidetone",
1276 	.class		= &omap3xxx_mcbsp_sidetone_hwmod_class,
1277 	.mpu_irqs	= omap3xxx_mcbsp2_sidetone_irqs,
1278 	.main_clk	= "mcbsp2_fck",
1279 	.prcm		= {
1280 		.omap2 = {
1281 			.prcm_reg_id = 1,
1282 			 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1283 			.module_offs = OMAP3430_PER_MOD,
1284 			.idlest_reg_id = 1,
1285 			.idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1286 		},
1287 	},
1288 };
1289 
1290 /* mcbsp3_sidetone */
1291 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
1292 	{ .name = "irq", .irq = 5 },
1293 	{ .irq = -1 }
1294 };
1295 
1296 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1297 	.name		= "mcbsp3_sidetone",
1298 	.class		= &omap3xxx_mcbsp_sidetone_hwmod_class,
1299 	.mpu_irqs	= omap3xxx_mcbsp3_sidetone_irqs,
1300 	.main_clk	= "mcbsp3_fck",
1301 	.prcm		= {
1302 		.omap2 = {
1303 			.prcm_reg_id = 1,
1304 			.module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1305 			.module_offs = OMAP3430_PER_MOD,
1306 			.idlest_reg_id = 1,
1307 			.idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1308 		},
1309 	},
1310 };
1311 
1312 /* SR common */
1313 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1314 	.clkact_shift	= 20,
1315 };
1316 
1317 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1318 	.sysc_offs	= 0x24,
1319 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1320 	.clockact	= CLOCKACT_TEST_ICLK,
1321 	.sysc_fields	= &omap34xx_sr_sysc_fields,
1322 };
1323 
1324 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1325 	.name = "smartreflex",
1326 	.sysc = &omap34xx_sr_sysc,
1327 	.rev  = 1,
1328 };
1329 
1330 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1331 	.sidle_shift	= 24,
1332 	.enwkup_shift	= 26,
1333 };
1334 
1335 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1336 	.sysc_offs	= 0x38,
1337 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1338 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1339 			SYSC_NO_CACHE),
1340 	.sysc_fields	= &omap36xx_sr_sysc_fields,
1341 };
1342 
1343 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1344 	.name = "smartreflex",
1345 	.sysc = &omap36xx_sr_sysc,
1346 	.rev  = 2,
1347 };
1348 
1349 /* SR1 */
1350 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1351 	.sensor_voltdm_name   = "mpu_iva",
1352 };
1353 
1354 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
1355 	{ .irq = 18 },
1356 	{ .irq = -1 }
1357 };
1358 
1359 static struct omap_hwmod omap34xx_sr1_hwmod = {
1360 	.name		= "smartreflex_mpu_iva",
1361 	.class		= &omap34xx_smartreflex_hwmod_class,
1362 	.main_clk	= "sr1_fck",
1363 	.prcm		= {
1364 		.omap2 = {
1365 			.prcm_reg_id = 1,
1366 			.module_bit = OMAP3430_EN_SR1_SHIFT,
1367 			.module_offs = WKUP_MOD,
1368 			.idlest_reg_id = 1,
1369 			.idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1370 		},
1371 	},
1372 	.dev_attr	= &sr1_dev_attr,
1373 	.mpu_irqs	= omap3_smartreflex_mpu_irqs,
1374 	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
1375 };
1376 
1377 static struct omap_hwmod omap36xx_sr1_hwmod = {
1378 	.name		= "smartreflex_mpu_iva",
1379 	.class		= &omap36xx_smartreflex_hwmod_class,
1380 	.main_clk	= "sr1_fck",
1381 	.prcm		= {
1382 		.omap2 = {
1383 			.prcm_reg_id = 1,
1384 			.module_bit = OMAP3430_EN_SR1_SHIFT,
1385 			.module_offs = WKUP_MOD,
1386 			.idlest_reg_id = 1,
1387 			.idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1388 		},
1389 	},
1390 	.dev_attr	= &sr1_dev_attr,
1391 	.mpu_irqs	= omap3_smartreflex_mpu_irqs,
1392 };
1393 
1394 /* SR2 */
1395 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1396 	.sensor_voltdm_name	= "core",
1397 };
1398 
1399 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
1400 	{ .irq = 19 },
1401 	{ .irq = -1 }
1402 };
1403 
1404 static struct omap_hwmod omap34xx_sr2_hwmod = {
1405 	.name		= "smartreflex_core",
1406 	.class		= &omap34xx_smartreflex_hwmod_class,
1407 	.main_clk	= "sr2_fck",
1408 	.prcm		= {
1409 		.omap2 = {
1410 			.prcm_reg_id = 1,
1411 			.module_bit = OMAP3430_EN_SR2_SHIFT,
1412 			.module_offs = WKUP_MOD,
1413 			.idlest_reg_id = 1,
1414 			.idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1415 		},
1416 	},
1417 	.dev_attr	= &sr2_dev_attr,
1418 	.mpu_irqs	= omap3_smartreflex_core_irqs,
1419 	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
1420 };
1421 
1422 static struct omap_hwmod omap36xx_sr2_hwmod = {
1423 	.name		= "smartreflex_core",
1424 	.class		= &omap36xx_smartreflex_hwmod_class,
1425 	.main_clk	= "sr2_fck",
1426 	.prcm		= {
1427 		.omap2 = {
1428 			.prcm_reg_id = 1,
1429 			.module_bit = OMAP3430_EN_SR2_SHIFT,
1430 			.module_offs = WKUP_MOD,
1431 			.idlest_reg_id = 1,
1432 			.idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1433 		},
1434 	},
1435 	.dev_attr	= &sr2_dev_attr,
1436 	.mpu_irqs	= omap3_smartreflex_core_irqs,
1437 };
1438 
1439 /*
1440  * 'mailbox' class
1441  * mailbox module allowing communication between the on-chip processors
1442  * using a queued mailbox-interrupt mechanism.
1443  */
1444 
1445 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1446 	.rev_offs	= 0x000,
1447 	.sysc_offs	= 0x010,
1448 	.syss_offs	= 0x014,
1449 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1450 				SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1451 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1452 	.sysc_fields	= &omap_hwmod_sysc_type1,
1453 };
1454 
1455 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1456 	.name = "mailbox",
1457 	.sysc = &omap3xxx_mailbox_sysc,
1458 };
1459 
1460 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
1461 	{ .irq = 26 },
1462 	{ .irq = -1 }
1463 };
1464 
1465 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1466 	.name		= "mailbox",
1467 	.class		= &omap3xxx_mailbox_hwmod_class,
1468 	.mpu_irqs	= omap3xxx_mailbox_irqs,
1469 	.main_clk	= "mailboxes_ick",
1470 	.prcm		= {
1471 		.omap2 = {
1472 			.prcm_reg_id = 1,
1473 			.module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1474 			.module_offs = CORE_MOD,
1475 			.idlest_reg_id = 1,
1476 			.idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1477 		},
1478 	},
1479 };
1480 
1481 /*
1482  * 'mcspi' class
1483  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1484  * bus
1485  */
1486 
1487 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1488 	.rev_offs	= 0x0000,
1489 	.sysc_offs	= 0x0010,
1490 	.syss_offs	= 0x0014,
1491 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1492 				SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1493 				SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1494 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1495 	.sysc_fields    = &omap_hwmod_sysc_type1,
1496 };
1497 
1498 static struct omap_hwmod_class omap34xx_mcspi_class = {
1499 	.name = "mcspi",
1500 	.sysc = &omap34xx_mcspi_sysc,
1501 	.rev = OMAP3_MCSPI_REV,
1502 };
1503 
1504 /* mcspi1 */
1505 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1506 	.num_chipselect = 4,
1507 };
1508 
1509 static struct omap_hwmod omap34xx_mcspi1 = {
1510 	.name		= "mcspi1",
1511 	.mpu_irqs	= omap2_mcspi1_mpu_irqs,
1512 	.sdma_reqs	= omap2_mcspi1_sdma_reqs,
1513 	.main_clk	= "mcspi1_fck",
1514 	.prcm		= {
1515 		.omap2 = {
1516 			.module_offs = CORE_MOD,
1517 			.prcm_reg_id = 1,
1518 			.module_bit = OMAP3430_EN_MCSPI1_SHIFT,
1519 			.idlest_reg_id = 1,
1520 			.idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1521 		},
1522 	},
1523 	.class		= &omap34xx_mcspi_class,
1524 	.dev_attr       = &omap_mcspi1_dev_attr,
1525 };
1526 
1527 /* mcspi2 */
1528 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1529 	.num_chipselect = 2,
1530 };
1531 
1532 static struct omap_hwmod omap34xx_mcspi2 = {
1533 	.name		= "mcspi2",
1534 	.mpu_irqs	= omap2_mcspi2_mpu_irqs,
1535 	.sdma_reqs	= omap2_mcspi2_sdma_reqs,
1536 	.main_clk	= "mcspi2_fck",
1537 	.prcm		= {
1538 		.omap2 = {
1539 			.module_offs = CORE_MOD,
1540 			.prcm_reg_id = 1,
1541 			.module_bit = OMAP3430_EN_MCSPI2_SHIFT,
1542 			.idlest_reg_id = 1,
1543 			.idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1544 		},
1545 	},
1546 	.class		= &omap34xx_mcspi_class,
1547 	.dev_attr       = &omap_mcspi2_dev_attr,
1548 };
1549 
1550 /* mcspi3 */
1551 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
1552 	{ .name = "irq", .irq = 91 }, /* 91 */
1553 	{ .irq = -1 }
1554 };
1555 
1556 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
1557 	{ .name = "tx0", .dma_req = 15 },
1558 	{ .name = "rx0", .dma_req = 16 },
1559 	{ .name = "tx1", .dma_req = 23 },
1560 	{ .name = "rx1", .dma_req = 24 },
1561 	{ .dma_req = -1 }
1562 };
1563 
1564 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1565 	.num_chipselect = 2,
1566 };
1567 
1568 static struct omap_hwmod omap34xx_mcspi3 = {
1569 	.name		= "mcspi3",
1570 	.mpu_irqs	= omap34xx_mcspi3_mpu_irqs,
1571 	.sdma_reqs	= omap34xx_mcspi3_sdma_reqs,
1572 	.main_clk	= "mcspi3_fck",
1573 	.prcm		= {
1574 		.omap2 = {
1575 			.module_offs = CORE_MOD,
1576 			.prcm_reg_id = 1,
1577 			.module_bit = OMAP3430_EN_MCSPI3_SHIFT,
1578 			.idlest_reg_id = 1,
1579 			.idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1580 		},
1581 	},
1582 	.class		= &omap34xx_mcspi_class,
1583 	.dev_attr       = &omap_mcspi3_dev_attr,
1584 };
1585 
1586 /* mcspi4 */
1587 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
1588 	{ .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
1589 	{ .irq = -1 }
1590 };
1591 
1592 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
1593 	{ .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
1594 	{ .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
1595 	{ .dma_req = -1 }
1596 };
1597 
1598 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1599 	.num_chipselect = 1,
1600 };
1601 
1602 static struct omap_hwmod omap34xx_mcspi4 = {
1603 	.name		= "mcspi4",
1604 	.mpu_irqs	= omap34xx_mcspi4_mpu_irqs,
1605 	.sdma_reqs	= omap34xx_mcspi4_sdma_reqs,
1606 	.main_clk	= "mcspi4_fck",
1607 	.prcm		= {
1608 		.omap2 = {
1609 			.module_offs = CORE_MOD,
1610 			.prcm_reg_id = 1,
1611 			.module_bit = OMAP3430_EN_MCSPI4_SHIFT,
1612 			.idlest_reg_id = 1,
1613 			.idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1614 		},
1615 	},
1616 	.class		= &omap34xx_mcspi_class,
1617 	.dev_attr       = &omap_mcspi4_dev_attr,
1618 };
1619 
1620 /* usbhsotg */
1621 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1622 	.rev_offs	= 0x0400,
1623 	.sysc_offs	= 0x0404,
1624 	.syss_offs	= 0x0408,
1625 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1626 			  SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1627 			  SYSC_HAS_AUTOIDLE),
1628 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1629 			  MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1630 	.sysc_fields	= &omap_hwmod_sysc_type1,
1631 };
1632 
1633 static struct omap_hwmod_class usbotg_class = {
1634 	.name = "usbotg",
1635 	.sysc = &omap3xxx_usbhsotg_sysc,
1636 };
1637 
1638 /* usb_otg_hs */
1639 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
1640 
1641 	{ .name = "mc", .irq = 92 },
1642 	{ .name = "dma", .irq = 93 },
1643 	{ .irq = -1 }
1644 };
1645 
1646 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1647 	.name		= "usb_otg_hs",
1648 	.mpu_irqs	= omap3xxx_usbhsotg_mpu_irqs,
1649 	.main_clk	= "hsotgusb_ick",
1650 	.prcm		= {
1651 		.omap2 = {
1652 			.prcm_reg_id = 1,
1653 			.module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1654 			.module_offs = CORE_MOD,
1655 			.idlest_reg_id = 1,
1656 			.idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1657 			.idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
1658 		},
1659 	},
1660 	.class		= &usbotg_class,
1661 
1662 	/*
1663 	 * Erratum ID: i479  idle_req / idle_ack mechanism potentially
1664 	 * broken when autoidle is enabled
1665 	 * workaround is to disable the autoidle bit at module level.
1666 	 */
1667 	.flags		= HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
1668 				| HWMOD_SWSUP_MSTANDBY,
1669 };
1670 
1671 /* usb_otg_hs */
1672 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
1673 	{ .name = "mc", .irq = 71 },
1674 	{ .irq = -1 }
1675 };
1676 
1677 static struct omap_hwmod_class am35xx_usbotg_class = {
1678 	.name = "am35xx_usbotg",
1679 };
1680 
1681 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1682 	.name		= "am35x_otg_hs",
1683 	.mpu_irqs	= am35xx_usbhsotg_mpu_irqs,
1684 	.main_clk	= "hsotgusb_fck",
1685 	.class		= &am35xx_usbotg_class,
1686 	.flags		= HWMOD_NO_IDLEST,
1687 };
1688 
1689 /* MMC/SD/SDIO common */
1690 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1691 	.rev_offs	= 0x1fc,
1692 	.sysc_offs	= 0x10,
1693 	.syss_offs	= 0x14,
1694 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1695 			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1696 			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1697 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1698 	.sysc_fields    = &omap_hwmod_sysc_type1,
1699 };
1700 
1701 static struct omap_hwmod_class omap34xx_mmc_class = {
1702 	.name = "mmc",
1703 	.sysc = &omap34xx_mmc_sysc,
1704 };
1705 
1706 /* MMC/SD/SDIO1 */
1707 
1708 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
1709 	{ .irq = 83, },
1710 	{ .irq = -1 }
1711 };
1712 
1713 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
1714 	{ .name = "tx",	.dma_req = 61, },
1715 	{ .name = "rx",	.dma_req = 62, },
1716 	{ .dma_req = -1 }
1717 };
1718 
1719 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1720 	{ .role = "dbck", .clk = "omap_32k_fck", },
1721 };
1722 
1723 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1724 	.flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1725 };
1726 
1727 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1728 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
1729 	.flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1730 		  OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1731 };
1732 
1733 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1734 	.name		= "mmc1",
1735 	.mpu_irqs	= omap34xx_mmc1_mpu_irqs,
1736 	.sdma_reqs	= omap34xx_mmc1_sdma_reqs,
1737 	.opt_clks	= omap34xx_mmc1_opt_clks,
1738 	.opt_clks_cnt	= ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1739 	.main_clk	= "mmchs1_fck",
1740 	.prcm		= {
1741 		.omap2 = {
1742 			.module_offs = CORE_MOD,
1743 			.prcm_reg_id = 1,
1744 			.module_bit = OMAP3430_EN_MMC1_SHIFT,
1745 			.idlest_reg_id = 1,
1746 			.idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1747 		},
1748 	},
1749 	.dev_attr	= &mmc1_pre_es3_dev_attr,
1750 	.class		= &omap34xx_mmc_class,
1751 };
1752 
1753 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1754 	.name		= "mmc1",
1755 	.mpu_irqs	= omap34xx_mmc1_mpu_irqs,
1756 	.sdma_reqs	= omap34xx_mmc1_sdma_reqs,
1757 	.opt_clks	= omap34xx_mmc1_opt_clks,
1758 	.opt_clks_cnt	= ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1759 	.main_clk	= "mmchs1_fck",
1760 	.prcm		= {
1761 		.omap2 = {
1762 			.module_offs = CORE_MOD,
1763 			.prcm_reg_id = 1,
1764 			.module_bit = OMAP3430_EN_MMC1_SHIFT,
1765 			.idlest_reg_id = 1,
1766 			.idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1767 		},
1768 	},
1769 	.dev_attr	= &mmc1_dev_attr,
1770 	.class		= &omap34xx_mmc_class,
1771 };
1772 
1773 /* MMC/SD/SDIO2 */
1774 
1775 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
1776 	{ .irq = INT_24XX_MMC2_IRQ, },
1777 	{ .irq = -1 }
1778 };
1779 
1780 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
1781 	{ .name = "tx",	.dma_req = 47, },
1782 	{ .name = "rx",	.dma_req = 48, },
1783 	{ .dma_req = -1 }
1784 };
1785 
1786 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1787 	{ .role = "dbck", .clk = "omap_32k_fck", },
1788 };
1789 
1790 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1791 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
1792 	.flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1793 };
1794 
1795 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1796 	.name		= "mmc2",
1797 	.mpu_irqs	= omap34xx_mmc2_mpu_irqs,
1798 	.sdma_reqs	= omap34xx_mmc2_sdma_reqs,
1799 	.opt_clks	= omap34xx_mmc2_opt_clks,
1800 	.opt_clks_cnt	= ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1801 	.main_clk	= "mmchs2_fck",
1802 	.prcm		= {
1803 		.omap2 = {
1804 			.module_offs = CORE_MOD,
1805 			.prcm_reg_id = 1,
1806 			.module_bit = OMAP3430_EN_MMC2_SHIFT,
1807 			.idlest_reg_id = 1,
1808 			.idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1809 		},
1810 	},
1811 	.dev_attr	= &mmc2_pre_es3_dev_attr,
1812 	.class		= &omap34xx_mmc_class,
1813 };
1814 
1815 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1816 	.name		= "mmc2",
1817 	.mpu_irqs	= omap34xx_mmc2_mpu_irqs,
1818 	.sdma_reqs	= omap34xx_mmc2_sdma_reqs,
1819 	.opt_clks	= omap34xx_mmc2_opt_clks,
1820 	.opt_clks_cnt	= ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1821 	.main_clk	= "mmchs2_fck",
1822 	.prcm		= {
1823 		.omap2 = {
1824 			.module_offs = CORE_MOD,
1825 			.prcm_reg_id = 1,
1826 			.module_bit = OMAP3430_EN_MMC2_SHIFT,
1827 			.idlest_reg_id = 1,
1828 			.idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1829 		},
1830 	},
1831 	.class		= &omap34xx_mmc_class,
1832 };
1833 
1834 /* MMC/SD/SDIO3 */
1835 
1836 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
1837 	{ .irq = 94, },
1838 	{ .irq = -1 }
1839 };
1840 
1841 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
1842 	{ .name = "tx",	.dma_req = 77, },
1843 	{ .name = "rx",	.dma_req = 78, },
1844 	{ .dma_req = -1 }
1845 };
1846 
1847 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1848 	{ .role = "dbck", .clk = "omap_32k_fck", },
1849 };
1850 
1851 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1852 	.name		= "mmc3",
1853 	.mpu_irqs	= omap34xx_mmc3_mpu_irqs,
1854 	.sdma_reqs	= omap34xx_mmc3_sdma_reqs,
1855 	.opt_clks	= omap34xx_mmc3_opt_clks,
1856 	.opt_clks_cnt	= ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1857 	.main_clk	= "mmchs3_fck",
1858 	.prcm		= {
1859 		.omap2 = {
1860 			.prcm_reg_id = 1,
1861 			.module_bit = OMAP3430_EN_MMC3_SHIFT,
1862 			.idlest_reg_id = 1,
1863 			.idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1864 		},
1865 	},
1866 	.class		= &omap34xx_mmc_class,
1867 };
1868 
1869 /*
1870  * 'usb_host_hs' class
1871  * high-speed multi-port usb host controller
1872  */
1873 
1874 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1875 	.rev_offs	= 0x0000,
1876 	.sysc_offs	= 0x0010,
1877 	.syss_offs	= 0x0014,
1878 	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1879 			   SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1880 			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1881 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1882 			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1883 	.sysc_fields	= &omap_hwmod_sysc_type1,
1884 };
1885 
1886 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1887 	.name = "usb_host_hs",
1888 	.sysc = &omap3xxx_usb_host_hs_sysc,
1889 };
1890 
1891 static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
1892 	  { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
1893 };
1894 
1895 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
1896 	{ .name = "ohci-irq", .irq = 76 },
1897 	{ .name = "ehci-irq", .irq = 77 },
1898 	{ .irq = -1 }
1899 };
1900 
1901 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1902 	.name		= "usb_host_hs",
1903 	.class		= &omap3xxx_usb_host_hs_hwmod_class,
1904 	.clkdm_name	= "l3_init_clkdm",
1905 	.mpu_irqs	= omap3xxx_usb_host_hs_irqs,
1906 	.main_clk	= "usbhost_48m_fck",
1907 	.prcm = {
1908 		.omap2 = {
1909 			.module_offs = OMAP3430ES2_USBHOST_MOD,
1910 			.prcm_reg_id = 1,
1911 			.module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
1912 			.idlest_reg_id = 1,
1913 			.idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1914 			.idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
1915 		},
1916 	},
1917 	.opt_clks	= omap3xxx_usb_host_hs_opt_clks,
1918 	.opt_clks_cnt	= ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
1919 
1920 	/*
1921 	 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1922 	 * id: i660
1923 	 *
1924 	 * Description:
1925 	 * In the following configuration :
1926 	 * - USBHOST module is set to smart-idle mode
1927 	 * - PRCM asserts idle_req to the USBHOST module ( This typically
1928 	 *   happens when the system is going to a low power mode : all ports
1929 	 *   have been suspended, the master part of the USBHOST module has
1930 	 *   entered the standby state, and SW has cut the functional clocks)
1931 	 * - an USBHOST interrupt occurs before the module is able to answer
1932 	 *   idle_ack, typically a remote wakeup IRQ.
1933 	 * Then the USB HOST module will enter a deadlock situation where it
1934 	 * is no more accessible nor functional.
1935 	 *
1936 	 * Workaround:
1937 	 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1938 	 */
1939 
1940 	/*
1941 	 * Errata: USB host EHCI may stall when entering smart-standby mode
1942 	 * Id: i571
1943 	 *
1944 	 * Description:
1945 	 * When the USBHOST module is set to smart-standby mode, and when it is
1946 	 * ready to enter the standby state (i.e. all ports are suspended and
1947 	 * all attached devices are in suspend mode), then it can wrongly assert
1948 	 * the Mstandby signal too early while there are still some residual OCP
1949 	 * transactions ongoing. If this condition occurs, the internal state
1950 	 * machine may go to an undefined state and the USB link may be stuck
1951 	 * upon the next resume.
1952 	 *
1953 	 * Workaround:
1954 	 * Don't use smart standby; use only force standby,
1955 	 * hence HWMOD_SWSUP_MSTANDBY
1956 	 */
1957 
1958 	/*
1959 	 * During system boot; If the hwmod framework resets the module
1960 	 * the module will have smart idle settings; which can lead to deadlock
1961 	 * (above Errata Id:i660); so, dont reset the module during boot;
1962 	 * Use HWMOD_INIT_NO_RESET.
1963 	 */
1964 
1965 	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
1966 			  HWMOD_INIT_NO_RESET,
1967 };
1968 
1969 /*
1970  * 'usb_tll_hs' class
1971  * usb_tll_hs module is the adapter on the usb_host_hs ports
1972  */
1973 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
1974 	.rev_offs	= 0x0000,
1975 	.sysc_offs	= 0x0010,
1976 	.syss_offs	= 0x0014,
1977 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1978 			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1979 			   SYSC_HAS_AUTOIDLE),
1980 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1981 	.sysc_fields	= &omap_hwmod_sysc_type1,
1982 };
1983 
1984 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
1985 	.name = "usb_tll_hs",
1986 	.sysc = &omap3xxx_usb_tll_hs_sysc,
1987 };
1988 
1989 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
1990 	{ .name = "tll-irq", .irq = 78 },
1991 	{ .irq = -1 }
1992 };
1993 
1994 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
1995 	.name		= "usb_tll_hs",
1996 	.class		= &omap3xxx_usb_tll_hs_hwmod_class,
1997 	.clkdm_name	= "l3_init_clkdm",
1998 	.mpu_irqs	= omap3xxx_usb_tll_hs_irqs,
1999 	.main_clk	= "usbtll_fck",
2000 	.prcm = {
2001 		.omap2 = {
2002 			.module_offs = CORE_MOD,
2003 			.prcm_reg_id = 3,
2004 			.module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
2005 			.idlest_reg_id = 3,
2006 			.idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
2007 		},
2008 	},
2009 };
2010 
2011 static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
2012 	.name		= "hdq1w",
2013 	.mpu_irqs	= omap2_hdq1w_mpu_irqs,
2014 	.main_clk	= "hdq_fck",
2015 	.prcm		= {
2016 		.omap2 = {
2017 			.module_offs = CORE_MOD,
2018 			.prcm_reg_id = 1,
2019 			.module_bit = OMAP3430_EN_HDQ_SHIFT,
2020 			.idlest_reg_id = 1,
2021 			.idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
2022 		},
2023 	},
2024 	.class		= &omap2_hdq1w_class,
2025 };
2026 
2027 /*
2028  * '32K sync counter' class
2029  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
2030  */
2031 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
2032 	.rev_offs	= 0x0000,
2033 	.sysc_offs	= 0x0004,
2034 	.sysc_flags	= SYSC_HAS_SIDLEMODE,
2035 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO),
2036 	.sysc_fields	= &omap_hwmod_sysc_type1,
2037 };
2038 
2039 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
2040 	.name	= "counter",
2041 	.sysc	= &omap3xxx_counter_sysc,
2042 };
2043 
2044 static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
2045 	.name		= "counter_32k",
2046 	.class		= &omap3xxx_counter_hwmod_class,
2047 	.clkdm_name	= "wkup_clkdm",
2048 	.flags		= HWMOD_SWSUP_SIDLE,
2049 	.main_clk	= "wkup_32k_fck",
2050 	.prcm		= {
2051 		.omap2	= {
2052 			.module_offs = WKUP_MOD,
2053 			.prcm_reg_id = 1,
2054 			.module_bit = OMAP3430_ST_32KSYNC_SHIFT,
2055 			.idlest_reg_id = 1,
2056 			.idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
2057 		},
2058 	},
2059 };
2060 
2061 /*
2062  * interfaces
2063  */
2064 
2065 /* L3 -> L4_CORE interface */
2066 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
2067 	.master	= &omap3xxx_l3_main_hwmod,
2068 	.slave	= &omap3xxx_l4_core_hwmod,
2069 	.user	= OCP_USER_MPU | OCP_USER_SDMA,
2070 };
2071 
2072 /* L3 -> L4_PER interface */
2073 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
2074 	.master = &omap3xxx_l3_main_hwmod,
2075 	.slave	= &omap3xxx_l4_per_hwmod,
2076 	.user	= OCP_USER_MPU | OCP_USER_SDMA,
2077 };
2078 
2079 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
2080 	{
2081 		.pa_start	= 0x68000000,
2082 		.pa_end		= 0x6800ffff,
2083 		.flags		= ADDR_TYPE_RT,
2084 	},
2085 	{ }
2086 };
2087 
2088 /* MPU -> L3 interface */
2089 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
2090 	.master   = &omap3xxx_mpu_hwmod,
2091 	.slave    = &omap3xxx_l3_main_hwmod,
2092 	.addr     = omap3xxx_l3_main_addrs,
2093 	.user	= OCP_USER_MPU,
2094 };
2095 
2096 /* DSS -> l3 */
2097 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
2098 	.master		= &omap3430es1_dss_core_hwmod,
2099 	.slave		= &omap3xxx_l3_main_hwmod,
2100 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2101 };
2102 
2103 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
2104 	.master		= &omap3xxx_dss_core_hwmod,
2105 	.slave		= &omap3xxx_l3_main_hwmod,
2106 	.fw = {
2107 		.omap2 = {
2108 			.l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
2109 			.flags	= OMAP_FIREWALL_L3,
2110 		}
2111 	},
2112 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2113 };
2114 
2115 /* l3_core -> usbhsotg interface */
2116 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
2117 	.master		= &omap3xxx_usbhsotg_hwmod,
2118 	.slave		= &omap3xxx_l3_main_hwmod,
2119 	.clk		= "core_l3_ick",
2120 	.user		= OCP_USER_MPU,
2121 };
2122 
2123 /* l3_core -> am35xx_usbhsotg interface */
2124 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
2125 	.master		= &am35xx_usbhsotg_hwmod,
2126 	.slave		= &omap3xxx_l3_main_hwmod,
2127 	.clk		= "hsotgusb_ick",
2128 	.user		= OCP_USER_MPU,
2129 };
2130 
2131 /* L4_CORE -> L4_WKUP interface */
2132 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
2133 	.master	= &omap3xxx_l4_core_hwmod,
2134 	.slave	= &omap3xxx_l4_wkup_hwmod,
2135 	.user	= OCP_USER_MPU | OCP_USER_SDMA,
2136 };
2137 
2138 /* L4 CORE -> MMC1 interface */
2139 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
2140 	.master		= &omap3xxx_l4_core_hwmod,
2141 	.slave		= &omap3xxx_pre_es3_mmc1_hwmod,
2142 	.clk		= "mmchs1_ick",
2143 	.addr		= omap2430_mmc1_addr_space,
2144 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2145 	.flags		= OMAP_FIREWALL_L4
2146 };
2147 
2148 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
2149 	.master		= &omap3xxx_l4_core_hwmod,
2150 	.slave		= &omap3xxx_es3plus_mmc1_hwmod,
2151 	.clk		= "mmchs1_ick",
2152 	.addr		= omap2430_mmc1_addr_space,
2153 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2154 	.flags		= OMAP_FIREWALL_L4
2155 };
2156 
2157 /* L4 CORE -> MMC2 interface */
2158 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
2159 	.master		= &omap3xxx_l4_core_hwmod,
2160 	.slave		= &omap3xxx_pre_es3_mmc2_hwmod,
2161 	.clk		= "mmchs2_ick",
2162 	.addr		= omap2430_mmc2_addr_space,
2163 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2164 	.flags		= OMAP_FIREWALL_L4
2165 };
2166 
2167 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2168 	.master		= &omap3xxx_l4_core_hwmod,
2169 	.slave		= &omap3xxx_es3plus_mmc2_hwmod,
2170 	.clk		= "mmchs2_ick",
2171 	.addr		= omap2430_mmc2_addr_space,
2172 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2173 	.flags		= OMAP_FIREWALL_L4
2174 };
2175 
2176 /* L4 CORE -> MMC3 interface */
2177 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
2178 	{
2179 		.pa_start	= 0x480ad000,
2180 		.pa_end		= 0x480ad1ff,
2181 		.flags		= ADDR_TYPE_RT,
2182 	},
2183 	{ }
2184 };
2185 
2186 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2187 	.master		= &omap3xxx_l4_core_hwmod,
2188 	.slave		= &omap3xxx_mmc3_hwmod,
2189 	.clk		= "mmchs3_ick",
2190 	.addr		= omap3xxx_mmc3_addr_space,
2191 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2192 	.flags		= OMAP_FIREWALL_L4
2193 };
2194 
2195 /* L4 CORE -> UART1 interface */
2196 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
2197 	{
2198 		.pa_start	= OMAP3_UART1_BASE,
2199 		.pa_end		= OMAP3_UART1_BASE + SZ_8K - 1,
2200 		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2201 	},
2202 	{ }
2203 };
2204 
2205 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2206 	.master		= &omap3xxx_l4_core_hwmod,
2207 	.slave		= &omap3xxx_uart1_hwmod,
2208 	.clk		= "uart1_ick",
2209 	.addr		= omap3xxx_uart1_addr_space,
2210 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2211 };
2212 
2213 /* L4 CORE -> UART2 interface */
2214 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
2215 	{
2216 		.pa_start	= OMAP3_UART2_BASE,
2217 		.pa_end		= OMAP3_UART2_BASE + SZ_1K - 1,
2218 		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2219 	},
2220 	{ }
2221 };
2222 
2223 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2224 	.master		= &omap3xxx_l4_core_hwmod,
2225 	.slave		= &omap3xxx_uart2_hwmod,
2226 	.clk		= "uart2_ick",
2227 	.addr		= omap3xxx_uart2_addr_space,
2228 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2229 };
2230 
2231 /* L4 PER -> UART3 interface */
2232 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
2233 	{
2234 		.pa_start	= OMAP3_UART3_BASE,
2235 		.pa_end		= OMAP3_UART3_BASE + SZ_1K - 1,
2236 		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2237 	},
2238 	{ }
2239 };
2240 
2241 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2242 	.master		= &omap3xxx_l4_per_hwmod,
2243 	.slave		= &omap3xxx_uart3_hwmod,
2244 	.clk		= "uart3_ick",
2245 	.addr		= omap3xxx_uart3_addr_space,
2246 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2247 };
2248 
2249 /* L4 PER -> UART4 interface */
2250 static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
2251 	{
2252 		.pa_start	= OMAP3_UART4_BASE,
2253 		.pa_end		= OMAP3_UART4_BASE + SZ_1K - 1,
2254 		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2255 	},
2256 	{ }
2257 };
2258 
2259 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2260 	.master		= &omap3xxx_l4_per_hwmod,
2261 	.slave		= &omap36xx_uart4_hwmod,
2262 	.clk		= "uart4_ick",
2263 	.addr		= omap36xx_uart4_addr_space,
2264 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2265 };
2266 
2267 /* AM35xx: L4 CORE -> UART4 interface */
2268 static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
2269 	{
2270 		.pa_start	= OMAP3_UART4_AM35XX_BASE,
2271 		.pa_end		= OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2272 		.flags		= ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2273 	},
2274 	{ }
2275 };
2276 
2277 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2278 	.master		= &omap3xxx_l4_core_hwmod,
2279 	.slave		= &am35xx_uart4_hwmod,
2280 	.clk		= "uart4_ick",
2281 	.addr		= am35xx_uart4_addr_space,
2282 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2283 };
2284 
2285 /* L4 CORE -> I2C1 interface */
2286 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2287 	.master		= &omap3xxx_l4_core_hwmod,
2288 	.slave		= &omap3xxx_i2c1_hwmod,
2289 	.clk		= "i2c1_ick",
2290 	.addr		= omap2_i2c1_addr_space,
2291 	.fw = {
2292 		.omap2 = {
2293 			.l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
2294 			.l4_prot_group = 7,
2295 			.flags	= OMAP_FIREWALL_L4,
2296 		}
2297 	},
2298 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2299 };
2300 
2301 /* L4 CORE -> I2C2 interface */
2302 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2303 	.master		= &omap3xxx_l4_core_hwmod,
2304 	.slave		= &omap3xxx_i2c2_hwmod,
2305 	.clk		= "i2c2_ick",
2306 	.addr		= omap2_i2c2_addr_space,
2307 	.fw = {
2308 		.omap2 = {
2309 			.l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
2310 			.l4_prot_group = 7,
2311 			.flags = OMAP_FIREWALL_L4,
2312 		}
2313 	},
2314 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2315 };
2316 
2317 /* L4 CORE -> I2C3 interface */
2318 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
2319 	{
2320 		.pa_start	= 0x48060000,
2321 		.pa_end		= 0x48060000 + SZ_128 - 1,
2322 		.flags		= ADDR_TYPE_RT,
2323 	},
2324 	{ }
2325 };
2326 
2327 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2328 	.master		= &omap3xxx_l4_core_hwmod,
2329 	.slave		= &omap3xxx_i2c3_hwmod,
2330 	.clk		= "i2c3_ick",
2331 	.addr		= omap3xxx_i2c3_addr_space,
2332 	.fw = {
2333 		.omap2 = {
2334 			.l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
2335 			.l4_prot_group = 7,
2336 			.flags = OMAP_FIREWALL_L4,
2337 		}
2338 	},
2339 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2340 };
2341 
2342 /* L4 CORE -> SR1 interface */
2343 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
2344 	{
2345 		.pa_start	= OMAP34XX_SR1_BASE,
2346 		.pa_end		= OMAP34XX_SR1_BASE + SZ_1K - 1,
2347 		.flags		= ADDR_TYPE_RT,
2348 	},
2349 	{ }
2350 };
2351 
2352 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2353 	.master		= &omap3xxx_l4_core_hwmod,
2354 	.slave		= &omap34xx_sr1_hwmod,
2355 	.clk		= "sr_l4_ick",
2356 	.addr		= omap3_sr1_addr_space,
2357 	.user		= OCP_USER_MPU,
2358 };
2359 
2360 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2361 	.master		= &omap3xxx_l4_core_hwmod,
2362 	.slave		= &omap36xx_sr1_hwmod,
2363 	.clk		= "sr_l4_ick",
2364 	.addr		= omap3_sr1_addr_space,
2365 	.user		= OCP_USER_MPU,
2366 };
2367 
2368 /* L4 CORE -> SR1 interface */
2369 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2370 	{
2371 		.pa_start	= OMAP34XX_SR2_BASE,
2372 		.pa_end		= OMAP34XX_SR2_BASE + SZ_1K - 1,
2373 		.flags		= ADDR_TYPE_RT,
2374 	},
2375 	{ }
2376 };
2377 
2378 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2379 	.master		= &omap3xxx_l4_core_hwmod,
2380 	.slave		= &omap34xx_sr2_hwmod,
2381 	.clk		= "sr_l4_ick",
2382 	.addr		= omap3_sr2_addr_space,
2383 	.user		= OCP_USER_MPU,
2384 };
2385 
2386 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2387 	.master		= &omap3xxx_l4_core_hwmod,
2388 	.slave		= &omap36xx_sr2_hwmod,
2389 	.clk		= "sr_l4_ick",
2390 	.addr		= omap3_sr2_addr_space,
2391 	.user		= OCP_USER_MPU,
2392 };
2393 
2394 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
2395 	{
2396 		.pa_start	= OMAP34XX_HSUSB_OTG_BASE,
2397 		.pa_end		= OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
2398 		.flags		= ADDR_TYPE_RT
2399 	},
2400 	{ }
2401 };
2402 
2403 /* l4_core -> usbhsotg  */
2404 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2405 	.master		= &omap3xxx_l4_core_hwmod,
2406 	.slave		= &omap3xxx_usbhsotg_hwmod,
2407 	.clk		= "l4_ick",
2408 	.addr		= omap3xxx_usbhsotg_addrs,
2409 	.user		= OCP_USER_MPU,
2410 };
2411 
2412 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2413 	{
2414 		.pa_start	= AM35XX_IPSS_USBOTGSS_BASE,
2415 		.pa_end		= AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
2416 		.flags		= ADDR_TYPE_RT
2417 	},
2418 	{ }
2419 };
2420 
2421 /* l4_core -> usbhsotg  */
2422 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2423 	.master		= &omap3xxx_l4_core_hwmod,
2424 	.slave		= &am35xx_usbhsotg_hwmod,
2425 	.clk		= "hsotgusb_ick",
2426 	.addr		= am35xx_usbhsotg_addrs,
2427 	.user		= OCP_USER_MPU,
2428 };
2429 
2430 /* L4_WKUP -> L4_SEC interface */
2431 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2432 	.master = &omap3xxx_l4_wkup_hwmod,
2433 	.slave	= &omap3xxx_l4_sec_hwmod,
2434 	.user	= OCP_USER_MPU | OCP_USER_SDMA,
2435 };
2436 
2437 /* IVA2 <- L3 interface */
2438 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2439 	.master		= &omap3xxx_l3_main_hwmod,
2440 	.slave		= &omap3xxx_iva_hwmod,
2441 	.clk		= "core_l3_ick",
2442 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2443 };
2444 
2445 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
2446 	{
2447 		.pa_start	= 0x48318000,
2448 		.pa_end		= 0x48318000 + SZ_1K - 1,
2449 		.flags		= ADDR_TYPE_RT
2450 	},
2451 	{ }
2452 };
2453 
2454 /* l4_wkup -> timer1 */
2455 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2456 	.master		= &omap3xxx_l4_wkup_hwmod,
2457 	.slave		= &omap3xxx_timer1_hwmod,
2458 	.clk		= "gpt1_ick",
2459 	.addr		= omap3xxx_timer1_addrs,
2460 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2461 };
2462 
2463 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
2464 	{
2465 		.pa_start	= 0x49032000,
2466 		.pa_end		= 0x49032000 + SZ_1K - 1,
2467 		.flags		= ADDR_TYPE_RT
2468 	},
2469 	{ }
2470 };
2471 
2472 /* l4_per -> timer2 */
2473 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2474 	.master		= &omap3xxx_l4_per_hwmod,
2475 	.slave		= &omap3xxx_timer2_hwmod,
2476 	.clk		= "gpt2_ick",
2477 	.addr		= omap3xxx_timer2_addrs,
2478 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2479 };
2480 
2481 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
2482 	{
2483 		.pa_start	= 0x49034000,
2484 		.pa_end		= 0x49034000 + SZ_1K - 1,
2485 		.flags		= ADDR_TYPE_RT
2486 	},
2487 	{ }
2488 };
2489 
2490 /* l4_per -> timer3 */
2491 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2492 	.master		= &omap3xxx_l4_per_hwmod,
2493 	.slave		= &omap3xxx_timer3_hwmod,
2494 	.clk		= "gpt3_ick",
2495 	.addr		= omap3xxx_timer3_addrs,
2496 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2497 };
2498 
2499 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
2500 	{
2501 		.pa_start	= 0x49036000,
2502 		.pa_end		= 0x49036000 + SZ_1K - 1,
2503 		.flags		= ADDR_TYPE_RT
2504 	},
2505 	{ }
2506 };
2507 
2508 /* l4_per -> timer4 */
2509 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2510 	.master		= &omap3xxx_l4_per_hwmod,
2511 	.slave		= &omap3xxx_timer4_hwmod,
2512 	.clk		= "gpt4_ick",
2513 	.addr		= omap3xxx_timer4_addrs,
2514 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2515 };
2516 
2517 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
2518 	{
2519 		.pa_start	= 0x49038000,
2520 		.pa_end		= 0x49038000 + SZ_1K - 1,
2521 		.flags		= ADDR_TYPE_RT
2522 	},
2523 	{ }
2524 };
2525 
2526 /* l4_per -> timer5 */
2527 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2528 	.master		= &omap3xxx_l4_per_hwmod,
2529 	.slave		= &omap3xxx_timer5_hwmod,
2530 	.clk		= "gpt5_ick",
2531 	.addr		= omap3xxx_timer5_addrs,
2532 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2533 };
2534 
2535 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
2536 	{
2537 		.pa_start	= 0x4903A000,
2538 		.pa_end		= 0x4903A000 + SZ_1K - 1,
2539 		.flags		= ADDR_TYPE_RT
2540 	},
2541 	{ }
2542 };
2543 
2544 /* l4_per -> timer6 */
2545 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2546 	.master		= &omap3xxx_l4_per_hwmod,
2547 	.slave		= &omap3xxx_timer6_hwmod,
2548 	.clk		= "gpt6_ick",
2549 	.addr		= omap3xxx_timer6_addrs,
2550 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2551 };
2552 
2553 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
2554 	{
2555 		.pa_start	= 0x4903C000,
2556 		.pa_end		= 0x4903C000 + SZ_1K - 1,
2557 		.flags		= ADDR_TYPE_RT
2558 	},
2559 	{ }
2560 };
2561 
2562 /* l4_per -> timer7 */
2563 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2564 	.master		= &omap3xxx_l4_per_hwmod,
2565 	.slave		= &omap3xxx_timer7_hwmod,
2566 	.clk		= "gpt7_ick",
2567 	.addr		= omap3xxx_timer7_addrs,
2568 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2569 };
2570 
2571 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
2572 	{
2573 		.pa_start	= 0x4903E000,
2574 		.pa_end		= 0x4903E000 + SZ_1K - 1,
2575 		.flags		= ADDR_TYPE_RT
2576 	},
2577 	{ }
2578 };
2579 
2580 /* l4_per -> timer8 */
2581 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2582 	.master		= &omap3xxx_l4_per_hwmod,
2583 	.slave		= &omap3xxx_timer8_hwmod,
2584 	.clk		= "gpt8_ick",
2585 	.addr		= omap3xxx_timer8_addrs,
2586 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2587 };
2588 
2589 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
2590 	{
2591 		.pa_start	= 0x49040000,
2592 		.pa_end		= 0x49040000 + SZ_1K - 1,
2593 		.flags		= ADDR_TYPE_RT
2594 	},
2595 	{ }
2596 };
2597 
2598 /* l4_per -> timer9 */
2599 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2600 	.master		= &omap3xxx_l4_per_hwmod,
2601 	.slave		= &omap3xxx_timer9_hwmod,
2602 	.clk		= "gpt9_ick",
2603 	.addr		= omap3xxx_timer9_addrs,
2604 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2605 };
2606 
2607 /* l4_core -> timer10 */
2608 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2609 	.master		= &omap3xxx_l4_core_hwmod,
2610 	.slave		= &omap3xxx_timer10_hwmod,
2611 	.clk		= "gpt10_ick",
2612 	.addr		= omap2_timer10_addrs,
2613 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2614 };
2615 
2616 /* l4_core -> timer11 */
2617 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2618 	.master		= &omap3xxx_l4_core_hwmod,
2619 	.slave		= &omap3xxx_timer11_hwmod,
2620 	.clk		= "gpt11_ick",
2621 	.addr		= omap2_timer11_addrs,
2622 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2623 };
2624 
2625 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
2626 	{
2627 		.pa_start	= 0x48304000,
2628 		.pa_end		= 0x48304000 + SZ_1K - 1,
2629 		.flags		= ADDR_TYPE_RT
2630 	},
2631 	{ }
2632 };
2633 
2634 /* l4_core -> timer12 */
2635 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2636 	.master		= &omap3xxx_l4_sec_hwmod,
2637 	.slave		= &omap3xxx_timer12_hwmod,
2638 	.clk		= "gpt12_ick",
2639 	.addr		= omap3xxx_timer12_addrs,
2640 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2641 };
2642 
2643 /* l4_wkup -> wd_timer2 */
2644 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
2645 	{
2646 		.pa_start	= 0x48314000,
2647 		.pa_end		= 0x4831407f,
2648 		.flags		= ADDR_TYPE_RT
2649 	},
2650 	{ }
2651 };
2652 
2653 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2654 	.master		= &omap3xxx_l4_wkup_hwmod,
2655 	.slave		= &omap3xxx_wd_timer2_hwmod,
2656 	.clk		= "wdt2_ick",
2657 	.addr		= omap3xxx_wd_timer2_addrs,
2658 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2659 };
2660 
2661 /* l4_core -> dss */
2662 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2663 	.master		= &omap3xxx_l4_core_hwmod,
2664 	.slave		= &omap3430es1_dss_core_hwmod,
2665 	.clk		= "dss_ick",
2666 	.addr		= omap2_dss_addrs,
2667 	.fw = {
2668 		.omap2 = {
2669 			.l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2670 			.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2671 			.flags	= OMAP_FIREWALL_L4,
2672 		}
2673 	},
2674 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2675 };
2676 
2677 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2678 	.master		= &omap3xxx_l4_core_hwmod,
2679 	.slave		= &omap3xxx_dss_core_hwmod,
2680 	.clk		= "dss_ick",
2681 	.addr		= omap2_dss_addrs,
2682 	.fw = {
2683 		.omap2 = {
2684 			.l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2685 			.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2686 			.flags	= OMAP_FIREWALL_L4,
2687 		}
2688 	},
2689 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2690 };
2691 
2692 /* l4_core -> dss_dispc */
2693 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2694 	.master		= &omap3xxx_l4_core_hwmod,
2695 	.slave		= &omap3xxx_dss_dispc_hwmod,
2696 	.clk		= "dss_ick",
2697 	.addr		= omap2_dss_dispc_addrs,
2698 	.fw = {
2699 		.omap2 = {
2700 			.l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2701 			.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2702 			.flags	= OMAP_FIREWALL_L4,
2703 		}
2704 	},
2705 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2706 };
2707 
2708 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
2709 	{
2710 		.pa_start	= 0x4804FC00,
2711 		.pa_end		= 0x4804FFFF,
2712 		.flags		= ADDR_TYPE_RT
2713 	},
2714 	{ }
2715 };
2716 
2717 /* l4_core -> dss_dsi1 */
2718 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2719 	.master		= &omap3xxx_l4_core_hwmod,
2720 	.slave		= &omap3xxx_dss_dsi1_hwmod,
2721 	.clk		= "dss_ick",
2722 	.addr		= omap3xxx_dss_dsi1_addrs,
2723 	.fw = {
2724 		.omap2 = {
2725 			.l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2726 			.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2727 			.flags	= OMAP_FIREWALL_L4,
2728 		}
2729 	},
2730 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2731 };
2732 
2733 /* l4_core -> dss_rfbi */
2734 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2735 	.master		= &omap3xxx_l4_core_hwmod,
2736 	.slave		= &omap3xxx_dss_rfbi_hwmod,
2737 	.clk		= "dss_ick",
2738 	.addr		= omap2_dss_rfbi_addrs,
2739 	.fw = {
2740 		.omap2 = {
2741 			.l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2742 			.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2743 			.flags	= OMAP_FIREWALL_L4,
2744 		}
2745 	},
2746 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2747 };
2748 
2749 /* l4_core -> dss_venc */
2750 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2751 	.master		= &omap3xxx_l4_core_hwmod,
2752 	.slave		= &omap3xxx_dss_venc_hwmod,
2753 	.clk		= "dss_ick",
2754 	.addr		= omap2_dss_venc_addrs,
2755 	.fw = {
2756 		.omap2 = {
2757 			.l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2758 			.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2759 			.flags	= OMAP_FIREWALL_L4,
2760 		}
2761 	},
2762 	.flags		= OCPIF_SWSUP_IDLE,
2763 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2764 };
2765 
2766 /* l4_wkup -> gpio1 */
2767 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2768 	{
2769 		.pa_start	= 0x48310000,
2770 		.pa_end		= 0x483101ff,
2771 		.flags		= ADDR_TYPE_RT
2772 	},
2773 	{ }
2774 };
2775 
2776 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2777 	.master		= &omap3xxx_l4_wkup_hwmod,
2778 	.slave		= &omap3xxx_gpio1_hwmod,
2779 	.addr		= omap3xxx_gpio1_addrs,
2780 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2781 };
2782 
2783 /* l4_per -> gpio2 */
2784 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2785 	{
2786 		.pa_start	= 0x49050000,
2787 		.pa_end		= 0x490501ff,
2788 		.flags		= ADDR_TYPE_RT
2789 	},
2790 	{ }
2791 };
2792 
2793 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2794 	.master		= &omap3xxx_l4_per_hwmod,
2795 	.slave		= &omap3xxx_gpio2_hwmod,
2796 	.addr		= omap3xxx_gpio2_addrs,
2797 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2798 };
2799 
2800 /* l4_per -> gpio3 */
2801 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2802 	{
2803 		.pa_start	= 0x49052000,
2804 		.pa_end		= 0x490521ff,
2805 		.flags		= ADDR_TYPE_RT
2806 	},
2807 	{ }
2808 };
2809 
2810 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2811 	.master		= &omap3xxx_l4_per_hwmod,
2812 	.slave		= &omap3xxx_gpio3_hwmod,
2813 	.addr		= omap3xxx_gpio3_addrs,
2814 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2815 };
2816 
2817 /* l4_per -> gpio4 */
2818 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
2819 	{
2820 		.pa_start	= 0x49054000,
2821 		.pa_end		= 0x490541ff,
2822 		.flags		= ADDR_TYPE_RT
2823 	},
2824 	{ }
2825 };
2826 
2827 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
2828 	.master		= &omap3xxx_l4_per_hwmod,
2829 	.slave		= &omap3xxx_gpio4_hwmod,
2830 	.addr		= omap3xxx_gpio4_addrs,
2831 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2832 };
2833 
2834 /* l4_per -> gpio5 */
2835 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
2836 	{
2837 		.pa_start	= 0x49056000,
2838 		.pa_end		= 0x490561ff,
2839 		.flags		= ADDR_TYPE_RT
2840 	},
2841 	{ }
2842 };
2843 
2844 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
2845 	.master		= &omap3xxx_l4_per_hwmod,
2846 	.slave		= &omap3xxx_gpio5_hwmod,
2847 	.addr		= omap3xxx_gpio5_addrs,
2848 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2849 };
2850 
2851 /* l4_per -> gpio6 */
2852 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
2853 	{
2854 		.pa_start	= 0x49058000,
2855 		.pa_end		= 0x490581ff,
2856 		.flags		= ADDR_TYPE_RT
2857 	},
2858 	{ }
2859 };
2860 
2861 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2862 	.master		= &omap3xxx_l4_per_hwmod,
2863 	.slave		= &omap3xxx_gpio6_hwmod,
2864 	.addr		= omap3xxx_gpio6_addrs,
2865 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2866 };
2867 
2868 /* dma_system -> L3 */
2869 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2870 	.master		= &omap3xxx_dma_system_hwmod,
2871 	.slave		= &omap3xxx_l3_main_hwmod,
2872 	.clk		= "core_l3_ick",
2873 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2874 };
2875 
2876 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2877 	{
2878 		.pa_start	= 0x48056000,
2879 		.pa_end		= 0x48056fff,
2880 		.flags		= ADDR_TYPE_RT
2881 	},
2882 	{ }
2883 };
2884 
2885 /* l4_cfg -> dma_system */
2886 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2887 	.master		= &omap3xxx_l4_core_hwmod,
2888 	.slave		= &omap3xxx_dma_system_hwmod,
2889 	.clk		= "core_l4_ick",
2890 	.addr		= omap3xxx_dma_system_addrs,
2891 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2892 };
2893 
2894 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2895 	{
2896 		.name		= "mpu",
2897 		.pa_start	= 0x48074000,
2898 		.pa_end		= 0x480740ff,
2899 		.flags		= ADDR_TYPE_RT
2900 	},
2901 	{ }
2902 };
2903 
2904 /* l4_core -> mcbsp1 */
2905 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2906 	.master		= &omap3xxx_l4_core_hwmod,
2907 	.slave		= &omap3xxx_mcbsp1_hwmod,
2908 	.clk		= "mcbsp1_ick",
2909 	.addr		= omap3xxx_mcbsp1_addrs,
2910 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2911 };
2912 
2913 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2914 	{
2915 		.name		= "mpu",
2916 		.pa_start	= 0x49022000,
2917 		.pa_end		= 0x490220ff,
2918 		.flags		= ADDR_TYPE_RT
2919 	},
2920 	{ }
2921 };
2922 
2923 /* l4_per -> mcbsp2 */
2924 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2925 	.master		= &omap3xxx_l4_per_hwmod,
2926 	.slave		= &omap3xxx_mcbsp2_hwmod,
2927 	.clk		= "mcbsp2_ick",
2928 	.addr		= omap3xxx_mcbsp2_addrs,
2929 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2930 };
2931 
2932 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2933 	{
2934 		.name		= "mpu",
2935 		.pa_start	= 0x49024000,
2936 		.pa_end		= 0x490240ff,
2937 		.flags		= ADDR_TYPE_RT
2938 	},
2939 	{ }
2940 };
2941 
2942 /* l4_per -> mcbsp3 */
2943 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2944 	.master		= &omap3xxx_l4_per_hwmod,
2945 	.slave		= &omap3xxx_mcbsp3_hwmod,
2946 	.clk		= "mcbsp3_ick",
2947 	.addr		= omap3xxx_mcbsp3_addrs,
2948 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2949 };
2950 
2951 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2952 	{
2953 		.name		= "mpu",
2954 		.pa_start	= 0x49026000,
2955 		.pa_end		= 0x490260ff,
2956 		.flags		= ADDR_TYPE_RT
2957 	},
2958 	{ }
2959 };
2960 
2961 /* l4_per -> mcbsp4 */
2962 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2963 	.master		= &omap3xxx_l4_per_hwmod,
2964 	.slave		= &omap3xxx_mcbsp4_hwmod,
2965 	.clk		= "mcbsp4_ick",
2966 	.addr		= omap3xxx_mcbsp4_addrs,
2967 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2968 };
2969 
2970 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2971 	{
2972 		.name		= "mpu",
2973 		.pa_start	= 0x48096000,
2974 		.pa_end		= 0x480960ff,
2975 		.flags		= ADDR_TYPE_RT
2976 	},
2977 	{ }
2978 };
2979 
2980 /* l4_core -> mcbsp5 */
2981 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2982 	.master		= &omap3xxx_l4_core_hwmod,
2983 	.slave		= &omap3xxx_mcbsp5_hwmod,
2984 	.clk		= "mcbsp5_ick",
2985 	.addr		= omap3xxx_mcbsp5_addrs,
2986 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2987 };
2988 
2989 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2990 	{
2991 		.name		= "sidetone",
2992 		.pa_start	= 0x49028000,
2993 		.pa_end		= 0x490280ff,
2994 		.flags		= ADDR_TYPE_RT
2995 	},
2996 	{ }
2997 };
2998 
2999 /* l4_per -> mcbsp2_sidetone */
3000 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
3001 	.master		= &omap3xxx_l4_per_hwmod,
3002 	.slave		= &omap3xxx_mcbsp2_sidetone_hwmod,
3003 	.clk		= "mcbsp2_ick",
3004 	.addr		= omap3xxx_mcbsp2_sidetone_addrs,
3005 	.user		= OCP_USER_MPU,
3006 };
3007 
3008 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
3009 	{
3010 		.name		= "sidetone",
3011 		.pa_start	= 0x4902A000,
3012 		.pa_end		= 0x4902A0ff,
3013 		.flags		= ADDR_TYPE_RT
3014 	},
3015 	{ }
3016 };
3017 
3018 /* l4_per -> mcbsp3_sidetone */
3019 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
3020 	.master		= &omap3xxx_l4_per_hwmod,
3021 	.slave		= &omap3xxx_mcbsp3_sidetone_hwmod,
3022 	.clk		= "mcbsp3_ick",
3023 	.addr		= omap3xxx_mcbsp3_sidetone_addrs,
3024 	.user		= OCP_USER_MPU,
3025 };
3026 
3027 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
3028 	{
3029 		.pa_start	= 0x48094000,
3030 		.pa_end		= 0x480941ff,
3031 		.flags		= ADDR_TYPE_RT,
3032 	},
3033 	{ }
3034 };
3035 
3036 /* l4_core -> mailbox */
3037 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3038 	.master		= &omap3xxx_l4_core_hwmod,
3039 	.slave		= &omap3xxx_mailbox_hwmod,
3040 	.addr		= omap3xxx_mailbox_addrs,
3041 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3042 };
3043 
3044 /* l4 core -> mcspi1 interface */
3045 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3046 	.master		= &omap3xxx_l4_core_hwmod,
3047 	.slave		= &omap34xx_mcspi1,
3048 	.clk		= "mcspi1_ick",
3049 	.addr		= omap2_mcspi1_addr_space,
3050 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3051 };
3052 
3053 /* l4 core -> mcspi2 interface */
3054 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3055 	.master		= &omap3xxx_l4_core_hwmod,
3056 	.slave		= &omap34xx_mcspi2,
3057 	.clk		= "mcspi2_ick",
3058 	.addr		= omap2_mcspi2_addr_space,
3059 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3060 };
3061 
3062 /* l4 core -> mcspi3 interface */
3063 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3064 	.master		= &omap3xxx_l4_core_hwmod,
3065 	.slave		= &omap34xx_mcspi3,
3066 	.clk		= "mcspi3_ick",
3067 	.addr		= omap2430_mcspi3_addr_space,
3068 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3069 };
3070 
3071 /* l4 core -> mcspi4 interface */
3072 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3073 	{
3074 		.pa_start	= 0x480ba000,
3075 		.pa_end		= 0x480ba0ff,
3076 		.flags		= ADDR_TYPE_RT,
3077 	},
3078 	{ }
3079 };
3080 
3081 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3082 	.master		= &omap3xxx_l4_core_hwmod,
3083 	.slave		= &omap34xx_mcspi4,
3084 	.clk		= "mcspi4_ick",
3085 	.addr		= omap34xx_mcspi4_addr_space,
3086 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3087 };
3088 
3089 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3090 	.master		= &omap3xxx_usb_host_hs_hwmod,
3091 	.slave		= &omap3xxx_l3_main_hwmod,
3092 	.clk		= "core_l3_ick",
3093 	.user		= OCP_USER_MPU,
3094 };
3095 
3096 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3097 	{
3098 		.name		= "uhh",
3099 		.pa_start	= 0x48064000,
3100 		.pa_end		= 0x480643ff,
3101 		.flags		= ADDR_TYPE_RT
3102 	},
3103 	{
3104 		.name		= "ohci",
3105 		.pa_start	= 0x48064400,
3106 		.pa_end		= 0x480647ff,
3107 	},
3108 	{
3109 		.name		= "ehci",
3110 		.pa_start	= 0x48064800,
3111 		.pa_end		= 0x48064cff,
3112 	},
3113 	{}
3114 };
3115 
3116 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3117 	.master		= &omap3xxx_l4_core_hwmod,
3118 	.slave		= &omap3xxx_usb_host_hs_hwmod,
3119 	.clk		= "usbhost_ick",
3120 	.addr		= omap3xxx_usb_host_hs_addrs,
3121 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3122 };
3123 
3124 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3125 	{
3126 		.name		= "tll",
3127 		.pa_start	= 0x48062000,
3128 		.pa_end		= 0x48062fff,
3129 		.flags		= ADDR_TYPE_RT
3130 	},
3131 	{}
3132 };
3133 
3134 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3135 	.master		= &omap3xxx_l4_core_hwmod,
3136 	.slave		= &omap3xxx_usb_tll_hs_hwmod,
3137 	.clk		= "usbtll_ick",
3138 	.addr		= omap3xxx_usb_tll_hs_addrs,
3139 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3140 };
3141 
3142 /* l4_core -> hdq1w interface */
3143 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
3144 	.master		= &omap3xxx_l4_core_hwmod,
3145 	.slave		= &omap3xxx_hdq1w_hwmod,
3146 	.clk		= "hdq_ick",
3147 	.addr		= omap2_hdq1w_addr_space,
3148 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3149 	.flags		= OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
3150 };
3151 
3152 /* l4_wkup -> 32ksync_counter */
3153 static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
3154 	{
3155 		.pa_start	= 0x48320000,
3156 		.pa_end		= 0x4832001f,
3157 		.flags		= ADDR_TYPE_RT
3158 	},
3159 	{ }
3160 };
3161 
3162 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
3163 	.master		= &omap3xxx_l4_wkup_hwmod,
3164 	.slave		= &omap3xxx_counter_32k_hwmod,
3165 	.clk		= "omap_32ksync_ick",
3166 	.addr		= omap3xxx_counter_32k_addrs,
3167 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3168 };
3169 
3170 /* am35xx has Davinci MDIO & EMAC */
3171 static struct omap_hwmod_class am35xx_mdio_class = {
3172 	.name = "davinci_mdio",
3173 };
3174 
3175 static struct omap_hwmod am35xx_mdio_hwmod = {
3176 	.name		= "davinci_mdio",
3177 	.class		= &am35xx_mdio_class,
3178 	.flags		= HWMOD_NO_IDLEST,
3179 };
3180 
3181 /*
3182  * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3183  * but this will probably require some additional hwmod core support,
3184  * so is left as a future to-do item.
3185  */
3186 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
3187 	.master		= &am35xx_mdio_hwmod,
3188 	.slave		= &omap3xxx_l3_main_hwmod,
3189 	.clk		= "emac_fck",
3190 	.user		= OCP_USER_MPU,
3191 };
3192 
3193 static struct omap_hwmod_addr_space am35xx_mdio_addrs[] = {
3194 	{
3195 		.pa_start	= AM35XX_IPSS_MDIO_BASE,
3196 		.pa_end		= AM35XX_IPSS_MDIO_BASE + SZ_4K - 1,
3197 		.flags		= ADDR_TYPE_RT,
3198 	},
3199 	{ }
3200 };
3201 
3202 /* l4_core -> davinci mdio  */
3203 /*
3204  * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3205  * but this will probably require some additional hwmod core support,
3206  * so is left as a future to-do item.
3207  */
3208 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
3209 	.master		= &omap3xxx_l4_core_hwmod,
3210 	.slave		= &am35xx_mdio_hwmod,
3211 	.clk		= "emac_fck",
3212 	.addr		= am35xx_mdio_addrs,
3213 	.user		= OCP_USER_MPU,
3214 };
3215 
3216 static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = {
3217 	{ .name = "rxthresh",	.irq = INT_35XX_EMAC_C0_RXTHRESH_IRQ },
3218 	{ .name = "rx_pulse",	.irq = INT_35XX_EMAC_C0_RX_PULSE_IRQ },
3219 	{ .name = "tx_pulse",	.irq = INT_35XX_EMAC_C0_TX_PULSE_IRQ },
3220 	{ .name = "misc_pulse",	.irq = INT_35XX_EMAC_C0_MISC_PULSE_IRQ },
3221 	{ .irq = -1 }
3222 };
3223 
3224 static struct omap_hwmod_class am35xx_emac_class = {
3225 	.name = "davinci_emac",
3226 };
3227 
3228 static struct omap_hwmod am35xx_emac_hwmod = {
3229 	.name		= "davinci_emac",
3230 	.mpu_irqs	= am35xx_emac_mpu_irqs,
3231 	.class		= &am35xx_emac_class,
3232 	.flags		= HWMOD_NO_IDLEST,
3233 };
3234 
3235 /* l3_core -> davinci emac interface */
3236 /*
3237  * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3238  * but this will probably require some additional hwmod core support,
3239  * so is left as a future to-do item.
3240  */
3241 static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
3242 	.master		= &am35xx_emac_hwmod,
3243 	.slave		= &omap3xxx_l3_main_hwmod,
3244 	.clk		= "emac_ick",
3245 	.user		= OCP_USER_MPU,
3246 };
3247 
3248 static struct omap_hwmod_addr_space am35xx_emac_addrs[] = {
3249 	{
3250 		.pa_start	= AM35XX_IPSS_EMAC_BASE,
3251 		.pa_end		= AM35XX_IPSS_EMAC_BASE + 0x30000 - 1,
3252 		.flags		= ADDR_TYPE_RT,
3253 	},
3254 	{ }
3255 };
3256 
3257 /* l4_core -> davinci emac  */
3258 /*
3259  * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3260  * but this will probably require some additional hwmod core support,
3261  * so is left as a future to-do item.
3262  */
3263 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
3264 	.master		= &omap3xxx_l4_core_hwmod,
3265 	.slave		= &am35xx_emac_hwmod,
3266 	.clk		= "emac_ick",
3267 	.addr		= am35xx_emac_addrs,
3268 	.user		= OCP_USER_MPU,
3269 };
3270 
3271 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3272 	&omap3xxx_l3_main__l4_core,
3273 	&omap3xxx_l3_main__l4_per,
3274 	&omap3xxx_mpu__l3_main,
3275 	&omap3xxx_l4_core__l4_wkup,
3276 	&omap3xxx_l4_core__mmc3,
3277 	&omap3_l4_core__uart1,
3278 	&omap3_l4_core__uart2,
3279 	&omap3_l4_per__uart3,
3280 	&omap3_l4_core__i2c1,
3281 	&omap3_l4_core__i2c2,
3282 	&omap3_l4_core__i2c3,
3283 	&omap3xxx_l4_wkup__l4_sec,
3284 	&omap3xxx_l4_wkup__timer1,
3285 	&omap3xxx_l4_per__timer2,
3286 	&omap3xxx_l4_per__timer3,
3287 	&omap3xxx_l4_per__timer4,
3288 	&omap3xxx_l4_per__timer5,
3289 	&omap3xxx_l4_per__timer6,
3290 	&omap3xxx_l4_per__timer7,
3291 	&omap3xxx_l4_per__timer8,
3292 	&omap3xxx_l4_per__timer9,
3293 	&omap3xxx_l4_core__timer10,
3294 	&omap3xxx_l4_core__timer11,
3295 	&omap3xxx_l4_wkup__wd_timer2,
3296 	&omap3xxx_l4_wkup__gpio1,
3297 	&omap3xxx_l4_per__gpio2,
3298 	&omap3xxx_l4_per__gpio3,
3299 	&omap3xxx_l4_per__gpio4,
3300 	&omap3xxx_l4_per__gpio5,
3301 	&omap3xxx_l4_per__gpio6,
3302 	&omap3xxx_dma_system__l3,
3303 	&omap3xxx_l4_core__dma_system,
3304 	&omap3xxx_l4_core__mcbsp1,
3305 	&omap3xxx_l4_per__mcbsp2,
3306 	&omap3xxx_l4_per__mcbsp3,
3307 	&omap3xxx_l4_per__mcbsp4,
3308 	&omap3xxx_l4_core__mcbsp5,
3309 	&omap3xxx_l4_per__mcbsp2_sidetone,
3310 	&omap3xxx_l4_per__mcbsp3_sidetone,
3311 	&omap34xx_l4_core__mcspi1,
3312 	&omap34xx_l4_core__mcspi2,
3313 	&omap34xx_l4_core__mcspi3,
3314 	&omap34xx_l4_core__mcspi4,
3315 	&omap3xxx_l4_wkup__counter_32k,
3316 	NULL,
3317 };
3318 
3319 /* GP-only hwmod links */
3320 static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = {
3321 	&omap3xxx_l4_sec__timer12,
3322 	NULL
3323 };
3324 
3325 /* 3430ES1-only hwmod links */
3326 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3327 	&omap3430es1_dss__l3,
3328 	&omap3430es1_l4_core__dss,
3329 	NULL
3330 };
3331 
3332 /* 3430ES2+-only hwmod links */
3333 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3334 	&omap3xxx_dss__l3,
3335 	&omap3xxx_l4_core__dss,
3336 	&omap3xxx_usbhsotg__l3,
3337 	&omap3xxx_l4_core__usbhsotg,
3338 	&omap3xxx_usb_host_hs__l3_main_2,
3339 	&omap3xxx_l4_core__usb_host_hs,
3340 	&omap3xxx_l4_core__usb_tll_hs,
3341 	NULL
3342 };
3343 
3344 /* <= 3430ES3-only hwmod links */
3345 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3346 	&omap3xxx_l4_core__pre_es3_mmc1,
3347 	&omap3xxx_l4_core__pre_es3_mmc2,
3348 	NULL
3349 };
3350 
3351 /* 3430ES3+-only hwmod links */
3352 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3353 	&omap3xxx_l4_core__es3plus_mmc1,
3354 	&omap3xxx_l4_core__es3plus_mmc2,
3355 	NULL
3356 };
3357 
3358 /* 34xx-only hwmod links (all ES revisions) */
3359 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3360 	&omap3xxx_l3__iva,
3361 	&omap34xx_l4_core__sr1,
3362 	&omap34xx_l4_core__sr2,
3363 	&omap3xxx_l4_core__mailbox,
3364 	&omap3xxx_l4_core__hdq1w,
3365 	NULL
3366 };
3367 
3368 /* 36xx-only hwmod links (all ES revisions) */
3369 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3370 	&omap3xxx_l3__iva,
3371 	&omap36xx_l4_per__uart4,
3372 	&omap3xxx_dss__l3,
3373 	&omap3xxx_l4_core__dss,
3374 	&omap36xx_l4_core__sr1,
3375 	&omap36xx_l4_core__sr2,
3376 	&omap3xxx_usbhsotg__l3,
3377 	&omap3xxx_l4_core__usbhsotg,
3378 	&omap3xxx_l4_core__mailbox,
3379 	&omap3xxx_usb_host_hs__l3_main_2,
3380 	&omap3xxx_l4_core__usb_host_hs,
3381 	&omap3xxx_l4_core__usb_tll_hs,
3382 	&omap3xxx_l4_core__es3plus_mmc1,
3383 	&omap3xxx_l4_core__es3plus_mmc2,
3384 	&omap3xxx_l4_core__hdq1w,
3385 	NULL
3386 };
3387 
3388 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3389 	&omap3xxx_dss__l3,
3390 	&omap3xxx_l4_core__dss,
3391 	&am35xx_usbhsotg__l3,
3392 	&am35xx_l4_core__usbhsotg,
3393 	&am35xx_l4_core__uart4,
3394 	&omap3xxx_usb_host_hs__l3_main_2,
3395 	&omap3xxx_l4_core__usb_host_hs,
3396 	&omap3xxx_l4_core__usb_tll_hs,
3397 	&omap3xxx_l4_core__es3plus_mmc1,
3398 	&omap3xxx_l4_core__es3plus_mmc2,
3399 	&am35xx_mdio__l3,
3400 	&am35xx_l4_core__mdio,
3401 	&am35xx_emac__l3,
3402 	&am35xx_l4_core__emac,
3403 	NULL
3404 };
3405 
3406 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3407 	&omap3xxx_l4_core__dss_dispc,
3408 	&omap3xxx_l4_core__dss_dsi1,
3409 	&omap3xxx_l4_core__dss_rfbi,
3410 	&omap3xxx_l4_core__dss_venc,
3411 	NULL
3412 };
3413 
3414 int __init omap3xxx_hwmod_init(void)
3415 {
3416 	int r;
3417 	struct omap_hwmod_ocp_if **h = NULL;
3418 	unsigned int rev;
3419 
3420 	omap_hwmod_init();
3421 
3422 	/* Register hwmod links common to all OMAP3 */
3423 	r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3424 	if (r < 0)
3425 		return r;
3426 
3427 	/* Register GP-only hwmod links. */
3428 	if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
3429 		r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs);
3430 		if (r < 0)
3431 			return r;
3432 	}
3433 
3434 	rev = omap_rev();
3435 
3436 	/*
3437 	 * Register hwmod links common to individual OMAP3 families, all
3438 	 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3439 	 * All possible revisions should be included in this conditional.
3440 	 */
3441 	if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3442 	    rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3443 	    rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3444 		h = omap34xx_hwmod_ocp_ifs;
3445 	} else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
3446 		h = am35xx_hwmod_ocp_ifs;
3447 	} else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3448 		   rev == OMAP3630_REV_ES1_2) {
3449 		h = omap36xx_hwmod_ocp_ifs;
3450 	} else {
3451 		WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3452 		return -EINVAL;
3453 	};
3454 
3455 	r = omap_hwmod_register_links(h);
3456 	if (r < 0)
3457 		return r;
3458 
3459 	/*
3460 	 * Register hwmod links specific to certain ES levels of a
3461 	 * particular family of silicon (e.g., 34xx ES1.0)
3462 	 */
3463 	h = NULL;
3464 	if (rev == OMAP3430_REV_ES1_0) {
3465 		h = omap3430es1_hwmod_ocp_ifs;
3466 	} else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3467 		   rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3468 		   rev == OMAP3430_REV_ES3_1_2) {
3469 		h = omap3430es2plus_hwmod_ocp_ifs;
3470 	};
3471 
3472 	if (h) {
3473 		r = omap_hwmod_register_links(h);
3474 		if (r < 0)
3475 			return r;
3476 	}
3477 
3478 	h = NULL;
3479 	if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3480 	    rev == OMAP3430_REV_ES2_1) {
3481 		h = omap3430_pre_es3_hwmod_ocp_ifs;
3482 	} else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3483 		   rev == OMAP3430_REV_ES3_1_2) {
3484 		h = omap3430_es3plus_hwmod_ocp_ifs;
3485 	};
3486 
3487 	if (h)
3488 		r = omap_hwmod_register_links(h);
3489 	if (r < 0)
3490 		return r;
3491 
3492 	/*
3493 	 * DSS code presumes that dss_core hwmod is handled first,
3494 	 * _before_ any other DSS related hwmods so register common
3495 	 * DSS hwmod links last to ensure that dss_core is already
3496 	 * registered.  Otherwise some change things may happen, for
3497 	 * ex. if dispc is handled before dss_core and DSS is enabled
3498 	 * in bootloader DISPC will be reset with outputs enabled
3499 	 * which sometimes leads to unrecoverable L3 error.  XXX The
3500 	 * long-term fix to this is to ensure hwmods are set up in
3501 	 * dependency order in the hwmod core code.
3502 	 */
3503 	r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
3504 
3505 	return r;
3506 }
3507