1 /* 2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips 3 * 4 * Copyright (C) 2009-2011 Nokia Corporation 5 * Copyright (C) 2012 Texas Instruments, Inc. 6 * Paul Walmsley 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * The data in this file should be completely autogeneratable from 13 * the TI hardware database or other technical documentation. 14 * 15 * XXX these should be marked initdata for multi-OMAP kernels 16 */ 17 18 #include <linux/i2c-omap.h> 19 #include <linux/power/smartreflex.h> 20 #include <linux/platform_data/gpio-omap.h> 21 #include <linux/platform_data/hsmmc-omap.h> 22 23 #include <linux/omap-dma.h> 24 #include "l3_3xxx.h" 25 #include "l4_3xxx.h" 26 #include <linux/platform_data/asoc-ti-mcbsp.h> 27 #include <linux/platform_data/spi-omap2-mcspi.h> 28 #include <plat/dmtimer.h> 29 30 #include "soc.h" 31 #include "omap_hwmod.h" 32 #include "omap_hwmod_common_data.h" 33 #include "prm-regbits-34xx.h" 34 #include "cm-regbits-34xx.h" 35 36 #include "i2c.h" 37 #include "wd_timer.h" 38 #include "serial.h" 39 40 /* 41 * OMAP3xxx hardware module integration data 42 * 43 * All of the data in this section should be autogeneratable from the 44 * TI hardware database or other technical documentation. Data that 45 * is driver-specific or driver-kernel integration-specific belongs 46 * elsewhere. 47 */ 48 49 #define AM35XX_IPSS_USBOTGSS_BASE 0x5C040000 50 51 /* 52 * IP blocks 53 */ 54 55 /* L3 */ 56 57 static struct omap_hwmod omap3xxx_l3_main_hwmod = { 58 .name = "l3_main", 59 .class = &l3_hwmod_class, 60 .flags = HWMOD_NO_IDLEST, 61 }; 62 63 /* L4 CORE */ 64 static struct omap_hwmod omap3xxx_l4_core_hwmod = { 65 .name = "l4_core", 66 .class = &l4_hwmod_class, 67 .flags = HWMOD_NO_IDLEST, 68 }; 69 70 /* L4 PER */ 71 static struct omap_hwmod omap3xxx_l4_per_hwmod = { 72 .name = "l4_per", 73 .class = &l4_hwmod_class, 74 .flags = HWMOD_NO_IDLEST, 75 }; 76 77 /* L4 WKUP */ 78 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { 79 .name = "l4_wkup", 80 .class = &l4_hwmod_class, 81 .flags = HWMOD_NO_IDLEST, 82 }; 83 84 /* L4 SEC */ 85 static struct omap_hwmod omap3xxx_l4_sec_hwmod = { 86 .name = "l4_sec", 87 .class = &l4_hwmod_class, 88 .flags = HWMOD_NO_IDLEST, 89 }; 90 91 /* MPU */ 92 93 static struct omap_hwmod omap3xxx_mpu_hwmod = { 94 .name = "mpu", 95 .class = &mpu_hwmod_class, 96 .main_clk = "arm_fck", 97 }; 98 99 /* IVA2 (IVA2) */ 100 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = { 101 { .name = "logic", .rst_shift = 0, .st_shift = 8 }, 102 { .name = "seq0", .rst_shift = 1, .st_shift = 9 }, 103 { .name = "seq1", .rst_shift = 2, .st_shift = 10 }, 104 }; 105 106 static struct omap_hwmod omap3xxx_iva_hwmod = { 107 .name = "iva", 108 .class = &iva_hwmod_class, 109 .clkdm_name = "iva2_clkdm", 110 .rst_lines = omap3xxx_iva_resets, 111 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets), 112 .main_clk = "iva2_ck", 113 .prcm = { 114 .omap2 = { 115 .module_offs = OMAP3430_IVA2_MOD, 116 .prcm_reg_id = 1, 117 .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, 118 .idlest_reg_id = 1, 119 .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT, 120 }, 121 }, 122 }; 123 124 /* 125 * 'debugss' class 126 * debug and emulation sub system 127 */ 128 129 static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = { 130 .name = "debugss", 131 }; 132 133 /* debugss */ 134 static struct omap_hwmod omap3xxx_debugss_hwmod = { 135 .name = "debugss", 136 .class = &omap3xxx_debugss_hwmod_class, 137 .clkdm_name = "emu_clkdm", 138 .main_clk = "emu_src_ck", 139 .flags = HWMOD_NO_IDLEST, 140 }; 141 142 /* timer class */ 143 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { 144 .rev_offs = 0x0000, 145 .sysc_offs = 0x0010, 146 .syss_offs = 0x0014, 147 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | 148 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 149 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | 150 SYSS_HAS_RESET_STATUS), 151 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 152 .sysc_fields = &omap_hwmod_sysc_type1, 153 }; 154 155 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { 156 .name = "timer", 157 .sysc = &omap3xxx_timer_sysc, 158 }; 159 160 /* secure timers dev attribute */ 161 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = { 162 .timer_capability = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE, 163 }; 164 165 /* always-on timers dev attribute */ 166 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { 167 .timer_capability = OMAP_TIMER_ALWON, 168 }; 169 170 /* pwm timers dev attribute */ 171 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { 172 .timer_capability = OMAP_TIMER_HAS_PWM, 173 }; 174 175 /* timers with DSP interrupt dev attribute */ 176 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = { 177 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ, 178 }; 179 180 /* pwm timers with DSP interrupt dev attribute */ 181 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = { 182 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM, 183 }; 184 185 /* timer1 */ 186 static struct omap_hwmod omap3xxx_timer1_hwmod = { 187 .name = "timer1", 188 .main_clk = "gpt1_fck", 189 .prcm = { 190 .omap2 = { 191 .prcm_reg_id = 1, 192 .module_bit = OMAP3430_EN_GPT1_SHIFT, 193 .module_offs = WKUP_MOD, 194 .idlest_reg_id = 1, 195 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT, 196 }, 197 }, 198 .dev_attr = &capability_alwon_dev_attr, 199 .class = &omap3xxx_timer_hwmod_class, 200 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 201 }; 202 203 /* timer2 */ 204 static struct omap_hwmod omap3xxx_timer2_hwmod = { 205 .name = "timer2", 206 .main_clk = "gpt2_fck", 207 .prcm = { 208 .omap2 = { 209 .prcm_reg_id = 1, 210 .module_bit = OMAP3430_EN_GPT2_SHIFT, 211 .module_offs = OMAP3430_PER_MOD, 212 .idlest_reg_id = 1, 213 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT, 214 }, 215 }, 216 .class = &omap3xxx_timer_hwmod_class, 217 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 218 }; 219 220 /* timer3 */ 221 static struct omap_hwmod omap3xxx_timer3_hwmod = { 222 .name = "timer3", 223 .main_clk = "gpt3_fck", 224 .prcm = { 225 .omap2 = { 226 .prcm_reg_id = 1, 227 .module_bit = OMAP3430_EN_GPT3_SHIFT, 228 .module_offs = OMAP3430_PER_MOD, 229 .idlest_reg_id = 1, 230 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT, 231 }, 232 }, 233 .class = &omap3xxx_timer_hwmod_class, 234 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 235 }; 236 237 /* timer4 */ 238 static struct omap_hwmod omap3xxx_timer4_hwmod = { 239 .name = "timer4", 240 .main_clk = "gpt4_fck", 241 .prcm = { 242 .omap2 = { 243 .prcm_reg_id = 1, 244 .module_bit = OMAP3430_EN_GPT4_SHIFT, 245 .module_offs = OMAP3430_PER_MOD, 246 .idlest_reg_id = 1, 247 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT, 248 }, 249 }, 250 .class = &omap3xxx_timer_hwmod_class, 251 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 252 }; 253 254 /* timer5 */ 255 static struct omap_hwmod omap3xxx_timer5_hwmod = { 256 .name = "timer5", 257 .main_clk = "gpt5_fck", 258 .prcm = { 259 .omap2 = { 260 .prcm_reg_id = 1, 261 .module_bit = OMAP3430_EN_GPT5_SHIFT, 262 .module_offs = OMAP3430_PER_MOD, 263 .idlest_reg_id = 1, 264 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT, 265 }, 266 }, 267 .dev_attr = &capability_dsp_dev_attr, 268 .class = &omap3xxx_timer_hwmod_class, 269 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 270 }; 271 272 /* timer6 */ 273 static struct omap_hwmod omap3xxx_timer6_hwmod = { 274 .name = "timer6", 275 .main_clk = "gpt6_fck", 276 .prcm = { 277 .omap2 = { 278 .prcm_reg_id = 1, 279 .module_bit = OMAP3430_EN_GPT6_SHIFT, 280 .module_offs = OMAP3430_PER_MOD, 281 .idlest_reg_id = 1, 282 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT, 283 }, 284 }, 285 .dev_attr = &capability_dsp_dev_attr, 286 .class = &omap3xxx_timer_hwmod_class, 287 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 288 }; 289 290 /* timer7 */ 291 static struct omap_hwmod omap3xxx_timer7_hwmod = { 292 .name = "timer7", 293 .main_clk = "gpt7_fck", 294 .prcm = { 295 .omap2 = { 296 .prcm_reg_id = 1, 297 .module_bit = OMAP3430_EN_GPT7_SHIFT, 298 .module_offs = OMAP3430_PER_MOD, 299 .idlest_reg_id = 1, 300 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT, 301 }, 302 }, 303 .dev_attr = &capability_dsp_dev_attr, 304 .class = &omap3xxx_timer_hwmod_class, 305 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 306 }; 307 308 /* timer8 */ 309 static struct omap_hwmod omap3xxx_timer8_hwmod = { 310 .name = "timer8", 311 .main_clk = "gpt8_fck", 312 .prcm = { 313 .omap2 = { 314 .prcm_reg_id = 1, 315 .module_bit = OMAP3430_EN_GPT8_SHIFT, 316 .module_offs = OMAP3430_PER_MOD, 317 .idlest_reg_id = 1, 318 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT, 319 }, 320 }, 321 .dev_attr = &capability_dsp_pwm_dev_attr, 322 .class = &omap3xxx_timer_hwmod_class, 323 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 324 }; 325 326 /* timer9 */ 327 static struct omap_hwmod omap3xxx_timer9_hwmod = { 328 .name = "timer9", 329 .main_clk = "gpt9_fck", 330 .prcm = { 331 .omap2 = { 332 .prcm_reg_id = 1, 333 .module_bit = OMAP3430_EN_GPT9_SHIFT, 334 .module_offs = OMAP3430_PER_MOD, 335 .idlest_reg_id = 1, 336 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT, 337 }, 338 }, 339 .dev_attr = &capability_pwm_dev_attr, 340 .class = &omap3xxx_timer_hwmod_class, 341 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 342 }; 343 344 /* timer10 */ 345 static struct omap_hwmod omap3xxx_timer10_hwmod = { 346 .name = "timer10", 347 .main_clk = "gpt10_fck", 348 .prcm = { 349 .omap2 = { 350 .prcm_reg_id = 1, 351 .module_bit = OMAP3430_EN_GPT10_SHIFT, 352 .module_offs = CORE_MOD, 353 .idlest_reg_id = 1, 354 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT, 355 }, 356 }, 357 .dev_attr = &capability_pwm_dev_attr, 358 .class = &omap3xxx_timer_hwmod_class, 359 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 360 }; 361 362 /* timer11 */ 363 static struct omap_hwmod omap3xxx_timer11_hwmod = { 364 .name = "timer11", 365 .main_clk = "gpt11_fck", 366 .prcm = { 367 .omap2 = { 368 .prcm_reg_id = 1, 369 .module_bit = OMAP3430_EN_GPT11_SHIFT, 370 .module_offs = CORE_MOD, 371 .idlest_reg_id = 1, 372 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT, 373 }, 374 }, 375 .dev_attr = &capability_pwm_dev_attr, 376 .class = &omap3xxx_timer_hwmod_class, 377 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 378 }; 379 380 /* timer12 */ 381 382 static struct omap_hwmod omap3xxx_timer12_hwmod = { 383 .name = "timer12", 384 .main_clk = "gpt12_fck", 385 .prcm = { 386 .omap2 = { 387 .prcm_reg_id = 1, 388 .module_bit = OMAP3430_EN_GPT12_SHIFT, 389 .module_offs = WKUP_MOD, 390 .idlest_reg_id = 1, 391 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT, 392 }, 393 }, 394 .dev_attr = &capability_secure_dev_attr, 395 .class = &omap3xxx_timer_hwmod_class, 396 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 397 }; 398 399 /* 400 * 'wd_timer' class 401 * 32-bit watchdog upward counter that generates a pulse on the reset pin on 402 * overflow condition 403 */ 404 405 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { 406 .rev_offs = 0x0000, 407 .sysc_offs = 0x0010, 408 .syss_offs = 0x0014, 409 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | 410 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 411 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | 412 SYSS_HAS_RESET_STATUS), 413 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 414 .sysc_fields = &omap_hwmod_sysc_type1, 415 }; 416 417 /* I2C common */ 418 static struct omap_hwmod_class_sysconfig i2c_sysc = { 419 .rev_offs = 0x00, 420 .sysc_offs = 0x20, 421 .syss_offs = 0x10, 422 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 423 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 424 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 425 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 426 .sysc_fields = &omap_hwmod_sysc_type1, 427 }; 428 429 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { 430 .name = "wd_timer", 431 .sysc = &omap3xxx_wd_timer_sysc, 432 .pre_shutdown = &omap2_wd_timer_disable, 433 .reset = &omap2_wd_timer_reset, 434 }; 435 436 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { 437 .name = "wd_timer2", 438 .class = &omap3xxx_wd_timer_hwmod_class, 439 .main_clk = "wdt2_fck", 440 .prcm = { 441 .omap2 = { 442 .prcm_reg_id = 1, 443 .module_bit = OMAP3430_EN_WDT2_SHIFT, 444 .module_offs = WKUP_MOD, 445 .idlest_reg_id = 1, 446 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, 447 }, 448 }, 449 /* 450 * XXX: Use software supervised mode, HW supervised smartidle seems to 451 * block CORE power domain idle transitions. Maybe a HW bug in wdt2? 452 */ 453 .flags = HWMOD_SWSUP_SIDLE, 454 }; 455 456 /* UART1 */ 457 static struct omap_hwmod omap3xxx_uart1_hwmod = { 458 .name = "uart1", 459 .main_clk = "uart1_fck", 460 .flags = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE, 461 .prcm = { 462 .omap2 = { 463 .module_offs = CORE_MOD, 464 .prcm_reg_id = 1, 465 .module_bit = OMAP3430_EN_UART1_SHIFT, 466 .idlest_reg_id = 1, 467 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, 468 }, 469 }, 470 .class = &omap2_uart_class, 471 }; 472 473 /* UART2 */ 474 static struct omap_hwmod omap3xxx_uart2_hwmod = { 475 .name = "uart2", 476 .main_clk = "uart2_fck", 477 .flags = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE, 478 .prcm = { 479 .omap2 = { 480 .module_offs = CORE_MOD, 481 .prcm_reg_id = 1, 482 .module_bit = OMAP3430_EN_UART2_SHIFT, 483 .idlest_reg_id = 1, 484 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, 485 }, 486 }, 487 .class = &omap2_uart_class, 488 }; 489 490 /* UART3 */ 491 static struct omap_hwmod omap3xxx_uart3_hwmod = { 492 .name = "uart3", 493 .main_clk = "uart3_fck", 494 .flags = DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS | 495 HWMOD_SWSUP_SIDLE, 496 .prcm = { 497 .omap2 = { 498 .module_offs = OMAP3430_PER_MOD, 499 .prcm_reg_id = 1, 500 .module_bit = OMAP3430_EN_UART3_SHIFT, 501 .idlest_reg_id = 1, 502 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, 503 }, 504 }, 505 .class = &omap2_uart_class, 506 }; 507 508 /* UART4 */ 509 510 511 static struct omap_hwmod omap36xx_uart4_hwmod = { 512 .name = "uart4", 513 .main_clk = "uart4_fck", 514 .flags = DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE, 515 .prcm = { 516 .omap2 = { 517 .module_offs = OMAP3430_PER_MOD, 518 .prcm_reg_id = 1, 519 .module_bit = OMAP3630_EN_UART4_SHIFT, 520 .idlest_reg_id = 1, 521 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, 522 }, 523 }, 524 .class = &omap2_uart_class, 525 }; 526 527 528 529 /* 530 * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or 531 * uart2_fck being enabled. So we add uart1_fck as an optional clock, 532 * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET. This really 533 * should not be needed. The functional clock structure of the AM35xx 534 * UART4 is extremely unclear and opaque; it is unclear what the role 535 * of uart1/2_fck is for the UART4. Any clarification from either 536 * empirical testing or the AM3505/3517 hardware designers would be 537 * most welcome. 538 */ 539 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = { 540 { .role = "softreset_uart1_fck", .clk = "uart1_fck" }, 541 }; 542 543 static struct omap_hwmod am35xx_uart4_hwmod = { 544 .name = "uart4", 545 .main_clk = "uart4_fck", 546 .prcm = { 547 .omap2 = { 548 .module_offs = CORE_MOD, 549 .prcm_reg_id = 1, 550 .module_bit = AM35XX_EN_UART4_SHIFT, 551 .idlest_reg_id = 1, 552 .idlest_idle_bit = AM35XX_ST_UART4_SHIFT, 553 }, 554 }, 555 .opt_clks = am35xx_uart4_opt_clks, 556 .opt_clks_cnt = ARRAY_SIZE(am35xx_uart4_opt_clks), 557 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 558 .class = &omap2_uart_class, 559 }; 560 561 static struct omap_hwmod_class i2c_class = { 562 .name = "i2c", 563 .sysc = &i2c_sysc, 564 .rev = OMAP_I2C_IP_VERSION_1, 565 .reset = &omap_i2c_reset, 566 }; 567 568 /* dss */ 569 static struct omap_hwmod_opt_clk dss_opt_clks[] = { 570 /* 571 * The DSS HW needs all DSS clocks enabled during reset. The dss_core 572 * driver does not use these clocks. 573 */ 574 { .role = "sys_clk", .clk = "dss2_alwon_fck" }, 575 { .role = "tv_clk", .clk = "dss_tv_fck" }, 576 /* required only on OMAP3430 */ 577 { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, 578 }; 579 580 static struct omap_hwmod omap3430es1_dss_core_hwmod = { 581 .name = "dss_core", 582 .class = &omap2_dss_hwmod_class, 583 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ 584 .prcm = { 585 .omap2 = { 586 .prcm_reg_id = 1, 587 .module_bit = OMAP3430_EN_DSS1_SHIFT, 588 .module_offs = OMAP3430_DSS_MOD, 589 .idlest_reg_id = 1, 590 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT, 591 }, 592 }, 593 .opt_clks = dss_opt_clks, 594 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), 595 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, 596 }; 597 598 static struct omap_hwmod omap3xxx_dss_core_hwmod = { 599 .name = "dss_core", 600 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 601 .class = &omap2_dss_hwmod_class, 602 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ 603 .prcm = { 604 .omap2 = { 605 .prcm_reg_id = 1, 606 .module_bit = OMAP3430_EN_DSS1_SHIFT, 607 .module_offs = OMAP3430_DSS_MOD, 608 .idlest_reg_id = 1, 609 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT, 610 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT, 611 }, 612 }, 613 .opt_clks = dss_opt_clks, 614 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), 615 }; 616 617 /* 618 * 'dispc' class 619 * display controller 620 */ 621 622 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = { 623 .rev_offs = 0x0000, 624 .sysc_offs = 0x0010, 625 .syss_offs = 0x0014, 626 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | 627 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | 628 SYSC_HAS_ENAWAKEUP), 629 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 630 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 631 .sysc_fields = &omap_hwmod_sysc_type1, 632 }; 633 634 static struct omap_hwmod_class omap3_dispc_hwmod_class = { 635 .name = "dispc", 636 .sysc = &omap3_dispc_sysc, 637 }; 638 639 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { 640 .name = "dss_dispc", 641 .class = &omap3_dispc_hwmod_class, 642 .main_clk = "dss1_alwon_fck", 643 .prcm = { 644 .omap2 = { 645 .prcm_reg_id = 1, 646 .module_bit = OMAP3430_EN_DSS1_SHIFT, 647 .module_offs = OMAP3430_DSS_MOD, 648 }, 649 }, 650 .flags = HWMOD_NO_IDLEST, 651 .dev_attr = &omap2_3_dss_dispc_dev_attr, 652 }; 653 654 /* 655 * 'dsi' class 656 * display serial interface controller 657 */ 658 659 static struct omap_hwmod_class_sysconfig omap3xxx_dsi_sysc = { 660 .rev_offs = 0x0000, 661 .sysc_offs = 0x0010, 662 .syss_offs = 0x0014, 663 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | 664 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | 665 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 666 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 667 .sysc_fields = &omap_hwmod_sysc_type1, 668 }; 669 670 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = { 671 .name = "dsi", 672 .sysc = &omap3xxx_dsi_sysc, 673 }; 674 675 /* dss_dsi1 */ 676 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { 677 { .role = "sys_clk", .clk = "dss2_alwon_fck" }, 678 }; 679 680 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { 681 .name = "dss_dsi1", 682 .class = &omap3xxx_dsi_hwmod_class, 683 .main_clk = "dss1_alwon_fck", 684 .prcm = { 685 .omap2 = { 686 .prcm_reg_id = 1, 687 .module_bit = OMAP3430_EN_DSS1_SHIFT, 688 .module_offs = OMAP3430_DSS_MOD, 689 }, 690 }, 691 .opt_clks = dss_dsi1_opt_clks, 692 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), 693 .flags = HWMOD_NO_IDLEST, 694 }; 695 696 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { 697 { .role = "ick", .clk = "dss_ick" }, 698 }; 699 700 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { 701 .name = "dss_rfbi", 702 .class = &omap2_rfbi_hwmod_class, 703 .main_clk = "dss1_alwon_fck", 704 .prcm = { 705 .omap2 = { 706 .prcm_reg_id = 1, 707 .module_bit = OMAP3430_EN_DSS1_SHIFT, 708 .module_offs = OMAP3430_DSS_MOD, 709 }, 710 }, 711 .opt_clks = dss_rfbi_opt_clks, 712 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), 713 .flags = HWMOD_NO_IDLEST, 714 }; 715 716 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = { 717 /* required only on OMAP3430 */ 718 { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, 719 }; 720 721 static struct omap_hwmod omap3xxx_dss_venc_hwmod = { 722 .name = "dss_venc", 723 .class = &omap2_venc_hwmod_class, 724 .main_clk = "dss_tv_fck", 725 .prcm = { 726 .omap2 = { 727 .prcm_reg_id = 1, 728 .module_bit = OMAP3430_EN_DSS1_SHIFT, 729 .module_offs = OMAP3430_DSS_MOD, 730 }, 731 }, 732 .opt_clks = dss_venc_opt_clks, 733 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks), 734 .flags = HWMOD_NO_IDLEST, 735 }; 736 737 /* I2C1 */ 738 static struct omap_i2c_dev_attr i2c1_dev_attr = { 739 .fifo_depth = 8, /* bytes */ 740 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2, 741 }; 742 743 static struct omap_hwmod omap3xxx_i2c1_hwmod = { 744 .name = "i2c1", 745 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 746 .main_clk = "i2c1_fck", 747 .prcm = { 748 .omap2 = { 749 .module_offs = CORE_MOD, 750 .prcm_reg_id = 1, 751 .module_bit = OMAP3430_EN_I2C1_SHIFT, 752 .idlest_reg_id = 1, 753 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT, 754 }, 755 }, 756 .class = &i2c_class, 757 .dev_attr = &i2c1_dev_attr, 758 }; 759 760 /* I2C2 */ 761 static struct omap_i2c_dev_attr i2c2_dev_attr = { 762 .fifo_depth = 8, /* bytes */ 763 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2, 764 }; 765 766 static struct omap_hwmod omap3xxx_i2c2_hwmod = { 767 .name = "i2c2", 768 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 769 .main_clk = "i2c2_fck", 770 .prcm = { 771 .omap2 = { 772 .module_offs = CORE_MOD, 773 .prcm_reg_id = 1, 774 .module_bit = OMAP3430_EN_I2C2_SHIFT, 775 .idlest_reg_id = 1, 776 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT, 777 }, 778 }, 779 .class = &i2c_class, 780 .dev_attr = &i2c2_dev_attr, 781 }; 782 783 /* I2C3 */ 784 static struct omap_i2c_dev_attr i2c3_dev_attr = { 785 .fifo_depth = 64, /* bytes */ 786 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2, 787 }; 788 789 790 791 static struct omap_hwmod omap3xxx_i2c3_hwmod = { 792 .name = "i2c3", 793 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 794 .main_clk = "i2c3_fck", 795 .prcm = { 796 .omap2 = { 797 .module_offs = CORE_MOD, 798 .prcm_reg_id = 1, 799 .module_bit = OMAP3430_EN_I2C3_SHIFT, 800 .idlest_reg_id = 1, 801 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT, 802 }, 803 }, 804 .class = &i2c_class, 805 .dev_attr = &i2c3_dev_attr, 806 }; 807 808 /* 809 * 'gpio' class 810 * general purpose io module 811 */ 812 813 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = { 814 .rev_offs = 0x0000, 815 .sysc_offs = 0x0010, 816 .syss_offs = 0x0014, 817 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | 818 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | 819 SYSS_HAS_RESET_STATUS), 820 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 821 .sysc_fields = &omap_hwmod_sysc_type1, 822 }; 823 824 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = { 825 .name = "gpio", 826 .sysc = &omap3xxx_gpio_sysc, 827 .rev = 1, 828 }; 829 830 /* gpio_dev_attr */ 831 static struct omap_gpio_dev_attr gpio_dev_attr = { 832 .bank_width = 32, 833 .dbck_flag = true, 834 }; 835 836 /* gpio1 */ 837 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { 838 { .role = "dbclk", .clk = "gpio1_dbck", }, 839 }; 840 841 static struct omap_hwmod omap3xxx_gpio1_hwmod = { 842 .name = "gpio1", 843 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 844 .main_clk = "gpio1_ick", 845 .opt_clks = gpio1_opt_clks, 846 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), 847 .prcm = { 848 .omap2 = { 849 .prcm_reg_id = 1, 850 .module_bit = OMAP3430_EN_GPIO1_SHIFT, 851 .module_offs = WKUP_MOD, 852 .idlest_reg_id = 1, 853 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT, 854 }, 855 }, 856 .class = &omap3xxx_gpio_hwmod_class, 857 .dev_attr = &gpio_dev_attr, 858 }; 859 860 /* gpio2 */ 861 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { 862 { .role = "dbclk", .clk = "gpio2_dbck", }, 863 }; 864 865 static struct omap_hwmod omap3xxx_gpio2_hwmod = { 866 .name = "gpio2", 867 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 868 .main_clk = "gpio2_ick", 869 .opt_clks = gpio2_opt_clks, 870 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), 871 .prcm = { 872 .omap2 = { 873 .prcm_reg_id = 1, 874 .module_bit = OMAP3430_EN_GPIO2_SHIFT, 875 .module_offs = OMAP3430_PER_MOD, 876 .idlest_reg_id = 1, 877 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT, 878 }, 879 }, 880 .class = &omap3xxx_gpio_hwmod_class, 881 .dev_attr = &gpio_dev_attr, 882 }; 883 884 /* gpio3 */ 885 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { 886 { .role = "dbclk", .clk = "gpio3_dbck", }, 887 }; 888 889 static struct omap_hwmod omap3xxx_gpio3_hwmod = { 890 .name = "gpio3", 891 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 892 .main_clk = "gpio3_ick", 893 .opt_clks = gpio3_opt_clks, 894 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), 895 .prcm = { 896 .omap2 = { 897 .prcm_reg_id = 1, 898 .module_bit = OMAP3430_EN_GPIO3_SHIFT, 899 .module_offs = OMAP3430_PER_MOD, 900 .idlest_reg_id = 1, 901 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT, 902 }, 903 }, 904 .class = &omap3xxx_gpio_hwmod_class, 905 .dev_attr = &gpio_dev_attr, 906 }; 907 908 /* gpio4 */ 909 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { 910 { .role = "dbclk", .clk = "gpio4_dbck", }, 911 }; 912 913 static struct omap_hwmod omap3xxx_gpio4_hwmod = { 914 .name = "gpio4", 915 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 916 .main_clk = "gpio4_ick", 917 .opt_clks = gpio4_opt_clks, 918 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), 919 .prcm = { 920 .omap2 = { 921 .prcm_reg_id = 1, 922 .module_bit = OMAP3430_EN_GPIO4_SHIFT, 923 .module_offs = OMAP3430_PER_MOD, 924 .idlest_reg_id = 1, 925 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT, 926 }, 927 }, 928 .class = &omap3xxx_gpio_hwmod_class, 929 .dev_attr = &gpio_dev_attr, 930 }; 931 932 /* gpio5 */ 933 934 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { 935 { .role = "dbclk", .clk = "gpio5_dbck", }, 936 }; 937 938 static struct omap_hwmod omap3xxx_gpio5_hwmod = { 939 .name = "gpio5", 940 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 941 .main_clk = "gpio5_ick", 942 .opt_clks = gpio5_opt_clks, 943 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), 944 .prcm = { 945 .omap2 = { 946 .prcm_reg_id = 1, 947 .module_bit = OMAP3430_EN_GPIO5_SHIFT, 948 .module_offs = OMAP3430_PER_MOD, 949 .idlest_reg_id = 1, 950 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT, 951 }, 952 }, 953 .class = &omap3xxx_gpio_hwmod_class, 954 .dev_attr = &gpio_dev_attr, 955 }; 956 957 /* gpio6 */ 958 959 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { 960 { .role = "dbclk", .clk = "gpio6_dbck", }, 961 }; 962 963 static struct omap_hwmod omap3xxx_gpio6_hwmod = { 964 .name = "gpio6", 965 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 966 .main_clk = "gpio6_ick", 967 .opt_clks = gpio6_opt_clks, 968 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), 969 .prcm = { 970 .omap2 = { 971 .prcm_reg_id = 1, 972 .module_bit = OMAP3430_EN_GPIO6_SHIFT, 973 .module_offs = OMAP3430_PER_MOD, 974 .idlest_reg_id = 1, 975 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT, 976 }, 977 }, 978 .class = &omap3xxx_gpio_hwmod_class, 979 .dev_attr = &gpio_dev_attr, 980 }; 981 982 /* dma attributes */ 983 static struct omap_dma_dev_attr dma_dev_attr = { 984 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | 985 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, 986 .lch_count = 32, 987 }; 988 989 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = { 990 .rev_offs = 0x0000, 991 .sysc_offs = 0x002c, 992 .syss_offs = 0x0028, 993 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 994 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | 995 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | 996 SYSS_HAS_RESET_STATUS), 997 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 998 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 999 .sysc_fields = &omap_hwmod_sysc_type1, 1000 }; 1001 1002 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = { 1003 .name = "dma", 1004 .sysc = &omap3xxx_dma_sysc, 1005 }; 1006 1007 /* dma_system */ 1008 static struct omap_hwmod omap3xxx_dma_system_hwmod = { 1009 .name = "dma", 1010 .class = &omap3xxx_dma_hwmod_class, 1011 .main_clk = "core_l3_ick", 1012 .prcm = { 1013 .omap2 = { 1014 .module_offs = CORE_MOD, 1015 .prcm_reg_id = 1, 1016 .module_bit = OMAP3430_ST_SDMA_SHIFT, 1017 .idlest_reg_id = 1, 1018 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT, 1019 }, 1020 }, 1021 .dev_attr = &dma_dev_attr, 1022 .flags = HWMOD_NO_IDLEST, 1023 }; 1024 1025 /* 1026 * 'mcbsp' class 1027 * multi channel buffered serial port controller 1028 */ 1029 1030 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = { 1031 .sysc_offs = 0x008c, 1032 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | 1033 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), 1034 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1035 .sysc_fields = &omap_hwmod_sysc_type1, 1036 }; 1037 1038 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = { 1039 .name = "mcbsp", 1040 .sysc = &omap3xxx_mcbsp_sysc, 1041 .rev = MCBSP_CONFIG_TYPE3, 1042 }; 1043 1044 /* McBSP functional clock mapping */ 1045 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = { 1046 { .role = "pad_fck", .clk = "mcbsp_clks" }, 1047 { .role = "prcm_fck", .clk = "core_96m_fck" }, 1048 }; 1049 1050 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = { 1051 { .role = "pad_fck", .clk = "mcbsp_clks" }, 1052 { .role = "prcm_fck", .clk = "per_96m_fck" }, 1053 }; 1054 1055 /* mcbsp1 */ 1056 1057 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { 1058 .name = "mcbsp1", 1059 .class = &omap3xxx_mcbsp_hwmod_class, 1060 .main_clk = "mcbsp1_fck", 1061 .prcm = { 1062 .omap2 = { 1063 .prcm_reg_id = 1, 1064 .module_bit = OMAP3430_EN_MCBSP1_SHIFT, 1065 .module_offs = CORE_MOD, 1066 .idlest_reg_id = 1, 1067 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, 1068 }, 1069 }, 1070 .opt_clks = mcbsp15_opt_clks, 1071 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks), 1072 }; 1073 1074 /* mcbsp2 */ 1075 1076 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { 1077 .sidetone = "mcbsp2_sidetone", 1078 }; 1079 1080 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { 1081 .name = "mcbsp2", 1082 .class = &omap3xxx_mcbsp_hwmod_class, 1083 .main_clk = "mcbsp2_fck", 1084 .prcm = { 1085 .omap2 = { 1086 .prcm_reg_id = 1, 1087 .module_bit = OMAP3430_EN_MCBSP2_SHIFT, 1088 .module_offs = OMAP3430_PER_MOD, 1089 .idlest_reg_id = 1, 1090 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, 1091 }, 1092 }, 1093 .opt_clks = mcbsp234_opt_clks, 1094 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), 1095 .dev_attr = &omap34xx_mcbsp2_dev_attr, 1096 }; 1097 1098 /* mcbsp3 */ 1099 1100 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { 1101 .sidetone = "mcbsp3_sidetone", 1102 }; 1103 1104 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { 1105 .name = "mcbsp3", 1106 .class = &omap3xxx_mcbsp_hwmod_class, 1107 .main_clk = "mcbsp3_fck", 1108 .prcm = { 1109 .omap2 = { 1110 .prcm_reg_id = 1, 1111 .module_bit = OMAP3430_EN_MCBSP3_SHIFT, 1112 .module_offs = OMAP3430_PER_MOD, 1113 .idlest_reg_id = 1, 1114 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, 1115 }, 1116 }, 1117 .opt_clks = mcbsp234_opt_clks, 1118 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), 1119 .dev_attr = &omap34xx_mcbsp3_dev_attr, 1120 }; 1121 1122 /* mcbsp4 */ 1123 1124 1125 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { 1126 .name = "mcbsp4", 1127 .class = &omap3xxx_mcbsp_hwmod_class, 1128 .main_clk = "mcbsp4_fck", 1129 .prcm = { 1130 .omap2 = { 1131 .prcm_reg_id = 1, 1132 .module_bit = OMAP3430_EN_MCBSP4_SHIFT, 1133 .module_offs = OMAP3430_PER_MOD, 1134 .idlest_reg_id = 1, 1135 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, 1136 }, 1137 }, 1138 .opt_clks = mcbsp234_opt_clks, 1139 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), 1140 }; 1141 1142 /* mcbsp5 */ 1143 1144 1145 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { 1146 .name = "mcbsp5", 1147 .class = &omap3xxx_mcbsp_hwmod_class, 1148 .main_clk = "mcbsp5_fck", 1149 .prcm = { 1150 .omap2 = { 1151 .prcm_reg_id = 1, 1152 .module_bit = OMAP3430_EN_MCBSP5_SHIFT, 1153 .module_offs = CORE_MOD, 1154 .idlest_reg_id = 1, 1155 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, 1156 }, 1157 }, 1158 .opt_clks = mcbsp15_opt_clks, 1159 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks), 1160 }; 1161 1162 /* 'mcbsp sidetone' class */ 1163 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = { 1164 .sysc_offs = 0x0010, 1165 .sysc_flags = SYSC_HAS_AUTOIDLE, 1166 .sysc_fields = &omap_hwmod_sysc_type1, 1167 }; 1168 1169 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = { 1170 .name = "mcbsp_sidetone", 1171 .sysc = &omap3xxx_mcbsp_sidetone_sysc, 1172 }; 1173 1174 /* mcbsp2_sidetone */ 1175 1176 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { 1177 .name = "mcbsp2_sidetone", 1178 .class = &omap3xxx_mcbsp_sidetone_hwmod_class, 1179 .main_clk = "mcbsp2_ick", 1180 .flags = HWMOD_NO_IDLEST, 1181 }; 1182 1183 /* mcbsp3_sidetone */ 1184 1185 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { 1186 .name = "mcbsp3_sidetone", 1187 .class = &omap3xxx_mcbsp_sidetone_hwmod_class, 1188 .main_clk = "mcbsp3_ick", 1189 .flags = HWMOD_NO_IDLEST, 1190 }; 1191 1192 /* SR common */ 1193 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { 1194 .clkact_shift = 20, 1195 }; 1196 1197 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = { 1198 .sysc_offs = 0x24, 1199 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE), 1200 .sysc_fields = &omap34xx_sr_sysc_fields, 1201 }; 1202 1203 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = { 1204 .name = "smartreflex", 1205 .sysc = &omap34xx_sr_sysc, 1206 .rev = 1, 1207 }; 1208 1209 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = { 1210 .sidle_shift = 24, 1211 .enwkup_shift = 26, 1212 }; 1213 1214 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = { 1215 .sysc_offs = 0x38, 1216 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1217 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | 1218 SYSC_NO_CACHE), 1219 .sysc_fields = &omap36xx_sr_sysc_fields, 1220 }; 1221 1222 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = { 1223 .name = "smartreflex", 1224 .sysc = &omap36xx_sr_sysc, 1225 .rev = 2, 1226 }; 1227 1228 /* SR1 */ 1229 static struct omap_smartreflex_dev_attr sr1_dev_attr = { 1230 .sensor_voltdm_name = "mpu_iva", 1231 }; 1232 1233 1234 static struct omap_hwmod omap34xx_sr1_hwmod = { 1235 .name = "smartreflex_mpu_iva", 1236 .class = &omap34xx_smartreflex_hwmod_class, 1237 .main_clk = "sr1_fck", 1238 .prcm = { 1239 .omap2 = { 1240 .prcm_reg_id = 1, 1241 .module_bit = OMAP3430_EN_SR1_SHIFT, 1242 .module_offs = WKUP_MOD, 1243 .idlest_reg_id = 1, 1244 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, 1245 }, 1246 }, 1247 .dev_attr = &sr1_dev_attr, 1248 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 1249 }; 1250 1251 static struct omap_hwmod omap36xx_sr1_hwmod = { 1252 .name = "smartreflex_mpu_iva", 1253 .class = &omap36xx_smartreflex_hwmod_class, 1254 .main_clk = "sr1_fck", 1255 .prcm = { 1256 .omap2 = { 1257 .prcm_reg_id = 1, 1258 .module_bit = OMAP3430_EN_SR1_SHIFT, 1259 .module_offs = WKUP_MOD, 1260 .idlest_reg_id = 1, 1261 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, 1262 }, 1263 }, 1264 .dev_attr = &sr1_dev_attr, 1265 }; 1266 1267 /* SR2 */ 1268 static struct omap_smartreflex_dev_attr sr2_dev_attr = { 1269 .sensor_voltdm_name = "core", 1270 }; 1271 1272 1273 static struct omap_hwmod omap34xx_sr2_hwmod = { 1274 .name = "smartreflex_core", 1275 .class = &omap34xx_smartreflex_hwmod_class, 1276 .main_clk = "sr2_fck", 1277 .prcm = { 1278 .omap2 = { 1279 .prcm_reg_id = 1, 1280 .module_bit = OMAP3430_EN_SR2_SHIFT, 1281 .module_offs = WKUP_MOD, 1282 .idlest_reg_id = 1, 1283 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, 1284 }, 1285 }, 1286 .dev_attr = &sr2_dev_attr, 1287 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 1288 }; 1289 1290 static struct omap_hwmod omap36xx_sr2_hwmod = { 1291 .name = "smartreflex_core", 1292 .class = &omap36xx_smartreflex_hwmod_class, 1293 .main_clk = "sr2_fck", 1294 .prcm = { 1295 .omap2 = { 1296 .prcm_reg_id = 1, 1297 .module_bit = OMAP3430_EN_SR2_SHIFT, 1298 .module_offs = WKUP_MOD, 1299 .idlest_reg_id = 1, 1300 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, 1301 }, 1302 }, 1303 .dev_attr = &sr2_dev_attr, 1304 }; 1305 1306 /* 1307 * 'mailbox' class 1308 * mailbox module allowing communication between the on-chip processors 1309 * using a queued mailbox-interrupt mechanism. 1310 */ 1311 1312 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = { 1313 .rev_offs = 0x000, 1314 .sysc_offs = 0x010, 1315 .syss_offs = 0x014, 1316 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1317 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), 1318 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1319 .sysc_fields = &omap_hwmod_sysc_type1, 1320 }; 1321 1322 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = { 1323 .name = "mailbox", 1324 .sysc = &omap3xxx_mailbox_sysc, 1325 }; 1326 1327 static struct omap_hwmod omap3xxx_mailbox_hwmod = { 1328 .name = "mailbox", 1329 .class = &omap3xxx_mailbox_hwmod_class, 1330 .main_clk = "mailboxes_ick", 1331 .prcm = { 1332 .omap2 = { 1333 .prcm_reg_id = 1, 1334 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT, 1335 .module_offs = CORE_MOD, 1336 .idlest_reg_id = 1, 1337 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT, 1338 }, 1339 }, 1340 }; 1341 1342 /* 1343 * 'mcspi' class 1344 * multichannel serial port interface (mcspi) / master/slave synchronous serial 1345 * bus 1346 */ 1347 1348 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = { 1349 .rev_offs = 0x0000, 1350 .sysc_offs = 0x0010, 1351 .syss_offs = 0x0014, 1352 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1353 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 1354 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 1355 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1356 .sysc_fields = &omap_hwmod_sysc_type1, 1357 }; 1358 1359 static struct omap_hwmod_class omap34xx_mcspi_class = { 1360 .name = "mcspi", 1361 .sysc = &omap34xx_mcspi_sysc, 1362 .rev = OMAP3_MCSPI_REV, 1363 }; 1364 1365 /* mcspi1 */ 1366 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { 1367 .num_chipselect = 4, 1368 }; 1369 1370 static struct omap_hwmod omap34xx_mcspi1 = { 1371 .name = "mcspi1", 1372 .main_clk = "mcspi1_fck", 1373 .prcm = { 1374 .omap2 = { 1375 .module_offs = CORE_MOD, 1376 .prcm_reg_id = 1, 1377 .module_bit = OMAP3430_EN_MCSPI1_SHIFT, 1378 .idlest_reg_id = 1, 1379 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT, 1380 }, 1381 }, 1382 .class = &omap34xx_mcspi_class, 1383 .dev_attr = &omap_mcspi1_dev_attr, 1384 }; 1385 1386 /* mcspi2 */ 1387 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { 1388 .num_chipselect = 2, 1389 }; 1390 1391 static struct omap_hwmod omap34xx_mcspi2 = { 1392 .name = "mcspi2", 1393 .main_clk = "mcspi2_fck", 1394 .prcm = { 1395 .omap2 = { 1396 .module_offs = CORE_MOD, 1397 .prcm_reg_id = 1, 1398 .module_bit = OMAP3430_EN_MCSPI2_SHIFT, 1399 .idlest_reg_id = 1, 1400 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT, 1401 }, 1402 }, 1403 .class = &omap34xx_mcspi_class, 1404 .dev_attr = &omap_mcspi2_dev_attr, 1405 }; 1406 1407 /* mcspi3 */ 1408 1409 1410 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { 1411 .num_chipselect = 2, 1412 }; 1413 1414 static struct omap_hwmod omap34xx_mcspi3 = { 1415 .name = "mcspi3", 1416 .main_clk = "mcspi3_fck", 1417 .prcm = { 1418 .omap2 = { 1419 .module_offs = CORE_MOD, 1420 .prcm_reg_id = 1, 1421 .module_bit = OMAP3430_EN_MCSPI3_SHIFT, 1422 .idlest_reg_id = 1, 1423 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT, 1424 }, 1425 }, 1426 .class = &omap34xx_mcspi_class, 1427 .dev_attr = &omap_mcspi3_dev_attr, 1428 }; 1429 1430 /* mcspi4 */ 1431 1432 1433 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { 1434 .num_chipselect = 1, 1435 }; 1436 1437 static struct omap_hwmod omap34xx_mcspi4 = { 1438 .name = "mcspi4", 1439 .main_clk = "mcspi4_fck", 1440 .prcm = { 1441 .omap2 = { 1442 .module_offs = CORE_MOD, 1443 .prcm_reg_id = 1, 1444 .module_bit = OMAP3430_EN_MCSPI4_SHIFT, 1445 .idlest_reg_id = 1, 1446 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT, 1447 }, 1448 }, 1449 .class = &omap34xx_mcspi_class, 1450 .dev_attr = &omap_mcspi4_dev_attr, 1451 }; 1452 1453 /* usbhsotg */ 1454 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = { 1455 .rev_offs = 0x0400, 1456 .sysc_offs = 0x0404, 1457 .syss_offs = 0x0408, 1458 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| 1459 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 1460 SYSC_HAS_AUTOIDLE), 1461 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 1462 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 1463 .sysc_fields = &omap_hwmod_sysc_type1, 1464 }; 1465 1466 static struct omap_hwmod_class usbotg_class = { 1467 .name = "usbotg", 1468 .sysc = &omap3xxx_usbhsotg_sysc, 1469 }; 1470 1471 /* usb_otg_hs */ 1472 1473 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { 1474 .name = "usb_otg_hs", 1475 .main_clk = "hsotgusb_ick", 1476 .prcm = { 1477 .omap2 = { 1478 .prcm_reg_id = 1, 1479 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT, 1480 .module_offs = CORE_MOD, 1481 .idlest_reg_id = 1, 1482 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT, 1483 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT, 1484 }, 1485 }, 1486 .class = &usbotg_class, 1487 1488 /* 1489 * Erratum ID: i479 idle_req / idle_ack mechanism potentially 1490 * broken when autoidle is enabled 1491 * workaround is to disable the autoidle bit at module level. 1492 * 1493 * Enabling the device in any other MIDLEMODE setting but force-idle 1494 * causes core_pwrdm not enter idle states at least on OMAP3630. 1495 * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY 1496 * signal when MIDLEMODE is set to force-idle. 1497 */ 1498 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE | 1499 HWMOD_FORCE_MSTANDBY | HWMOD_RECONFIG_IO_CHAIN, 1500 }; 1501 1502 /* usb_otg_hs */ 1503 1504 static struct omap_hwmod_class am35xx_usbotg_class = { 1505 .name = "am35xx_usbotg", 1506 }; 1507 1508 static struct omap_hwmod am35xx_usbhsotg_hwmod = { 1509 .name = "am35x_otg_hs", 1510 .main_clk = "hsotgusb_fck", 1511 .class = &am35xx_usbotg_class, 1512 .flags = HWMOD_NO_IDLEST, 1513 }; 1514 1515 /* MMC/SD/SDIO common */ 1516 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = { 1517 .rev_offs = 0x1fc, 1518 .sysc_offs = 0x10, 1519 .syss_offs = 0x14, 1520 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1521 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 1522 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 1523 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1524 .sysc_fields = &omap_hwmod_sysc_type1, 1525 }; 1526 1527 static struct omap_hwmod_class omap34xx_mmc_class = { 1528 .name = "mmc", 1529 .sysc = &omap34xx_mmc_sysc, 1530 }; 1531 1532 /* MMC/SD/SDIO1 */ 1533 1534 1535 1536 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = { 1537 { .role = "dbck", .clk = "omap_32k_fck", }, 1538 }; 1539 1540 static struct omap_hsmmc_dev_attr mmc1_dev_attr = { 1541 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, 1542 }; 1543 1544 /* See 35xx errata 2.1.1.128 in SPRZ278F */ 1545 static struct omap_hsmmc_dev_attr mmc1_pre_es3_dev_attr = { 1546 .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT | 1547 OMAP_HSMMC_BROKEN_MULTIBLOCK_READ), 1548 }; 1549 1550 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = { 1551 .name = "mmc1", 1552 .opt_clks = omap34xx_mmc1_opt_clks, 1553 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), 1554 .main_clk = "mmchs1_fck", 1555 .prcm = { 1556 .omap2 = { 1557 .module_offs = CORE_MOD, 1558 .prcm_reg_id = 1, 1559 .module_bit = OMAP3430_EN_MMC1_SHIFT, 1560 .idlest_reg_id = 1, 1561 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, 1562 }, 1563 }, 1564 .dev_attr = &mmc1_pre_es3_dev_attr, 1565 .class = &omap34xx_mmc_class, 1566 }; 1567 1568 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = { 1569 .name = "mmc1", 1570 .opt_clks = omap34xx_mmc1_opt_clks, 1571 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), 1572 .main_clk = "mmchs1_fck", 1573 .prcm = { 1574 .omap2 = { 1575 .module_offs = CORE_MOD, 1576 .prcm_reg_id = 1, 1577 .module_bit = OMAP3430_EN_MMC1_SHIFT, 1578 .idlest_reg_id = 1, 1579 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, 1580 }, 1581 }, 1582 .dev_attr = &mmc1_dev_attr, 1583 .class = &omap34xx_mmc_class, 1584 }; 1585 1586 /* MMC/SD/SDIO2 */ 1587 1588 1589 1590 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = { 1591 { .role = "dbck", .clk = "omap_32k_fck", }, 1592 }; 1593 1594 /* See 35xx errata 2.1.1.128 in SPRZ278F */ 1595 static struct omap_hsmmc_dev_attr mmc2_pre_es3_dev_attr = { 1596 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, 1597 }; 1598 1599 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = { 1600 .name = "mmc2", 1601 .opt_clks = omap34xx_mmc2_opt_clks, 1602 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), 1603 .main_clk = "mmchs2_fck", 1604 .prcm = { 1605 .omap2 = { 1606 .module_offs = CORE_MOD, 1607 .prcm_reg_id = 1, 1608 .module_bit = OMAP3430_EN_MMC2_SHIFT, 1609 .idlest_reg_id = 1, 1610 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, 1611 }, 1612 }, 1613 .dev_attr = &mmc2_pre_es3_dev_attr, 1614 .class = &omap34xx_mmc_class, 1615 }; 1616 1617 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = { 1618 .name = "mmc2", 1619 .opt_clks = omap34xx_mmc2_opt_clks, 1620 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), 1621 .main_clk = "mmchs2_fck", 1622 .prcm = { 1623 .omap2 = { 1624 .module_offs = CORE_MOD, 1625 .prcm_reg_id = 1, 1626 .module_bit = OMAP3430_EN_MMC2_SHIFT, 1627 .idlest_reg_id = 1, 1628 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, 1629 }, 1630 }, 1631 .class = &omap34xx_mmc_class, 1632 }; 1633 1634 /* MMC/SD/SDIO3 */ 1635 1636 1637 1638 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = { 1639 { .role = "dbck", .clk = "omap_32k_fck", }, 1640 }; 1641 1642 static struct omap_hwmod omap3xxx_mmc3_hwmod = { 1643 .name = "mmc3", 1644 .opt_clks = omap34xx_mmc3_opt_clks, 1645 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks), 1646 .main_clk = "mmchs3_fck", 1647 .prcm = { 1648 .omap2 = { 1649 .prcm_reg_id = 1, 1650 .module_bit = OMAP3430_EN_MMC3_SHIFT, 1651 .idlest_reg_id = 1, 1652 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT, 1653 }, 1654 }, 1655 .class = &omap34xx_mmc_class, 1656 }; 1657 1658 /* 1659 * 'usb_host_hs' class 1660 * high-speed multi-port usb host controller 1661 */ 1662 1663 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = { 1664 .rev_offs = 0x0000, 1665 .sysc_offs = 0x0010, 1666 .syss_offs = 0x0014, 1667 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | 1668 SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | 1669 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | 1670 SYSS_HAS_RESET_STATUS), 1671 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 1672 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 1673 .sysc_fields = &omap_hwmod_sysc_type1, 1674 }; 1675 1676 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = { 1677 .name = "usb_host_hs", 1678 .sysc = &omap3xxx_usb_host_hs_sysc, 1679 }; 1680 1681 1682 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = { 1683 .name = "usb_host_hs", 1684 .class = &omap3xxx_usb_host_hs_hwmod_class, 1685 .clkdm_name = "usbhost_clkdm", 1686 .main_clk = "usbhost_48m_fck", 1687 .prcm = { 1688 .omap2 = { 1689 .module_offs = OMAP3430ES2_USBHOST_MOD, 1690 .prcm_reg_id = 1, 1691 .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, 1692 .idlest_reg_id = 1, 1693 .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT, 1694 .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT, 1695 }, 1696 }, 1697 1698 /* 1699 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock 1700 * id: i660 1701 * 1702 * Description: 1703 * In the following configuration : 1704 * - USBHOST module is set to smart-idle mode 1705 * - PRCM asserts idle_req to the USBHOST module ( This typically 1706 * happens when the system is going to a low power mode : all ports 1707 * have been suspended, the master part of the USBHOST module has 1708 * entered the standby state, and SW has cut the functional clocks) 1709 * - an USBHOST interrupt occurs before the module is able to answer 1710 * idle_ack, typically a remote wakeup IRQ. 1711 * Then the USB HOST module will enter a deadlock situation where it 1712 * is no more accessible nor functional. 1713 * 1714 * Workaround: 1715 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE 1716 */ 1717 1718 /* 1719 * Errata: USB host EHCI may stall when entering smart-standby mode 1720 * Id: i571 1721 * 1722 * Description: 1723 * When the USBHOST module is set to smart-standby mode, and when it is 1724 * ready to enter the standby state (i.e. all ports are suspended and 1725 * all attached devices are in suspend mode), then it can wrongly assert 1726 * the Mstandby signal too early while there are still some residual OCP 1727 * transactions ongoing. If this condition occurs, the internal state 1728 * machine may go to an undefined state and the USB link may be stuck 1729 * upon the next resume. 1730 * 1731 * Workaround: 1732 * Don't use smart standby; use only force standby, 1733 * hence HWMOD_SWSUP_MSTANDBY 1734 */ 1735 1736 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, 1737 }; 1738 1739 /* 1740 * 'usb_tll_hs' class 1741 * usb_tll_hs module is the adapter on the usb_host_hs ports 1742 */ 1743 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = { 1744 .rev_offs = 0x0000, 1745 .sysc_offs = 0x0010, 1746 .syss_offs = 0x0014, 1747 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1748 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 1749 SYSC_HAS_AUTOIDLE), 1750 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1751 .sysc_fields = &omap_hwmod_sysc_type1, 1752 }; 1753 1754 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = { 1755 .name = "usb_tll_hs", 1756 .sysc = &omap3xxx_usb_tll_hs_sysc, 1757 }; 1758 1759 1760 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { 1761 .name = "usb_tll_hs", 1762 .class = &omap3xxx_usb_tll_hs_hwmod_class, 1763 .clkdm_name = "core_l4_clkdm", 1764 .main_clk = "usbtll_fck", 1765 .prcm = { 1766 .omap2 = { 1767 .module_offs = CORE_MOD, 1768 .prcm_reg_id = 3, 1769 .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT, 1770 .idlest_reg_id = 3, 1771 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT, 1772 }, 1773 }, 1774 }; 1775 1776 static struct omap_hwmod omap3xxx_hdq1w_hwmod = { 1777 .name = "hdq1w", 1778 .main_clk = "hdq_fck", 1779 .prcm = { 1780 .omap2 = { 1781 .module_offs = CORE_MOD, 1782 .prcm_reg_id = 1, 1783 .module_bit = OMAP3430_EN_HDQ_SHIFT, 1784 .idlest_reg_id = 1, 1785 .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT, 1786 }, 1787 }, 1788 .class = &omap2_hdq1w_class, 1789 }; 1790 1791 /* SAD2D */ 1792 static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = { 1793 { .name = "rst_modem_pwron_sw", .rst_shift = 0 }, 1794 { .name = "rst_modem_sw", .rst_shift = 1 }, 1795 }; 1796 1797 static struct omap_hwmod_class omap3xxx_sad2d_class = { 1798 .name = "sad2d", 1799 }; 1800 1801 static struct omap_hwmod omap3xxx_sad2d_hwmod = { 1802 .name = "sad2d", 1803 .rst_lines = omap3xxx_sad2d_resets, 1804 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_sad2d_resets), 1805 .main_clk = "sad2d_ick", 1806 .prcm = { 1807 .omap2 = { 1808 .module_offs = CORE_MOD, 1809 .prcm_reg_id = 1, 1810 .module_bit = OMAP3430_EN_SAD2D_SHIFT, 1811 .idlest_reg_id = 1, 1812 .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT, 1813 }, 1814 }, 1815 .class = &omap3xxx_sad2d_class, 1816 }; 1817 1818 /* 1819 * '32K sync counter' class 1820 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock 1821 */ 1822 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = { 1823 .rev_offs = 0x0000, 1824 .sysc_offs = 0x0004, 1825 .sysc_flags = SYSC_HAS_SIDLEMODE, 1826 .idlemodes = (SIDLE_FORCE | SIDLE_NO), 1827 .sysc_fields = &omap_hwmod_sysc_type1, 1828 }; 1829 1830 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = { 1831 .name = "counter", 1832 .sysc = &omap3xxx_counter_sysc, 1833 }; 1834 1835 static struct omap_hwmod omap3xxx_counter_32k_hwmod = { 1836 .name = "counter_32k", 1837 .class = &omap3xxx_counter_hwmod_class, 1838 .clkdm_name = "wkup_clkdm", 1839 .flags = HWMOD_SWSUP_SIDLE, 1840 .main_clk = "wkup_32k_fck", 1841 .prcm = { 1842 .omap2 = { 1843 .module_offs = WKUP_MOD, 1844 .prcm_reg_id = 1, 1845 .module_bit = OMAP3430_ST_32KSYNC_SHIFT, 1846 .idlest_reg_id = 1, 1847 .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT, 1848 }, 1849 }, 1850 }; 1851 1852 /* 1853 * 'gpmc' class 1854 * general purpose memory controller 1855 */ 1856 1857 static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = { 1858 .rev_offs = 0x0000, 1859 .sysc_offs = 0x0010, 1860 .syss_offs = 0x0014, 1861 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | 1862 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 1863 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1864 .sysc_fields = &omap_hwmod_sysc_type1, 1865 }; 1866 1867 static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = { 1868 .name = "gpmc", 1869 .sysc = &omap3xxx_gpmc_sysc, 1870 }; 1871 1872 static struct omap_hwmod omap3xxx_gpmc_hwmod = { 1873 .name = "gpmc", 1874 .class = &omap3xxx_gpmc_hwmod_class, 1875 .clkdm_name = "core_l3_clkdm", 1876 .main_clk = "gpmc_fck", 1877 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */ 1878 .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS, 1879 }; 1880 1881 /* 1882 * interfaces 1883 */ 1884 1885 /* L3 -> L4_CORE interface */ 1886 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { 1887 .master = &omap3xxx_l3_main_hwmod, 1888 .slave = &omap3xxx_l4_core_hwmod, 1889 .user = OCP_USER_MPU | OCP_USER_SDMA, 1890 }; 1891 1892 /* L3 -> L4_PER interface */ 1893 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { 1894 .master = &omap3xxx_l3_main_hwmod, 1895 .slave = &omap3xxx_l4_per_hwmod, 1896 .user = OCP_USER_MPU | OCP_USER_SDMA, 1897 }; 1898 1899 1900 /* MPU -> L3 interface */ 1901 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { 1902 .master = &omap3xxx_mpu_hwmod, 1903 .slave = &omap3xxx_l3_main_hwmod, 1904 .user = OCP_USER_MPU, 1905 }; 1906 1907 1908 /* l3 -> debugss */ 1909 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = { 1910 .master = &omap3xxx_l3_main_hwmod, 1911 .slave = &omap3xxx_debugss_hwmod, 1912 .user = OCP_USER_MPU, 1913 }; 1914 1915 /* DSS -> l3 */ 1916 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = { 1917 .master = &omap3430es1_dss_core_hwmod, 1918 .slave = &omap3xxx_l3_main_hwmod, 1919 .user = OCP_USER_MPU | OCP_USER_SDMA, 1920 }; 1921 1922 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = { 1923 .master = &omap3xxx_dss_core_hwmod, 1924 .slave = &omap3xxx_l3_main_hwmod, 1925 .fw = { 1926 .omap2 = { 1927 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS, 1928 .flags = OMAP_FIREWALL_L3, 1929 }, 1930 }, 1931 .user = OCP_USER_MPU | OCP_USER_SDMA, 1932 }; 1933 1934 /* l3_core -> usbhsotg interface */ 1935 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { 1936 .master = &omap3xxx_usbhsotg_hwmod, 1937 .slave = &omap3xxx_l3_main_hwmod, 1938 .clk = "core_l3_ick", 1939 .user = OCP_USER_MPU, 1940 }; 1941 1942 /* l3_core -> am35xx_usbhsotg interface */ 1943 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { 1944 .master = &am35xx_usbhsotg_hwmod, 1945 .slave = &omap3xxx_l3_main_hwmod, 1946 .clk = "hsotgusb_ick", 1947 .user = OCP_USER_MPU, 1948 }; 1949 1950 /* l3_core -> sad2d interface */ 1951 static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = { 1952 .master = &omap3xxx_sad2d_hwmod, 1953 .slave = &omap3xxx_l3_main_hwmod, 1954 .clk = "core_l3_ick", 1955 .user = OCP_USER_MPU, 1956 }; 1957 1958 /* L4_CORE -> L4_WKUP interface */ 1959 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { 1960 .master = &omap3xxx_l4_core_hwmod, 1961 .slave = &omap3xxx_l4_wkup_hwmod, 1962 .user = OCP_USER_MPU | OCP_USER_SDMA, 1963 }; 1964 1965 /* L4 CORE -> MMC1 interface */ 1966 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = { 1967 .master = &omap3xxx_l4_core_hwmod, 1968 .slave = &omap3xxx_pre_es3_mmc1_hwmod, 1969 .clk = "mmchs1_ick", 1970 .user = OCP_USER_MPU | OCP_USER_SDMA, 1971 .flags = OMAP_FIREWALL_L4, 1972 }; 1973 1974 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = { 1975 .master = &omap3xxx_l4_core_hwmod, 1976 .slave = &omap3xxx_es3plus_mmc1_hwmod, 1977 .clk = "mmchs1_ick", 1978 .user = OCP_USER_MPU | OCP_USER_SDMA, 1979 .flags = OMAP_FIREWALL_L4, 1980 }; 1981 1982 /* L4 CORE -> MMC2 interface */ 1983 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = { 1984 .master = &omap3xxx_l4_core_hwmod, 1985 .slave = &omap3xxx_pre_es3_mmc2_hwmod, 1986 .clk = "mmchs2_ick", 1987 .user = OCP_USER_MPU | OCP_USER_SDMA, 1988 .flags = OMAP_FIREWALL_L4, 1989 }; 1990 1991 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = { 1992 .master = &omap3xxx_l4_core_hwmod, 1993 .slave = &omap3xxx_es3plus_mmc2_hwmod, 1994 .clk = "mmchs2_ick", 1995 .user = OCP_USER_MPU | OCP_USER_SDMA, 1996 .flags = OMAP_FIREWALL_L4, 1997 }; 1998 1999 /* L4 CORE -> MMC3 interface */ 2000 2001 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { 2002 .master = &omap3xxx_l4_core_hwmod, 2003 .slave = &omap3xxx_mmc3_hwmod, 2004 .clk = "mmchs3_ick", 2005 .user = OCP_USER_MPU | OCP_USER_SDMA, 2006 .flags = OMAP_FIREWALL_L4, 2007 }; 2008 2009 /* L4 CORE -> UART1 interface */ 2010 2011 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { 2012 .master = &omap3xxx_l4_core_hwmod, 2013 .slave = &omap3xxx_uart1_hwmod, 2014 .clk = "uart1_ick", 2015 .user = OCP_USER_MPU | OCP_USER_SDMA, 2016 }; 2017 2018 /* L4 CORE -> UART2 interface */ 2019 2020 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { 2021 .master = &omap3xxx_l4_core_hwmod, 2022 .slave = &omap3xxx_uart2_hwmod, 2023 .clk = "uart2_ick", 2024 .user = OCP_USER_MPU | OCP_USER_SDMA, 2025 }; 2026 2027 /* L4 PER -> UART3 interface */ 2028 2029 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { 2030 .master = &omap3xxx_l4_per_hwmod, 2031 .slave = &omap3xxx_uart3_hwmod, 2032 .clk = "uart3_ick", 2033 .user = OCP_USER_MPU | OCP_USER_SDMA, 2034 }; 2035 2036 /* L4 PER -> UART4 interface */ 2037 2038 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = { 2039 .master = &omap3xxx_l4_per_hwmod, 2040 .slave = &omap36xx_uart4_hwmod, 2041 .clk = "uart4_ick", 2042 .user = OCP_USER_MPU | OCP_USER_SDMA, 2043 }; 2044 2045 /* AM35xx: L4 CORE -> UART4 interface */ 2046 2047 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = { 2048 .master = &omap3xxx_l4_core_hwmod, 2049 .slave = &am35xx_uart4_hwmod, 2050 .clk = "uart4_ick", 2051 .user = OCP_USER_MPU | OCP_USER_SDMA, 2052 }; 2053 2054 /* L4 CORE -> I2C1 interface */ 2055 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { 2056 .master = &omap3xxx_l4_core_hwmod, 2057 .slave = &omap3xxx_i2c1_hwmod, 2058 .clk = "i2c1_ick", 2059 .fw = { 2060 .omap2 = { 2061 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, 2062 .l4_prot_group = 7, 2063 .flags = OMAP_FIREWALL_L4, 2064 }, 2065 }, 2066 .user = OCP_USER_MPU | OCP_USER_SDMA, 2067 }; 2068 2069 /* L4 CORE -> I2C2 interface */ 2070 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { 2071 .master = &omap3xxx_l4_core_hwmod, 2072 .slave = &omap3xxx_i2c2_hwmod, 2073 .clk = "i2c2_ick", 2074 .fw = { 2075 .omap2 = { 2076 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, 2077 .l4_prot_group = 7, 2078 .flags = OMAP_FIREWALL_L4, 2079 }, 2080 }, 2081 .user = OCP_USER_MPU | OCP_USER_SDMA, 2082 }; 2083 2084 /* L4 CORE -> I2C3 interface */ 2085 2086 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { 2087 .master = &omap3xxx_l4_core_hwmod, 2088 .slave = &omap3xxx_i2c3_hwmod, 2089 .clk = "i2c3_ick", 2090 .fw = { 2091 .omap2 = { 2092 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, 2093 .l4_prot_group = 7, 2094 .flags = OMAP_FIREWALL_L4, 2095 }, 2096 }, 2097 .user = OCP_USER_MPU | OCP_USER_SDMA, 2098 }; 2099 2100 /* L4 CORE -> SR1 interface */ 2101 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = { 2102 .master = &omap3xxx_l4_core_hwmod, 2103 .slave = &omap34xx_sr1_hwmod, 2104 .clk = "sr_l4_ick", 2105 .user = OCP_USER_MPU, 2106 }; 2107 2108 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = { 2109 .master = &omap3xxx_l4_core_hwmod, 2110 .slave = &omap36xx_sr1_hwmod, 2111 .clk = "sr_l4_ick", 2112 .user = OCP_USER_MPU, 2113 }; 2114 2115 /* L4 CORE -> SR2 interface */ 2116 2117 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = { 2118 .master = &omap3xxx_l4_core_hwmod, 2119 .slave = &omap34xx_sr2_hwmod, 2120 .clk = "sr_l4_ick", 2121 .user = OCP_USER_MPU, 2122 }; 2123 2124 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = { 2125 .master = &omap3xxx_l4_core_hwmod, 2126 .slave = &omap36xx_sr2_hwmod, 2127 .clk = "sr_l4_ick", 2128 .user = OCP_USER_MPU, 2129 }; 2130 2131 2132 /* l4_core -> usbhsotg */ 2133 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { 2134 .master = &omap3xxx_l4_core_hwmod, 2135 .slave = &omap3xxx_usbhsotg_hwmod, 2136 .clk = "l4_ick", 2137 .user = OCP_USER_MPU, 2138 }; 2139 2140 2141 /* l4_core -> usbhsotg */ 2142 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { 2143 .master = &omap3xxx_l4_core_hwmod, 2144 .slave = &am35xx_usbhsotg_hwmod, 2145 .clk = "hsotgusb_ick", 2146 .user = OCP_USER_MPU, 2147 }; 2148 2149 /* L4_WKUP -> L4_SEC interface */ 2150 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = { 2151 .master = &omap3xxx_l4_wkup_hwmod, 2152 .slave = &omap3xxx_l4_sec_hwmod, 2153 .user = OCP_USER_MPU | OCP_USER_SDMA, 2154 }; 2155 2156 /* IVA2 <- L3 interface */ 2157 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = { 2158 .master = &omap3xxx_l3_main_hwmod, 2159 .slave = &omap3xxx_iva_hwmod, 2160 .clk = "core_l3_ick", 2161 .user = OCP_USER_MPU | OCP_USER_SDMA, 2162 }; 2163 2164 2165 /* l4_wkup -> timer1 */ 2166 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = { 2167 .master = &omap3xxx_l4_wkup_hwmod, 2168 .slave = &omap3xxx_timer1_hwmod, 2169 .clk = "gpt1_ick", 2170 .user = OCP_USER_MPU | OCP_USER_SDMA, 2171 }; 2172 2173 2174 /* l4_per -> timer2 */ 2175 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = { 2176 .master = &omap3xxx_l4_per_hwmod, 2177 .slave = &omap3xxx_timer2_hwmod, 2178 .clk = "gpt2_ick", 2179 .user = OCP_USER_MPU | OCP_USER_SDMA, 2180 }; 2181 2182 2183 /* l4_per -> timer3 */ 2184 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = { 2185 .master = &omap3xxx_l4_per_hwmod, 2186 .slave = &omap3xxx_timer3_hwmod, 2187 .clk = "gpt3_ick", 2188 .user = OCP_USER_MPU | OCP_USER_SDMA, 2189 }; 2190 2191 2192 /* l4_per -> timer4 */ 2193 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = { 2194 .master = &omap3xxx_l4_per_hwmod, 2195 .slave = &omap3xxx_timer4_hwmod, 2196 .clk = "gpt4_ick", 2197 .user = OCP_USER_MPU | OCP_USER_SDMA, 2198 }; 2199 2200 2201 /* l4_per -> timer5 */ 2202 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = { 2203 .master = &omap3xxx_l4_per_hwmod, 2204 .slave = &omap3xxx_timer5_hwmod, 2205 .clk = "gpt5_ick", 2206 .user = OCP_USER_MPU | OCP_USER_SDMA, 2207 }; 2208 2209 2210 /* l4_per -> timer6 */ 2211 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = { 2212 .master = &omap3xxx_l4_per_hwmod, 2213 .slave = &omap3xxx_timer6_hwmod, 2214 .clk = "gpt6_ick", 2215 .user = OCP_USER_MPU | OCP_USER_SDMA, 2216 }; 2217 2218 2219 /* l4_per -> timer7 */ 2220 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = { 2221 .master = &omap3xxx_l4_per_hwmod, 2222 .slave = &omap3xxx_timer7_hwmod, 2223 .clk = "gpt7_ick", 2224 .user = OCP_USER_MPU | OCP_USER_SDMA, 2225 }; 2226 2227 2228 /* l4_per -> timer8 */ 2229 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = { 2230 .master = &omap3xxx_l4_per_hwmod, 2231 .slave = &omap3xxx_timer8_hwmod, 2232 .clk = "gpt8_ick", 2233 .user = OCP_USER_MPU | OCP_USER_SDMA, 2234 }; 2235 2236 2237 /* l4_per -> timer9 */ 2238 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = { 2239 .master = &omap3xxx_l4_per_hwmod, 2240 .slave = &omap3xxx_timer9_hwmod, 2241 .clk = "gpt9_ick", 2242 .user = OCP_USER_MPU | OCP_USER_SDMA, 2243 }; 2244 2245 /* l4_core -> timer10 */ 2246 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = { 2247 .master = &omap3xxx_l4_core_hwmod, 2248 .slave = &omap3xxx_timer10_hwmod, 2249 .clk = "gpt10_ick", 2250 .user = OCP_USER_MPU | OCP_USER_SDMA, 2251 }; 2252 2253 /* l4_core -> timer11 */ 2254 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { 2255 .master = &omap3xxx_l4_core_hwmod, 2256 .slave = &omap3xxx_timer11_hwmod, 2257 .clk = "gpt11_ick", 2258 .user = OCP_USER_MPU | OCP_USER_SDMA, 2259 }; 2260 2261 2262 /* l4_core -> timer12 */ 2263 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = { 2264 .master = &omap3xxx_l4_sec_hwmod, 2265 .slave = &omap3xxx_timer12_hwmod, 2266 .clk = "gpt12_ick", 2267 .user = OCP_USER_MPU | OCP_USER_SDMA, 2268 }; 2269 2270 /* l4_wkup -> wd_timer2 */ 2271 2272 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { 2273 .master = &omap3xxx_l4_wkup_hwmod, 2274 .slave = &omap3xxx_wd_timer2_hwmod, 2275 .clk = "wdt2_ick", 2276 .user = OCP_USER_MPU | OCP_USER_SDMA, 2277 }; 2278 2279 /* l4_core -> dss */ 2280 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { 2281 .master = &omap3xxx_l4_core_hwmod, 2282 .slave = &omap3430es1_dss_core_hwmod, 2283 .clk = "dss_ick", 2284 .fw = { 2285 .omap2 = { 2286 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, 2287 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 2288 .flags = OMAP_FIREWALL_L4, 2289 }, 2290 }, 2291 .user = OCP_USER_MPU | OCP_USER_SDMA, 2292 }; 2293 2294 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = { 2295 .master = &omap3xxx_l4_core_hwmod, 2296 .slave = &omap3xxx_dss_core_hwmod, 2297 .clk = "dss_ick", 2298 .fw = { 2299 .omap2 = { 2300 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, 2301 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 2302 .flags = OMAP_FIREWALL_L4, 2303 }, 2304 }, 2305 .user = OCP_USER_MPU | OCP_USER_SDMA, 2306 }; 2307 2308 /* l4_core -> dss_dispc */ 2309 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { 2310 .master = &omap3xxx_l4_core_hwmod, 2311 .slave = &omap3xxx_dss_dispc_hwmod, 2312 .clk = "dss_ick", 2313 .fw = { 2314 .omap2 = { 2315 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, 2316 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 2317 .flags = OMAP_FIREWALL_L4, 2318 }, 2319 }, 2320 .user = OCP_USER_MPU | OCP_USER_SDMA, 2321 }; 2322 2323 /* l4_core -> dss_dsi1 */ 2324 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { 2325 .master = &omap3xxx_l4_core_hwmod, 2326 .slave = &omap3xxx_dss_dsi1_hwmod, 2327 .clk = "dss_ick", 2328 .fw = { 2329 .omap2 = { 2330 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, 2331 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 2332 .flags = OMAP_FIREWALL_L4, 2333 }, 2334 }, 2335 .user = OCP_USER_MPU | OCP_USER_SDMA, 2336 }; 2337 2338 /* l4_core -> dss_rfbi */ 2339 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { 2340 .master = &omap3xxx_l4_core_hwmod, 2341 .slave = &omap3xxx_dss_rfbi_hwmod, 2342 .clk = "dss_ick", 2343 .fw = { 2344 .omap2 = { 2345 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, 2346 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP , 2347 .flags = OMAP_FIREWALL_L4, 2348 }, 2349 }, 2350 .user = OCP_USER_MPU | OCP_USER_SDMA, 2351 }; 2352 2353 /* l4_core -> dss_venc */ 2354 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { 2355 .master = &omap3xxx_l4_core_hwmod, 2356 .slave = &omap3xxx_dss_venc_hwmod, 2357 .clk = "dss_ick", 2358 .fw = { 2359 .omap2 = { 2360 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, 2361 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 2362 .flags = OMAP_FIREWALL_L4, 2363 }, 2364 }, 2365 .flags = OCPIF_SWSUP_IDLE, 2366 .user = OCP_USER_MPU | OCP_USER_SDMA, 2367 }; 2368 2369 /* l4_wkup -> gpio1 */ 2370 2371 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { 2372 .master = &omap3xxx_l4_wkup_hwmod, 2373 .slave = &omap3xxx_gpio1_hwmod, 2374 .user = OCP_USER_MPU | OCP_USER_SDMA, 2375 }; 2376 2377 /* l4_per -> gpio2 */ 2378 2379 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { 2380 .master = &omap3xxx_l4_per_hwmod, 2381 .slave = &omap3xxx_gpio2_hwmod, 2382 .user = OCP_USER_MPU | OCP_USER_SDMA, 2383 }; 2384 2385 /* l4_per -> gpio3 */ 2386 2387 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { 2388 .master = &omap3xxx_l4_per_hwmod, 2389 .slave = &omap3xxx_gpio3_hwmod, 2390 .user = OCP_USER_MPU | OCP_USER_SDMA, 2391 }; 2392 2393 /* 2394 * 'mmu' class 2395 * The memory management unit performs virtual to physical address translation 2396 * for its requestors. 2397 */ 2398 2399 static struct omap_hwmod_class_sysconfig mmu_sysc = { 2400 .rev_offs = 0x000, 2401 .sysc_offs = 0x010, 2402 .syss_offs = 0x014, 2403 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 2404 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), 2405 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 2406 .sysc_fields = &omap_hwmod_sysc_type1, 2407 }; 2408 2409 static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = { 2410 .name = "mmu", 2411 .sysc = &mmu_sysc, 2412 }; 2413 2414 /* mmu isp */ 2415 static struct omap_hwmod omap3xxx_mmu_isp_hwmod; 2416 2417 /* l4_core -> mmu isp */ 2418 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = { 2419 .master = &omap3xxx_l4_core_hwmod, 2420 .slave = &omap3xxx_mmu_isp_hwmod, 2421 .user = OCP_USER_MPU | OCP_USER_SDMA, 2422 }; 2423 2424 static struct omap_hwmod omap3xxx_mmu_isp_hwmod = { 2425 .name = "mmu_isp", 2426 .class = &omap3xxx_mmu_hwmod_class, 2427 .main_clk = "cam_ick", 2428 .flags = HWMOD_NO_IDLEST, 2429 }; 2430 2431 /* mmu iva */ 2432 2433 static struct omap_hwmod omap3xxx_mmu_iva_hwmod; 2434 2435 static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = { 2436 { .name = "mmu", .rst_shift = 1, .st_shift = 9 }, 2437 }; 2438 2439 /* l3_main -> iva mmu */ 2440 static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = { 2441 .master = &omap3xxx_l3_main_hwmod, 2442 .slave = &omap3xxx_mmu_iva_hwmod, 2443 .user = OCP_USER_MPU | OCP_USER_SDMA, 2444 }; 2445 2446 static struct omap_hwmod omap3xxx_mmu_iva_hwmod = { 2447 .name = "mmu_iva", 2448 .class = &omap3xxx_mmu_hwmod_class, 2449 .clkdm_name = "iva2_clkdm", 2450 .rst_lines = omap3xxx_mmu_iva_resets, 2451 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_mmu_iva_resets), 2452 .main_clk = "iva2_ck", 2453 .prcm = { 2454 .omap2 = { 2455 .module_offs = OMAP3430_IVA2_MOD, 2456 .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, 2457 .idlest_reg_id = 1, 2458 .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT, 2459 }, 2460 }, 2461 .flags = HWMOD_NO_IDLEST, 2462 }; 2463 2464 /* l4_per -> gpio4 */ 2465 2466 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { 2467 .master = &omap3xxx_l4_per_hwmod, 2468 .slave = &omap3xxx_gpio4_hwmod, 2469 .user = OCP_USER_MPU | OCP_USER_SDMA, 2470 }; 2471 2472 /* l4_per -> gpio5 */ 2473 2474 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { 2475 .master = &omap3xxx_l4_per_hwmod, 2476 .slave = &omap3xxx_gpio5_hwmod, 2477 .user = OCP_USER_MPU | OCP_USER_SDMA, 2478 }; 2479 2480 /* l4_per -> gpio6 */ 2481 2482 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { 2483 .master = &omap3xxx_l4_per_hwmod, 2484 .slave = &omap3xxx_gpio6_hwmod, 2485 .user = OCP_USER_MPU | OCP_USER_SDMA, 2486 }; 2487 2488 /* dma_system -> L3 */ 2489 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = { 2490 .master = &omap3xxx_dma_system_hwmod, 2491 .slave = &omap3xxx_l3_main_hwmod, 2492 .clk = "core_l3_ick", 2493 .user = OCP_USER_MPU | OCP_USER_SDMA, 2494 }; 2495 2496 /* l4_cfg -> dma_system */ 2497 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = { 2498 .master = &omap3xxx_l4_core_hwmod, 2499 .slave = &omap3xxx_dma_system_hwmod, 2500 .clk = "core_l4_ick", 2501 .user = OCP_USER_MPU | OCP_USER_SDMA, 2502 }; 2503 2504 2505 /* l4_core -> mcbsp1 */ 2506 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = { 2507 .master = &omap3xxx_l4_core_hwmod, 2508 .slave = &omap3xxx_mcbsp1_hwmod, 2509 .clk = "mcbsp1_ick", 2510 .user = OCP_USER_MPU | OCP_USER_SDMA, 2511 }; 2512 2513 2514 /* l4_per -> mcbsp2 */ 2515 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = { 2516 .master = &omap3xxx_l4_per_hwmod, 2517 .slave = &omap3xxx_mcbsp2_hwmod, 2518 .clk = "mcbsp2_ick", 2519 .user = OCP_USER_MPU | OCP_USER_SDMA, 2520 }; 2521 2522 2523 /* l4_per -> mcbsp3 */ 2524 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = { 2525 .master = &omap3xxx_l4_per_hwmod, 2526 .slave = &omap3xxx_mcbsp3_hwmod, 2527 .clk = "mcbsp3_ick", 2528 .user = OCP_USER_MPU | OCP_USER_SDMA, 2529 }; 2530 2531 2532 /* l4_per -> mcbsp4 */ 2533 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = { 2534 .master = &omap3xxx_l4_per_hwmod, 2535 .slave = &omap3xxx_mcbsp4_hwmod, 2536 .clk = "mcbsp4_ick", 2537 .user = OCP_USER_MPU | OCP_USER_SDMA, 2538 }; 2539 2540 2541 /* l4_core -> mcbsp5 */ 2542 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = { 2543 .master = &omap3xxx_l4_core_hwmod, 2544 .slave = &omap3xxx_mcbsp5_hwmod, 2545 .clk = "mcbsp5_ick", 2546 .user = OCP_USER_MPU | OCP_USER_SDMA, 2547 }; 2548 2549 2550 /* l4_per -> mcbsp2_sidetone */ 2551 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = { 2552 .master = &omap3xxx_l4_per_hwmod, 2553 .slave = &omap3xxx_mcbsp2_sidetone_hwmod, 2554 .clk = "mcbsp2_ick", 2555 .user = OCP_USER_MPU, 2556 }; 2557 2558 2559 /* l4_per -> mcbsp3_sidetone */ 2560 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = { 2561 .master = &omap3xxx_l4_per_hwmod, 2562 .slave = &omap3xxx_mcbsp3_sidetone_hwmod, 2563 .clk = "mcbsp3_ick", 2564 .user = OCP_USER_MPU, 2565 }; 2566 2567 /* l4_core -> mailbox */ 2568 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = { 2569 .master = &omap3xxx_l4_core_hwmod, 2570 .slave = &omap3xxx_mailbox_hwmod, 2571 .user = OCP_USER_MPU | OCP_USER_SDMA, 2572 }; 2573 2574 /* l4 core -> mcspi1 interface */ 2575 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { 2576 .master = &omap3xxx_l4_core_hwmod, 2577 .slave = &omap34xx_mcspi1, 2578 .clk = "mcspi1_ick", 2579 .user = OCP_USER_MPU | OCP_USER_SDMA, 2580 }; 2581 2582 /* l4 core -> mcspi2 interface */ 2583 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { 2584 .master = &omap3xxx_l4_core_hwmod, 2585 .slave = &omap34xx_mcspi2, 2586 .clk = "mcspi2_ick", 2587 .user = OCP_USER_MPU | OCP_USER_SDMA, 2588 }; 2589 2590 /* l4 core -> mcspi3 interface */ 2591 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { 2592 .master = &omap3xxx_l4_core_hwmod, 2593 .slave = &omap34xx_mcspi3, 2594 .clk = "mcspi3_ick", 2595 .user = OCP_USER_MPU | OCP_USER_SDMA, 2596 }; 2597 2598 /* l4 core -> mcspi4 interface */ 2599 2600 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { 2601 .master = &omap3xxx_l4_core_hwmod, 2602 .slave = &omap34xx_mcspi4, 2603 .clk = "mcspi4_ick", 2604 .user = OCP_USER_MPU | OCP_USER_SDMA, 2605 }; 2606 2607 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = { 2608 .master = &omap3xxx_usb_host_hs_hwmod, 2609 .slave = &omap3xxx_l3_main_hwmod, 2610 .clk = "core_l3_ick", 2611 .user = OCP_USER_MPU, 2612 }; 2613 2614 2615 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = { 2616 .master = &omap3xxx_l4_core_hwmod, 2617 .slave = &omap3xxx_usb_host_hs_hwmod, 2618 .clk = "usbhost_ick", 2619 .user = OCP_USER_MPU | OCP_USER_SDMA, 2620 }; 2621 2622 2623 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = { 2624 .master = &omap3xxx_l4_core_hwmod, 2625 .slave = &omap3xxx_usb_tll_hs_hwmod, 2626 .clk = "usbtll_ick", 2627 .user = OCP_USER_MPU | OCP_USER_SDMA, 2628 }; 2629 2630 /* l4_core -> hdq1w interface */ 2631 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = { 2632 .master = &omap3xxx_l4_core_hwmod, 2633 .slave = &omap3xxx_hdq1w_hwmod, 2634 .clk = "hdq_ick", 2635 .user = OCP_USER_MPU | OCP_USER_SDMA, 2636 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, 2637 }; 2638 2639 /* l4_wkup -> 32ksync_counter */ 2640 2641 2642 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = { 2643 .master = &omap3xxx_l4_wkup_hwmod, 2644 .slave = &omap3xxx_counter_32k_hwmod, 2645 .clk = "omap_32ksync_ick", 2646 .user = OCP_USER_MPU | OCP_USER_SDMA, 2647 }; 2648 2649 /* am35xx has Davinci MDIO & EMAC */ 2650 static struct omap_hwmod_class am35xx_mdio_class = { 2651 .name = "davinci_mdio", 2652 }; 2653 2654 static struct omap_hwmod am35xx_mdio_hwmod = { 2655 .name = "davinci_mdio", 2656 .class = &am35xx_mdio_class, 2657 .flags = HWMOD_NO_IDLEST, 2658 }; 2659 2660 /* 2661 * XXX Should be connected to an IPSS hwmod, not the L3 directly; 2662 * but this will probably require some additional hwmod core support, 2663 * so is left as a future to-do item. 2664 */ 2665 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = { 2666 .master = &am35xx_mdio_hwmod, 2667 .slave = &omap3xxx_l3_main_hwmod, 2668 .clk = "emac_fck", 2669 .user = OCP_USER_MPU, 2670 }; 2671 2672 /* l4_core -> davinci mdio */ 2673 /* 2674 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly; 2675 * but this will probably require some additional hwmod core support, 2676 * so is left as a future to-do item. 2677 */ 2678 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = { 2679 .master = &omap3xxx_l4_core_hwmod, 2680 .slave = &am35xx_mdio_hwmod, 2681 .clk = "emac_fck", 2682 .user = OCP_USER_MPU, 2683 }; 2684 2685 static struct omap_hwmod_class am35xx_emac_class = { 2686 .name = "davinci_emac", 2687 }; 2688 2689 static struct omap_hwmod am35xx_emac_hwmod = { 2690 .name = "davinci_emac", 2691 .class = &am35xx_emac_class, 2692 /* 2693 * According to Mark Greer, the MPU will not return from WFI 2694 * when the EMAC signals an interrupt. 2695 * http://www.spinics.net/lists/arm-kernel/msg174734.html 2696 */ 2697 .flags = (HWMOD_NO_IDLEST | HWMOD_BLOCK_WFI), 2698 }; 2699 2700 /* l3_core -> davinci emac interface */ 2701 /* 2702 * XXX Should be connected to an IPSS hwmod, not the L3 directly; 2703 * but this will probably require some additional hwmod core support, 2704 * so is left as a future to-do item. 2705 */ 2706 static struct omap_hwmod_ocp_if am35xx_emac__l3 = { 2707 .master = &am35xx_emac_hwmod, 2708 .slave = &omap3xxx_l3_main_hwmod, 2709 .clk = "emac_ick", 2710 .user = OCP_USER_MPU, 2711 }; 2712 2713 /* l4_core -> davinci emac */ 2714 /* 2715 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly; 2716 * but this will probably require some additional hwmod core support, 2717 * so is left as a future to-do item. 2718 */ 2719 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = { 2720 .master = &omap3xxx_l4_core_hwmod, 2721 .slave = &am35xx_emac_hwmod, 2722 .clk = "emac_ick", 2723 .user = OCP_USER_MPU, 2724 }; 2725 2726 static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = { 2727 .master = &omap3xxx_l3_main_hwmod, 2728 .slave = &omap3xxx_gpmc_hwmod, 2729 .clk = "core_l3_ick", 2730 .user = OCP_USER_MPU | OCP_USER_SDMA, 2731 }; 2732 2733 /* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */ 2734 static struct omap_hwmod_sysc_fields omap3_sham_sysc_fields = { 2735 .sidle_shift = 4, 2736 .srst_shift = 1, 2737 .autoidle_shift = 0, 2738 }; 2739 2740 static struct omap_hwmod_class_sysconfig omap3_sham_sysc = { 2741 .rev_offs = 0x5c, 2742 .sysc_offs = 0x60, 2743 .syss_offs = 0x64, 2744 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 2745 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 2746 .sysc_fields = &omap3_sham_sysc_fields, 2747 }; 2748 2749 static struct omap_hwmod_class omap3xxx_sham_class = { 2750 .name = "sham", 2751 .sysc = &omap3_sham_sysc, 2752 }; 2753 2754 2755 2756 static struct omap_hwmod omap3xxx_sham_hwmod = { 2757 .name = "sham", 2758 .main_clk = "sha12_ick", 2759 .prcm = { 2760 .omap2 = { 2761 .module_offs = CORE_MOD, 2762 .prcm_reg_id = 1, 2763 .module_bit = OMAP3430_EN_SHA12_SHIFT, 2764 .idlest_reg_id = 1, 2765 .idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT, 2766 }, 2767 }, 2768 .class = &omap3xxx_sham_class, 2769 }; 2770 2771 2772 static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = { 2773 .master = &omap3xxx_l4_core_hwmod, 2774 .slave = &omap3xxx_sham_hwmod, 2775 .clk = "sha12_ick", 2776 .user = OCP_USER_MPU | OCP_USER_SDMA, 2777 }; 2778 2779 /* l4_core -> AES */ 2780 static struct omap_hwmod_sysc_fields omap3xxx_aes_sysc_fields = { 2781 .sidle_shift = 6, 2782 .srst_shift = 1, 2783 .autoidle_shift = 0, 2784 }; 2785 2786 static struct omap_hwmod_class_sysconfig omap3_aes_sysc = { 2787 .rev_offs = 0x44, 2788 .sysc_offs = 0x48, 2789 .syss_offs = 0x4c, 2790 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 2791 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 2792 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 2793 .sysc_fields = &omap3xxx_aes_sysc_fields, 2794 }; 2795 2796 static struct omap_hwmod_class omap3xxx_aes_class = { 2797 .name = "aes", 2798 .sysc = &omap3_aes_sysc, 2799 }; 2800 2801 2802 static struct omap_hwmod omap3xxx_aes_hwmod = { 2803 .name = "aes", 2804 .main_clk = "aes2_ick", 2805 .prcm = { 2806 .omap2 = { 2807 .module_offs = CORE_MOD, 2808 .prcm_reg_id = 1, 2809 .module_bit = OMAP3430_EN_AES2_SHIFT, 2810 .idlest_reg_id = 1, 2811 .idlest_idle_bit = OMAP3430_ST_AES2_SHIFT, 2812 }, 2813 }, 2814 .class = &omap3xxx_aes_class, 2815 }; 2816 2817 2818 static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = { 2819 .master = &omap3xxx_l4_core_hwmod, 2820 .slave = &omap3xxx_aes_hwmod, 2821 .clk = "aes2_ick", 2822 .user = OCP_USER_MPU | OCP_USER_SDMA, 2823 }; 2824 2825 /* 2826 * 'ssi' class 2827 * synchronous serial interface (multichannel and full-duplex serial if) 2828 */ 2829 2830 static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = { 2831 .rev_offs = 0x0000, 2832 .sysc_offs = 0x0010, 2833 .syss_offs = 0x0014, 2834 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_MIDLEMODE | 2835 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), 2836 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 2837 .sysc_fields = &omap_hwmod_sysc_type1, 2838 }; 2839 2840 static struct omap_hwmod_class omap3xxx_ssi_hwmod_class = { 2841 .name = "ssi", 2842 .sysc = &omap34xx_ssi_sysc, 2843 }; 2844 2845 static struct omap_hwmod omap3xxx_ssi_hwmod = { 2846 .name = "ssi", 2847 .class = &omap3xxx_ssi_hwmod_class, 2848 .clkdm_name = "core_l4_clkdm", 2849 .main_clk = "ssi_ssr_fck", 2850 .prcm = { 2851 .omap2 = { 2852 .prcm_reg_id = 1, 2853 .module_bit = OMAP3430_EN_SSI_SHIFT, 2854 .module_offs = CORE_MOD, 2855 .idlest_reg_id = 1, 2856 .idlest_idle_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT, 2857 }, 2858 }, 2859 }; 2860 2861 /* L4 CORE -> SSI */ 2862 static struct omap_hwmod_ocp_if omap3xxx_l4_core__ssi = { 2863 .master = &omap3xxx_l4_core_hwmod, 2864 .slave = &omap3xxx_ssi_hwmod, 2865 .clk = "ssi_ick", 2866 .user = OCP_USER_MPU | OCP_USER_SDMA, 2867 }; 2868 2869 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { 2870 &omap3xxx_l3_main__l4_core, 2871 &omap3xxx_l3_main__l4_per, 2872 &omap3xxx_mpu__l3_main, 2873 &omap3xxx_l3_main__l4_debugss, 2874 &omap3xxx_l4_core__l4_wkup, 2875 &omap3xxx_l4_core__mmc3, 2876 &omap3_l4_core__uart1, 2877 &omap3_l4_core__uart2, 2878 &omap3_l4_per__uart3, 2879 &omap3_l4_core__i2c1, 2880 &omap3_l4_core__i2c2, 2881 &omap3_l4_core__i2c3, 2882 &omap3xxx_l4_wkup__l4_sec, 2883 &omap3xxx_l4_wkup__timer1, 2884 &omap3xxx_l4_per__timer2, 2885 &omap3xxx_l4_per__timer3, 2886 &omap3xxx_l4_per__timer4, 2887 &omap3xxx_l4_per__timer5, 2888 &omap3xxx_l4_per__timer6, 2889 &omap3xxx_l4_per__timer7, 2890 &omap3xxx_l4_per__timer8, 2891 &omap3xxx_l4_per__timer9, 2892 &omap3xxx_l4_core__timer10, 2893 &omap3xxx_l4_core__timer11, 2894 &omap3xxx_l4_wkup__wd_timer2, 2895 &omap3xxx_l4_wkup__gpio1, 2896 &omap3xxx_l4_per__gpio2, 2897 &omap3xxx_l4_per__gpio3, 2898 &omap3xxx_l4_per__gpio4, 2899 &omap3xxx_l4_per__gpio5, 2900 &omap3xxx_l4_per__gpio6, 2901 &omap3xxx_dma_system__l3, 2902 &omap3xxx_l4_core__dma_system, 2903 &omap3xxx_l4_core__mcbsp1, 2904 &omap3xxx_l4_per__mcbsp2, 2905 &omap3xxx_l4_per__mcbsp3, 2906 &omap3xxx_l4_per__mcbsp4, 2907 &omap3xxx_l4_core__mcbsp5, 2908 &omap3xxx_l4_per__mcbsp2_sidetone, 2909 &omap3xxx_l4_per__mcbsp3_sidetone, 2910 &omap34xx_l4_core__mcspi1, 2911 &omap34xx_l4_core__mcspi2, 2912 &omap34xx_l4_core__mcspi3, 2913 &omap34xx_l4_core__mcspi4, 2914 &omap3xxx_l4_wkup__counter_32k, 2915 &omap3xxx_l3_main__gpmc, 2916 NULL, 2917 }; 2918 2919 /* GP-only hwmod links */ 2920 static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = { 2921 &omap3xxx_l4_sec__timer12, 2922 NULL, 2923 }; 2924 2925 static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = { 2926 &omap3xxx_l4_sec__timer12, 2927 NULL, 2928 }; 2929 2930 static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = { 2931 &omap3xxx_l4_sec__timer12, 2932 NULL, 2933 }; 2934 2935 /* crypto hwmod links */ 2936 static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = { 2937 &omap3xxx_l4_core__sham, 2938 NULL, 2939 }; 2940 2941 static struct omap_hwmod_ocp_if *omap34xx_aes_hwmod_ocp_ifs[] __initdata = { 2942 &omap3xxx_l4_core__aes, 2943 NULL, 2944 }; 2945 2946 static struct omap_hwmod_ocp_if *omap36xx_sham_hwmod_ocp_ifs[] __initdata = { 2947 &omap3xxx_l4_core__sham, 2948 NULL 2949 }; 2950 2951 static struct omap_hwmod_ocp_if *omap36xx_aes_hwmod_ocp_ifs[] __initdata = { 2952 &omap3xxx_l4_core__aes, 2953 NULL 2954 }; 2955 2956 /* 2957 * Apparently the SHA/MD5 and AES accelerator IP blocks are 2958 * only present on some AM35xx chips, and no one knows which 2959 * ones. See 2960 * http://www.spinics.net/lists/arm-kernel/msg215466.html So 2961 * if you need these IP blocks on an AM35xx, try uncommenting 2962 * the following lines. 2963 */ 2964 static struct omap_hwmod_ocp_if *am35xx_sham_hwmod_ocp_ifs[] __initdata = { 2965 /* &omap3xxx_l4_core__sham, */ 2966 NULL 2967 }; 2968 2969 static struct omap_hwmod_ocp_if *am35xx_aes_hwmod_ocp_ifs[] __initdata = { 2970 /* &omap3xxx_l4_core__aes, */ 2971 NULL, 2972 }; 2973 2974 /* 3430ES1-only hwmod links */ 2975 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = { 2976 &omap3430es1_dss__l3, 2977 &omap3430es1_l4_core__dss, 2978 NULL, 2979 }; 2980 2981 /* 3430ES2+-only hwmod links */ 2982 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = { 2983 &omap3xxx_dss__l3, 2984 &omap3xxx_l4_core__dss, 2985 &omap3xxx_usbhsotg__l3, 2986 &omap3xxx_l4_core__usbhsotg, 2987 &omap3xxx_usb_host_hs__l3_main_2, 2988 &omap3xxx_l4_core__usb_host_hs, 2989 &omap3xxx_l4_core__usb_tll_hs, 2990 NULL, 2991 }; 2992 2993 /* <= 3430ES3-only hwmod links */ 2994 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = { 2995 &omap3xxx_l4_core__pre_es3_mmc1, 2996 &omap3xxx_l4_core__pre_es3_mmc2, 2997 NULL, 2998 }; 2999 3000 /* 3430ES3+-only hwmod links */ 3001 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = { 3002 &omap3xxx_l4_core__es3plus_mmc1, 3003 &omap3xxx_l4_core__es3plus_mmc2, 3004 NULL, 3005 }; 3006 3007 /* 34xx-only hwmod links (all ES revisions) */ 3008 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = { 3009 &omap3xxx_l3__iva, 3010 &omap34xx_l4_core__sr1, 3011 &omap34xx_l4_core__sr2, 3012 &omap3xxx_l4_core__mailbox, 3013 &omap3xxx_l4_core__hdq1w, 3014 &omap3xxx_sad2d__l3, 3015 &omap3xxx_l4_core__mmu_isp, 3016 &omap3xxx_l3_main__mmu_iva, 3017 &omap3xxx_l4_core__ssi, 3018 NULL, 3019 }; 3020 3021 /* 36xx-only hwmod links (all ES revisions) */ 3022 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = { 3023 &omap3xxx_l3__iva, 3024 &omap36xx_l4_per__uart4, 3025 &omap3xxx_dss__l3, 3026 &omap3xxx_l4_core__dss, 3027 &omap36xx_l4_core__sr1, 3028 &omap36xx_l4_core__sr2, 3029 &omap3xxx_usbhsotg__l3, 3030 &omap3xxx_l4_core__usbhsotg, 3031 &omap3xxx_l4_core__mailbox, 3032 &omap3xxx_usb_host_hs__l3_main_2, 3033 &omap3xxx_l4_core__usb_host_hs, 3034 &omap3xxx_l4_core__usb_tll_hs, 3035 &omap3xxx_l4_core__es3plus_mmc1, 3036 &omap3xxx_l4_core__es3plus_mmc2, 3037 &omap3xxx_l4_core__hdq1w, 3038 &omap3xxx_sad2d__l3, 3039 &omap3xxx_l4_core__mmu_isp, 3040 &omap3xxx_l3_main__mmu_iva, 3041 &omap3xxx_l4_core__ssi, 3042 NULL, 3043 }; 3044 3045 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = { 3046 &omap3xxx_dss__l3, 3047 &omap3xxx_l4_core__dss, 3048 &am35xx_usbhsotg__l3, 3049 &am35xx_l4_core__usbhsotg, 3050 &am35xx_l4_core__uart4, 3051 &omap3xxx_usb_host_hs__l3_main_2, 3052 &omap3xxx_l4_core__usb_host_hs, 3053 &omap3xxx_l4_core__usb_tll_hs, 3054 &omap3xxx_l4_core__es3plus_mmc1, 3055 &omap3xxx_l4_core__es3plus_mmc2, 3056 &omap3xxx_l4_core__hdq1w, 3057 &am35xx_mdio__l3, 3058 &am35xx_l4_core__mdio, 3059 &am35xx_emac__l3, 3060 &am35xx_l4_core__emac, 3061 NULL, 3062 }; 3063 3064 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = { 3065 &omap3xxx_l4_core__dss_dispc, 3066 &omap3xxx_l4_core__dss_dsi1, 3067 &omap3xxx_l4_core__dss_rfbi, 3068 &omap3xxx_l4_core__dss_venc, 3069 NULL, 3070 }; 3071 3072 /** 3073 * omap3xxx_hwmod_is_hs_ip_block_usable - is a security IP block accessible? 3074 * @bus: struct device_node * for the top-level OMAP DT data 3075 * @dev_name: device name used in the DT file 3076 * 3077 * Determine whether a "secure" IP block @dev_name is usable by Linux. 3078 * There doesn't appear to be a 100% reliable way to determine this, 3079 * so we rely on heuristics. If @bus is null, meaning there's no DT 3080 * data, then we only assume the IP block is accessible if the OMAP is 3081 * fused as a 'general-purpose' SoC. If however DT data is present, 3082 * test to see if the IP block is described in the DT data and set to 3083 * 'status = "okay"'. If so then we assume the ODM has configured the 3084 * OMAP firewalls to allow access to the IP block. 3085 * 3086 * Return: 0 if device named @dev_name is not likely to be accessible, 3087 * or 1 if it is likely to be accessible. 3088 */ 3089 static bool __init omap3xxx_hwmod_is_hs_ip_block_usable(struct device_node *bus, 3090 const char *dev_name) 3091 { 3092 struct device_node *node; 3093 bool available; 3094 3095 if (!bus) 3096 return omap_type() == OMAP2_DEVICE_TYPE_GP; 3097 3098 node = of_get_child_by_name(bus, dev_name); 3099 available = of_device_is_available(node); 3100 of_node_put(node); 3101 3102 return available; 3103 } 3104 3105 int __init omap3xxx_hwmod_init(void) 3106 { 3107 int r; 3108 struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL, **h_sham = NULL; 3109 struct omap_hwmod_ocp_if **h_aes = NULL; 3110 struct device_node *bus; 3111 unsigned int rev; 3112 3113 omap_hwmod_init(); 3114 3115 /* Register hwmod links common to all OMAP3 */ 3116 r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs); 3117 if (r < 0) 3118 return r; 3119 3120 rev = omap_rev(); 3121 3122 /* 3123 * Register hwmod links common to individual OMAP3 families, all 3124 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx) 3125 * All possible revisions should be included in this conditional. 3126 */ 3127 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || 3128 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 || 3129 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { 3130 h = omap34xx_hwmod_ocp_ifs; 3131 h_gp = omap34xx_gp_hwmod_ocp_ifs; 3132 h_sham = omap34xx_sham_hwmod_ocp_ifs; 3133 h_aes = omap34xx_aes_hwmod_ocp_ifs; 3134 } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) { 3135 h = am35xx_hwmod_ocp_ifs; 3136 h_gp = am35xx_gp_hwmod_ocp_ifs; 3137 h_sham = am35xx_sham_hwmod_ocp_ifs; 3138 h_aes = am35xx_aes_hwmod_ocp_ifs; 3139 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 || 3140 rev == OMAP3630_REV_ES1_2) { 3141 h = omap36xx_hwmod_ocp_ifs; 3142 h_gp = omap36xx_gp_hwmod_ocp_ifs; 3143 h_sham = omap36xx_sham_hwmod_ocp_ifs; 3144 h_aes = omap36xx_aes_hwmod_ocp_ifs; 3145 } else { 3146 WARN(1, "OMAP3 hwmod family init: unknown chip type\n"); 3147 return -EINVAL; 3148 } 3149 3150 r = omap_hwmod_register_links(h); 3151 if (r < 0) 3152 return r; 3153 3154 /* Register GP-only hwmod links. */ 3155 if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) { 3156 r = omap_hwmod_register_links(h_gp); 3157 if (r < 0) 3158 return r; 3159 } 3160 3161 /* 3162 * Register crypto hwmod links only if they are not disabled in DT. 3163 * If DT information is missing, enable them only for GP devices. 3164 */ 3165 3166 bus = of_find_node_by_name(NULL, "ocp"); 3167 3168 if (h_sham && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "sham")) { 3169 r = omap_hwmod_register_links(h_sham); 3170 if (r < 0) 3171 goto put_node; 3172 } 3173 3174 if (h_aes && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "aes")) { 3175 r = omap_hwmod_register_links(h_aes); 3176 if (r < 0) 3177 goto put_node; 3178 } 3179 of_node_put(bus); 3180 3181 /* 3182 * Register hwmod links specific to certain ES levels of a 3183 * particular family of silicon (e.g., 34xx ES1.0) 3184 */ 3185 h = NULL; 3186 if (rev == OMAP3430_REV_ES1_0) { 3187 h = omap3430es1_hwmod_ocp_ifs; 3188 } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 || 3189 rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || 3190 rev == OMAP3430_REV_ES3_1_2) { 3191 h = omap3430es2plus_hwmod_ocp_ifs; 3192 } 3193 3194 if (h) { 3195 r = omap_hwmod_register_links(h); 3196 if (r < 0) 3197 return r; 3198 } 3199 3200 h = NULL; 3201 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || 3202 rev == OMAP3430_REV_ES2_1) { 3203 h = omap3430_pre_es3_hwmod_ocp_ifs; 3204 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || 3205 rev == OMAP3430_REV_ES3_1_2) { 3206 h = omap3430_es3plus_hwmod_ocp_ifs; 3207 } 3208 3209 if (h) 3210 r = omap_hwmod_register_links(h); 3211 if (r < 0) 3212 return r; 3213 3214 /* 3215 * DSS code presumes that dss_core hwmod is handled first, 3216 * _before_ any other DSS related hwmods so register common 3217 * DSS hwmod links last to ensure that dss_core is already 3218 * registered. Otherwise some change things may happen, for 3219 * ex. if dispc is handled before dss_core and DSS is enabled 3220 * in bootloader DISPC will be reset with outputs enabled 3221 * which sometimes leads to unrecoverable L3 error. XXX The 3222 * long-term fix to this is to ensure hwmods are set up in 3223 * dependency order in the hwmod core code. 3224 */ 3225 r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs); 3226 3227 return r; 3228 3229 put_node: 3230 of_node_put(bus); 3231 return r; 3232 } 3233