1 /*
2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
3  *
4  * Copyright (C) 2009-2011 Nokia Corporation
5  * Copyright (C) 2012 Texas Instruments, Inc.
6  * Paul Walmsley
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  *
12  * The data in this file should be completely autogeneratable from
13  * the TI hardware database or other technical documentation.
14  *
15  * XXX these should be marked initdata for multi-OMAP kernels
16  */
17 
18 #include <linux/platform_data/i2c-omap.h>
19 #include <linux/power/smartreflex.h>
20 #include <linux/platform_data/hsmmc-omap.h>
21 
22 #include <linux/omap-dma.h>
23 #include "l3_3xxx.h"
24 #include "l4_3xxx.h"
25 
26 #include "soc.h"
27 #include "omap_hwmod.h"
28 #include "omap_hwmod_common_data.h"
29 #include "prm-regbits-34xx.h"
30 #include "cm-regbits-34xx.h"
31 
32 #include "i2c.h"
33 #include "wd_timer.h"
34 #include "serial.h"
35 
36 /*
37  * OMAP3xxx hardware module integration data
38  *
39  * All of the data in this section should be autogeneratable from the
40  * TI hardware database or other technical documentation.  Data that
41  * is driver-specific or driver-kernel integration-specific belongs
42  * elsewhere.
43  */
44 
45 #define AM35XX_IPSS_USBOTGSS_BASE      0x5C040000
46 
47 /*
48  * IP blocks
49  */
50 
51 /* L3 */
52 
53 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
54 	.name		= "l3_main",
55 	.class		= &l3_hwmod_class,
56 	.flags		= HWMOD_NO_IDLEST,
57 };
58 
59 /* L4 CORE */
60 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
61 	.name		= "l4_core",
62 	.class		= &l4_hwmod_class,
63 	.flags		= HWMOD_NO_IDLEST,
64 };
65 
66 /* L4 PER */
67 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
68 	.name		= "l4_per",
69 	.class		= &l4_hwmod_class,
70 	.flags		= HWMOD_NO_IDLEST,
71 };
72 
73 /* L4 WKUP */
74 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
75 	.name		= "l4_wkup",
76 	.class		= &l4_hwmod_class,
77 	.flags		= HWMOD_NO_IDLEST,
78 };
79 
80 /* L4 SEC */
81 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
82 	.name		= "l4_sec",
83 	.class		= &l4_hwmod_class,
84 	.flags		= HWMOD_NO_IDLEST,
85 };
86 
87 /* MPU */
88 
89 static struct omap_hwmod omap3xxx_mpu_hwmod = {
90 	.name		= "mpu",
91 	.class		= &mpu_hwmod_class,
92 	.main_clk	= "arm_fck",
93 };
94 
95 /* IVA2 (IVA2) */
96 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
97 	{ .name = "logic", .rst_shift = 0, .st_shift = 8 },
98 	{ .name = "seq0", .rst_shift = 1, .st_shift = 9 },
99 	{ .name = "seq1", .rst_shift = 2, .st_shift = 10 },
100 };
101 
102 static struct omap_hwmod omap3xxx_iva_hwmod = {
103 	.name		= "iva",
104 	.class		= &iva_hwmod_class,
105 	.clkdm_name	= "iva2_clkdm",
106 	.rst_lines	= omap3xxx_iva_resets,
107 	.rst_lines_cnt	= ARRAY_SIZE(omap3xxx_iva_resets),
108 	.main_clk	= "iva2_ck",
109 	.prcm = {
110 		.omap2 = {
111 			.module_offs = OMAP3430_IVA2_MOD,
112 			.idlest_reg_id = 1,
113 			.idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
114 		},
115 	},
116 };
117 
118 /*
119  * 'debugss' class
120  * debug and emulation sub system
121  */
122 
123 static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = {
124 	.name	= "debugss",
125 };
126 
127 /* debugss */
128 static struct omap_hwmod omap3xxx_debugss_hwmod = {
129 	.name		= "debugss",
130 	.class		= &omap3xxx_debugss_hwmod_class,
131 	.clkdm_name	= "emu_clkdm",
132 	.main_clk	= "emu_src_ck",
133 	.flags		= HWMOD_NO_IDLEST,
134 };
135 
136 /* timer class */
137 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
138 	.rev_offs	= 0x0000,
139 	.sysc_offs	= 0x0010,
140 	.syss_offs	= 0x0014,
141 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
142 			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
143 			   SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
144 			   SYSS_HAS_RESET_STATUS),
145 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
146 	.sysc_fields	= &omap_hwmod_sysc_type1,
147 };
148 
149 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
150 	.name = "timer",
151 	.sysc = &omap3xxx_timer_sysc,
152 };
153 
154 /* timer1 */
155 static struct omap_hwmod omap3xxx_timer1_hwmod = {
156 	.name		= "timer1",
157 	.main_clk	= "gpt1_fck",
158 	.prcm		= {
159 		.omap2 = {
160 			.module_offs = WKUP_MOD,
161 			.idlest_reg_id = 1,
162 			.idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
163 		},
164 	},
165 	.class		= &omap3xxx_timer_hwmod_class,
166 	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
167 };
168 
169 /* timer2 */
170 static struct omap_hwmod omap3xxx_timer2_hwmod = {
171 	.name		= "timer2",
172 	.main_clk	= "gpt2_fck",
173 	.prcm		= {
174 		.omap2 = {
175 			.module_offs = OMAP3430_PER_MOD,
176 			.idlest_reg_id = 1,
177 			.idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
178 		},
179 	},
180 	.class		= &omap3xxx_timer_hwmod_class,
181 	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
182 };
183 
184 /* timer3 */
185 static struct omap_hwmod omap3xxx_timer3_hwmod = {
186 	.name		= "timer3",
187 	.main_clk	= "gpt3_fck",
188 	.prcm		= {
189 		.omap2 = {
190 			.module_offs = OMAP3430_PER_MOD,
191 			.idlest_reg_id = 1,
192 			.idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
193 		},
194 	},
195 	.class		= &omap3xxx_timer_hwmod_class,
196 	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
197 };
198 
199 /* timer4 */
200 static struct omap_hwmod omap3xxx_timer4_hwmod = {
201 	.name		= "timer4",
202 	.main_clk	= "gpt4_fck",
203 	.prcm		= {
204 		.omap2 = {
205 			.module_offs = OMAP3430_PER_MOD,
206 			.idlest_reg_id = 1,
207 			.idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
208 		},
209 	},
210 	.class		= &omap3xxx_timer_hwmod_class,
211 	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
212 };
213 
214 /* timer5 */
215 static struct omap_hwmod omap3xxx_timer5_hwmod = {
216 	.name		= "timer5",
217 	.main_clk	= "gpt5_fck",
218 	.prcm		= {
219 		.omap2 = {
220 			.module_offs = OMAP3430_PER_MOD,
221 			.idlest_reg_id = 1,
222 			.idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
223 		},
224 	},
225 	.class		= &omap3xxx_timer_hwmod_class,
226 	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
227 };
228 
229 /* timer6 */
230 static struct omap_hwmod omap3xxx_timer6_hwmod = {
231 	.name		= "timer6",
232 	.main_clk	= "gpt6_fck",
233 	.prcm		= {
234 		.omap2 = {
235 			.module_offs = OMAP3430_PER_MOD,
236 			.idlest_reg_id = 1,
237 			.idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
238 		},
239 	},
240 	.class		= &omap3xxx_timer_hwmod_class,
241 	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
242 };
243 
244 /* timer7 */
245 static struct omap_hwmod omap3xxx_timer7_hwmod = {
246 	.name		= "timer7",
247 	.main_clk	= "gpt7_fck",
248 	.prcm		= {
249 		.omap2 = {
250 			.module_offs = OMAP3430_PER_MOD,
251 			.idlest_reg_id = 1,
252 			.idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
253 		},
254 	},
255 	.class		= &omap3xxx_timer_hwmod_class,
256 	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
257 };
258 
259 /* timer8 */
260 static struct omap_hwmod omap3xxx_timer8_hwmod = {
261 	.name		= "timer8",
262 	.main_clk	= "gpt8_fck",
263 	.prcm		= {
264 		.omap2 = {
265 			.module_offs = OMAP3430_PER_MOD,
266 			.idlest_reg_id = 1,
267 			.idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
268 		},
269 	},
270 	.class		= &omap3xxx_timer_hwmod_class,
271 	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
272 };
273 
274 /* timer9 */
275 static struct omap_hwmod omap3xxx_timer9_hwmod = {
276 	.name		= "timer9",
277 	.main_clk	= "gpt9_fck",
278 	.prcm		= {
279 		.omap2 = {
280 			.module_offs = OMAP3430_PER_MOD,
281 			.idlest_reg_id = 1,
282 			.idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
283 		},
284 	},
285 	.class		= &omap3xxx_timer_hwmod_class,
286 	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
287 };
288 
289 /* timer10 */
290 static struct omap_hwmod omap3xxx_timer10_hwmod = {
291 	.name		= "timer10",
292 	.main_clk	= "gpt10_fck",
293 	.prcm		= {
294 		.omap2 = {
295 			.module_offs = CORE_MOD,
296 			.idlest_reg_id = 1,
297 			.idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
298 		},
299 	},
300 	.class		= &omap3xxx_timer_hwmod_class,
301 	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
302 };
303 
304 /* timer11 */
305 static struct omap_hwmod omap3xxx_timer11_hwmod = {
306 	.name		= "timer11",
307 	.main_clk	= "gpt11_fck",
308 	.prcm		= {
309 		.omap2 = {
310 			.module_offs = CORE_MOD,
311 			.idlest_reg_id = 1,
312 			.idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
313 		},
314 	},
315 	.class		= &omap3xxx_timer_hwmod_class,
316 	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
317 };
318 
319 /* timer12 */
320 static struct omap_hwmod omap3xxx_timer12_hwmod = {
321 	.name		= "timer12",
322 	.main_clk	= "gpt12_fck",
323 	.prcm		= {
324 		.omap2 = {
325 			.module_offs = WKUP_MOD,
326 			.idlest_reg_id = 1,
327 			.idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
328 		},
329 	},
330 	.class		= &omap3xxx_timer_hwmod_class,
331 	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
332 };
333 
334 /*
335  * 'wd_timer' class
336  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
337  * overflow condition
338  */
339 
340 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
341 	.rev_offs	= 0x0000,
342 	.sysc_offs	= 0x0010,
343 	.syss_offs	= 0x0014,
344 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
345 			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
346 			   SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
347 			   SYSS_HAS_RESET_STATUS),
348 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
349 	.sysc_fields    = &omap_hwmod_sysc_type1,
350 };
351 
352 /* I2C common */
353 static struct omap_hwmod_class_sysconfig i2c_sysc = {
354 	.rev_offs	= 0x00,
355 	.sysc_offs	= 0x20,
356 	.syss_offs	= 0x10,
357 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
358 			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
359 			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
360 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
361 	.sysc_fields    = &omap_hwmod_sysc_type1,
362 };
363 
364 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
365 	.name		= "wd_timer",
366 	.sysc		= &omap3xxx_wd_timer_sysc,
367 	.pre_shutdown	= &omap2_wd_timer_disable,
368 	.reset		= &omap2_wd_timer_reset,
369 };
370 
371 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
372 	.name		= "wd_timer2",
373 	.class		= &omap3xxx_wd_timer_hwmod_class,
374 	.main_clk	= "wdt2_fck",
375 	.prcm		= {
376 		.omap2 = {
377 			.module_offs = WKUP_MOD,
378 			.idlest_reg_id = 1,
379 			.idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
380 		},
381 	},
382 	/*
383 	 * XXX: Use software supervised mode, HW supervised smartidle seems to
384 	 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
385 	 */
386 	.flags		= HWMOD_SWSUP_SIDLE,
387 };
388 
389 /* UART1 */
390 static struct omap_hwmod omap3xxx_uart1_hwmod = {
391 	.name		= "uart1",
392 	.main_clk	= "uart1_fck",
393 	.flags		= DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE,
394 	.prcm		= {
395 		.omap2 = {
396 			.module_offs = CORE_MOD,
397 			.idlest_reg_id = 1,
398 			.idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
399 		},
400 	},
401 	.class		= &omap2_uart_class,
402 };
403 
404 /* UART2 */
405 static struct omap_hwmod omap3xxx_uart2_hwmod = {
406 	.name		= "uart2",
407 	.main_clk	= "uart2_fck",
408 	.flags		= DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE,
409 	.prcm		= {
410 		.omap2 = {
411 			.module_offs = CORE_MOD,
412 			.idlest_reg_id = 1,
413 			.idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
414 		},
415 	},
416 	.class		= &omap2_uart_class,
417 };
418 
419 /* UART3 */
420 static struct omap_hwmod omap3xxx_uart3_hwmod = {
421 	.name		= "uart3",
422 	.main_clk	= "uart3_fck",
423 	.flags		= DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS |
424 				HWMOD_SWSUP_SIDLE,
425 	.prcm		= {
426 		.omap2 = {
427 			.module_offs = OMAP3430_PER_MOD,
428 			.idlest_reg_id = 1,
429 			.idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
430 		},
431 	},
432 	.class		= &omap2_uart_class,
433 };
434 
435 /* UART4 */
436 
437 
438 static struct omap_hwmod omap36xx_uart4_hwmod = {
439 	.name		= "uart4",
440 	.main_clk	= "uart4_fck",
441 	.flags		= DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE,
442 	.prcm		= {
443 		.omap2 = {
444 			.module_offs = OMAP3430_PER_MOD,
445 			.idlest_reg_id = 1,
446 			.idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
447 		},
448 	},
449 	.class		= &omap2_uart_class,
450 };
451 
452 
453 
454 /*
455  * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
456  * uart2_fck being enabled.  So we add uart1_fck as an optional clock,
457  * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET.  This really
458  * should not be needed.  The functional clock structure of the AM35xx
459  * UART4 is extremely unclear and opaque; it is unclear what the role
460  * of uart1/2_fck is for the UART4.  Any clarification from either
461  * empirical testing or the AM3505/3517 hardware designers would be
462  * most welcome.
463  */
464 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
465 	{ .role = "softreset_uart1_fck", .clk = "uart1_fck" },
466 };
467 
468 static struct omap_hwmod am35xx_uart4_hwmod = {
469 	.name		= "uart4",
470 	.main_clk	= "uart4_fck",
471 	.prcm		= {
472 		.omap2 = {
473 			.module_offs = CORE_MOD,
474 			.idlest_reg_id = 1,
475 			.idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
476 		},
477 	},
478 	.opt_clks	= am35xx_uart4_opt_clks,
479 	.opt_clks_cnt	= ARRAY_SIZE(am35xx_uart4_opt_clks),
480 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
481 	.class		= &omap2_uart_class,
482 };
483 
484 static struct omap_hwmod_class i2c_class = {
485 	.name	= "i2c",
486 	.sysc	= &i2c_sysc,
487 	.rev	= OMAP_I2C_IP_VERSION_1,
488 	.reset	= &omap_i2c_reset,
489 };
490 
491 /* dss */
492 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
493 	/*
494 	 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
495 	 * driver does not use these clocks.
496 	 */
497 	{ .role = "sys_clk", .clk = "dss2_alwon_fck" },
498 	{ .role = "tv_clk", .clk = "dss_tv_fck" },
499 	/* required only on OMAP3430 */
500 	{ .role = "tv_dac_clk", .clk = "dss_96m_fck" },
501 };
502 
503 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
504 	.name		= "dss_core",
505 	.class		= &omap2_dss_hwmod_class,
506 	.main_clk	= "dss1_alwon_fck", /* instead of dss_fck */
507 	.prcm		= {
508 		.omap2 = {
509 			.module_offs = OMAP3430_DSS_MOD,
510 			.idlest_reg_id = 1,
511 		},
512 	},
513 	.opt_clks	= dss_opt_clks,
514 	.opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
515 	.flags		= HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
516 };
517 
518 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
519 	.name		= "dss_core",
520 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
521 	.class		= &omap2_dss_hwmod_class,
522 	.main_clk	= "dss1_alwon_fck", /* instead of dss_fck */
523 	.prcm		= {
524 		.omap2 = {
525 			.module_offs = OMAP3430_DSS_MOD,
526 			.idlest_reg_id = 1,
527 			.idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
528 		},
529 	},
530 	.opt_clks	= dss_opt_clks,
531 	.opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
532 };
533 
534 /*
535  * 'dispc' class
536  * display controller
537  */
538 
539 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
540 	.rev_offs	= 0x0000,
541 	.sysc_offs	= 0x0010,
542 	.syss_offs	= 0x0014,
543 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
544 			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
545 			   SYSC_HAS_ENAWAKEUP),
546 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
547 			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
548 	.sysc_fields	= &omap_hwmod_sysc_type1,
549 };
550 
551 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
552 	.name	= "dispc",
553 	.sysc	= &omap3_dispc_sysc,
554 };
555 
556 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
557 	.name		= "dss_dispc",
558 	.class		= &omap3_dispc_hwmod_class,
559 	.main_clk	= "dss1_alwon_fck",
560 	.prcm		= {
561 		.omap2 = {
562 			.module_offs = OMAP3430_DSS_MOD,
563 		},
564 	},
565 	.flags		= HWMOD_NO_IDLEST,
566 	.dev_attr	= &omap2_3_dss_dispc_dev_attr,
567 };
568 
569 /*
570  * 'dsi' class
571  * display serial interface controller
572  */
573 
574 static struct omap_hwmod_class_sysconfig omap3xxx_dsi_sysc = {
575 	.rev_offs	= 0x0000,
576 	.sysc_offs	= 0x0010,
577 	.syss_offs	= 0x0014,
578 	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
579 			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
580 			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
581 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
582 	.sysc_fields	= &omap_hwmod_sysc_type1,
583 };
584 
585 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
586 	.name = "dsi",
587 	.sysc	= &omap3xxx_dsi_sysc,
588 };
589 
590 /* dss_dsi1 */
591 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
592 	{ .role = "sys_clk", .clk = "dss2_alwon_fck" },
593 };
594 
595 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
596 	.name		= "dss_dsi1",
597 	.class		= &omap3xxx_dsi_hwmod_class,
598 	.main_clk	= "dss1_alwon_fck",
599 	.prcm		= {
600 		.omap2 = {
601 			.module_offs = OMAP3430_DSS_MOD,
602 		},
603 	},
604 	.opt_clks	= dss_dsi1_opt_clks,
605 	.opt_clks_cnt	= ARRAY_SIZE(dss_dsi1_opt_clks),
606 	.flags		= HWMOD_NO_IDLEST,
607 };
608 
609 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
610 	{ .role = "ick", .clk = "dss_ick" },
611 };
612 
613 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
614 	.name		= "dss_rfbi",
615 	.class		= &omap2_rfbi_hwmod_class,
616 	.main_clk	= "dss1_alwon_fck",
617 	.prcm		= {
618 		.omap2 = {
619 			.module_offs = OMAP3430_DSS_MOD,
620 		},
621 	},
622 	.opt_clks	= dss_rfbi_opt_clks,
623 	.opt_clks_cnt	= ARRAY_SIZE(dss_rfbi_opt_clks),
624 	.flags		= HWMOD_NO_IDLEST,
625 };
626 
627 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
628 	/* required only on OMAP3430 */
629 	{ .role = "tv_dac_clk", .clk = "dss_96m_fck" },
630 };
631 
632 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
633 	.name		= "dss_venc",
634 	.class		= &omap2_venc_hwmod_class,
635 	.main_clk	= "dss_tv_fck",
636 	.prcm		= {
637 		.omap2 = {
638 			.module_offs = OMAP3430_DSS_MOD,
639 		},
640 	},
641 	.opt_clks	= dss_venc_opt_clks,
642 	.opt_clks_cnt	= ARRAY_SIZE(dss_venc_opt_clks),
643 	.flags		= HWMOD_NO_IDLEST,
644 };
645 
646 /* I2C1 */
647 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
648 	.name		= "i2c1",
649 	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
650 	.main_clk	= "i2c1_fck",
651 	.prcm		= {
652 		.omap2 = {
653 			.module_offs = CORE_MOD,
654 			.idlest_reg_id = 1,
655 			.idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
656 		},
657 	},
658 	.class		= &i2c_class,
659 };
660 
661 /* I2C2 */
662 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
663 	.name		= "i2c2",
664 	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
665 	.main_clk	= "i2c2_fck",
666 	.prcm		= {
667 		.omap2 = {
668 			.module_offs = CORE_MOD,
669 			.idlest_reg_id = 1,
670 			.idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
671 		},
672 	},
673 	.class		= &i2c_class,
674 };
675 
676 /* I2C3 */
677 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
678 	.name		= "i2c3",
679 	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
680 	.main_clk	= "i2c3_fck",
681 	.prcm		= {
682 		.omap2 = {
683 			.module_offs = CORE_MOD,
684 			.idlest_reg_id = 1,
685 			.idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
686 		},
687 	},
688 	.class		= &i2c_class,
689 };
690 
691 /*
692  * 'gpio' class
693  * general purpose io module
694  */
695 
696 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
697 	.rev_offs	= 0x0000,
698 	.sysc_offs	= 0x0010,
699 	.syss_offs	= 0x0014,
700 	.sysc_flags	= (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
701 			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
702 			   SYSS_HAS_RESET_STATUS),
703 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
704 	.sysc_fields    = &omap_hwmod_sysc_type1,
705 };
706 
707 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
708 	.name = "gpio",
709 	.sysc = &omap3xxx_gpio_sysc,
710 	.rev = 1,
711 };
712 
713 /* gpio1 */
714 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
715 	{ .role = "dbclk", .clk = "gpio1_dbck", },
716 };
717 
718 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
719 	.name		= "gpio1",
720 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
721 	.main_clk	= "gpio1_ick",
722 	.opt_clks	= gpio1_opt_clks,
723 	.opt_clks_cnt	= ARRAY_SIZE(gpio1_opt_clks),
724 	.prcm		= {
725 		.omap2 = {
726 			.module_offs = WKUP_MOD,
727 			.idlest_reg_id = 1,
728 			.idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
729 		},
730 	},
731 	.class		= &omap3xxx_gpio_hwmod_class,
732 };
733 
734 /* gpio2 */
735 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
736 	{ .role = "dbclk", .clk = "gpio2_dbck", },
737 };
738 
739 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
740 	.name		= "gpio2",
741 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
742 	.main_clk	= "gpio2_ick",
743 	.opt_clks	= gpio2_opt_clks,
744 	.opt_clks_cnt	= ARRAY_SIZE(gpio2_opt_clks),
745 	.prcm		= {
746 		.omap2 = {
747 			.module_offs = OMAP3430_PER_MOD,
748 			.idlest_reg_id = 1,
749 			.idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
750 		},
751 	},
752 	.class		= &omap3xxx_gpio_hwmod_class,
753 };
754 
755 /* gpio3 */
756 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
757 	{ .role = "dbclk", .clk = "gpio3_dbck", },
758 };
759 
760 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
761 	.name		= "gpio3",
762 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
763 	.main_clk	= "gpio3_ick",
764 	.opt_clks	= gpio3_opt_clks,
765 	.opt_clks_cnt	= ARRAY_SIZE(gpio3_opt_clks),
766 	.prcm		= {
767 		.omap2 = {
768 			.module_offs = OMAP3430_PER_MOD,
769 			.idlest_reg_id = 1,
770 			.idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
771 		},
772 	},
773 	.class		= &omap3xxx_gpio_hwmod_class,
774 };
775 
776 /* gpio4 */
777 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
778 	{ .role = "dbclk", .clk = "gpio4_dbck", },
779 };
780 
781 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
782 	.name		= "gpio4",
783 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
784 	.main_clk	= "gpio4_ick",
785 	.opt_clks	= gpio4_opt_clks,
786 	.opt_clks_cnt	= ARRAY_SIZE(gpio4_opt_clks),
787 	.prcm		= {
788 		.omap2 = {
789 			.module_offs = OMAP3430_PER_MOD,
790 			.idlest_reg_id = 1,
791 			.idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
792 		},
793 	},
794 	.class		= &omap3xxx_gpio_hwmod_class,
795 };
796 
797 /* gpio5 */
798 
799 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
800 	{ .role = "dbclk", .clk = "gpio5_dbck", },
801 };
802 
803 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
804 	.name		= "gpio5",
805 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
806 	.main_clk	= "gpio5_ick",
807 	.opt_clks	= gpio5_opt_clks,
808 	.opt_clks_cnt	= ARRAY_SIZE(gpio5_opt_clks),
809 	.prcm		= {
810 		.omap2 = {
811 			.module_offs = OMAP3430_PER_MOD,
812 			.idlest_reg_id = 1,
813 			.idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
814 		},
815 	},
816 	.class		= &omap3xxx_gpio_hwmod_class,
817 };
818 
819 /* gpio6 */
820 
821 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
822 	{ .role = "dbclk", .clk = "gpio6_dbck", },
823 };
824 
825 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
826 	.name		= "gpio6",
827 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
828 	.main_clk	= "gpio6_ick",
829 	.opt_clks	= gpio6_opt_clks,
830 	.opt_clks_cnt	= ARRAY_SIZE(gpio6_opt_clks),
831 	.prcm		= {
832 		.omap2 = {
833 			.module_offs = OMAP3430_PER_MOD,
834 			.idlest_reg_id = 1,
835 			.idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
836 		},
837 	},
838 	.class		= &omap3xxx_gpio_hwmod_class,
839 };
840 
841 /* dma attributes */
842 static struct omap_dma_dev_attr dma_dev_attr = {
843 	.dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
844 				IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
845 	.lch_count = 32,
846 };
847 
848 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
849 	.rev_offs	= 0x0000,
850 	.sysc_offs	= 0x002c,
851 	.syss_offs	= 0x0028,
852 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
853 			   SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
854 			   SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
855 			   SYSS_HAS_RESET_STATUS),
856 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
857 			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
858 	.sysc_fields	= &omap_hwmod_sysc_type1,
859 };
860 
861 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
862 	.name = "dma",
863 	.sysc = &omap3xxx_dma_sysc,
864 };
865 
866 /* dma_system */
867 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
868 	.name		= "dma",
869 	.class		= &omap3xxx_dma_hwmod_class,
870 	.main_clk	= "core_l3_ick",
871 	.prcm = {
872 		.omap2 = {
873 			.module_offs		= CORE_MOD,
874 			.idlest_reg_id		= 1,
875 			.idlest_idle_bit	= OMAP3430_ST_SDMA_SHIFT,
876 		},
877 	},
878 	.dev_attr	= &dma_dev_attr,
879 	.flags		= HWMOD_NO_IDLEST,
880 };
881 
882 /*
883  * 'mcbsp' class
884  * multi channel buffered serial port controller
885  */
886 
887 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
888 	.rev_offs	= -ENODEV,
889 	.sysc_offs	= 0x008c,
890 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
891 			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
892 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
893 	.sysc_fields	= &omap_hwmod_sysc_type1,
894 };
895 
896 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
897 	.name = "mcbsp",
898 	.sysc = &omap3xxx_mcbsp_sysc,
899 };
900 
901 /* McBSP functional clock mapping */
902 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
903 	{ .role = "pad_fck", .clk = "mcbsp_clks" },
904 	{ .role = "prcm_fck", .clk = "core_96m_fck" },
905 };
906 
907 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
908 	{ .role = "pad_fck", .clk = "mcbsp_clks" },
909 	{ .role = "prcm_fck", .clk = "per_96m_fck" },
910 };
911 
912 /* mcbsp1 */
913 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
914 	.name		= "mcbsp1",
915 	.class		= &omap3xxx_mcbsp_hwmod_class,
916 	.main_clk	= "mcbsp1_fck",
917 	.prcm		= {
918 		.omap2 = {
919 			.module_offs = CORE_MOD,
920 			.idlest_reg_id = 1,
921 			.idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
922 		},
923 	},
924 	.opt_clks	= mcbsp15_opt_clks,
925 	.opt_clks_cnt	= ARRAY_SIZE(mcbsp15_opt_clks),
926 };
927 
928 /* mcbsp2 */
929 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
930 	.name		= "mcbsp2",
931 	.class		= &omap3xxx_mcbsp_hwmod_class,
932 	.main_clk	= "mcbsp2_fck",
933 	.prcm		= {
934 		.omap2 = {
935 			.module_offs = OMAP3430_PER_MOD,
936 			.idlest_reg_id = 1,
937 			.idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
938 		},
939 	},
940 	.opt_clks	= mcbsp234_opt_clks,
941 	.opt_clks_cnt	= ARRAY_SIZE(mcbsp234_opt_clks),
942 };
943 
944 /* mcbsp3 */
945 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
946 	.name		= "mcbsp3",
947 	.class		= &omap3xxx_mcbsp_hwmod_class,
948 	.main_clk	= "mcbsp3_fck",
949 	.prcm		= {
950 		.omap2 = {
951 			.module_offs = OMAP3430_PER_MOD,
952 			.idlest_reg_id = 1,
953 			.idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
954 		},
955 	},
956 	.opt_clks	= mcbsp234_opt_clks,
957 	.opt_clks_cnt	= ARRAY_SIZE(mcbsp234_opt_clks),
958 };
959 
960 /* mcbsp4 */
961 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
962 	.name		= "mcbsp4",
963 	.class		= &omap3xxx_mcbsp_hwmod_class,
964 	.main_clk	= "mcbsp4_fck",
965 	.prcm		= {
966 		.omap2 = {
967 			.module_offs = OMAP3430_PER_MOD,
968 			.idlest_reg_id = 1,
969 			.idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
970 		},
971 	},
972 	.opt_clks	= mcbsp234_opt_clks,
973 	.opt_clks_cnt	= ARRAY_SIZE(mcbsp234_opt_clks),
974 };
975 
976 /* mcbsp5 */
977 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
978 	.name		= "mcbsp5",
979 	.class		= &omap3xxx_mcbsp_hwmod_class,
980 	.main_clk	= "mcbsp5_fck",
981 	.prcm		= {
982 		.omap2 = {
983 			.module_offs = CORE_MOD,
984 			.idlest_reg_id = 1,
985 			.idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
986 		},
987 	},
988 	.opt_clks	= mcbsp15_opt_clks,
989 	.opt_clks_cnt	= ARRAY_SIZE(mcbsp15_opt_clks),
990 };
991 
992 /* 'mcbsp sidetone' class */
993 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
994 	.rev_offs	= -ENODEV,
995 	.sysc_offs	= 0x0010,
996 	.sysc_flags	= SYSC_HAS_AUTOIDLE,
997 	.sysc_fields	= &omap_hwmod_sysc_type1,
998 };
999 
1000 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1001 	.name = "mcbsp_sidetone",
1002 	.sysc = &omap3xxx_mcbsp_sidetone_sysc,
1003 };
1004 
1005 /* mcbsp2_sidetone */
1006 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1007 	.name		= "mcbsp2_sidetone",
1008 	.class		= &omap3xxx_mcbsp_sidetone_hwmod_class,
1009 	.main_clk	= "mcbsp2_ick",
1010 	.flags		= HWMOD_NO_IDLEST,
1011 };
1012 
1013 /* mcbsp3_sidetone */
1014 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1015 	.name		= "mcbsp3_sidetone",
1016 	.class		= &omap3xxx_mcbsp_sidetone_hwmod_class,
1017 	.main_clk	= "mcbsp3_ick",
1018 	.flags		= HWMOD_NO_IDLEST,
1019 };
1020 
1021 /* SR common */
1022 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1023 	.rev_offs	= -ENODEV,
1024 	.sysc_offs	= 0x24,
1025 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1026 	.sysc_fields	= &omap34xx_sr_sysc_fields,
1027 };
1028 
1029 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1030 	.name = "smartreflex",
1031 	.sysc = &omap34xx_sr_sysc,
1032 	.rev  = 1,
1033 };
1034 
1035 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1036 	.rev_offs	= -ENODEV,
1037 	.sysc_offs	= 0x38,
1038 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1039 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1040 			SYSC_NO_CACHE),
1041 	.sysc_fields	= &omap36xx_sr_sysc_fields,
1042 };
1043 
1044 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1045 	.name = "smartreflex",
1046 	.sysc = &omap36xx_sr_sysc,
1047 	.rev  = 2,
1048 };
1049 
1050 /* SR1 */
1051 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1052 	.sensor_voltdm_name   = "mpu_iva",
1053 };
1054 
1055 
1056 static struct omap_hwmod omap34xx_sr1_hwmod = {
1057 	.name		= "smartreflex_mpu_iva",
1058 	.class		= &omap34xx_smartreflex_hwmod_class,
1059 	.main_clk	= "sr1_fck",
1060 	.prcm		= {
1061 		.omap2 = {
1062 			.module_offs = WKUP_MOD,
1063 			.idlest_reg_id = 1,
1064 			.idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1065 		},
1066 	},
1067 	.dev_attr	= &sr1_dev_attr,
1068 	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
1069 };
1070 
1071 static struct omap_hwmod omap36xx_sr1_hwmod = {
1072 	.name		= "smartreflex_mpu_iva",
1073 	.class		= &omap36xx_smartreflex_hwmod_class,
1074 	.main_clk	= "sr1_fck",
1075 	.prcm		= {
1076 		.omap2 = {
1077 			.module_offs = WKUP_MOD,
1078 			.idlest_reg_id = 1,
1079 			.idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1080 		},
1081 	},
1082 	.dev_attr	= &sr1_dev_attr,
1083 };
1084 
1085 /* SR2 */
1086 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1087 	.sensor_voltdm_name	= "core",
1088 };
1089 
1090 
1091 static struct omap_hwmod omap34xx_sr2_hwmod = {
1092 	.name		= "smartreflex_core",
1093 	.class		= &omap34xx_smartreflex_hwmod_class,
1094 	.main_clk	= "sr2_fck",
1095 	.prcm		= {
1096 		.omap2 = {
1097 			.module_offs = WKUP_MOD,
1098 			.idlest_reg_id = 1,
1099 			.idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1100 		},
1101 	},
1102 	.dev_attr	= &sr2_dev_attr,
1103 	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
1104 };
1105 
1106 static struct omap_hwmod omap36xx_sr2_hwmod = {
1107 	.name		= "smartreflex_core",
1108 	.class		= &omap36xx_smartreflex_hwmod_class,
1109 	.main_clk	= "sr2_fck",
1110 	.prcm		= {
1111 		.omap2 = {
1112 			.module_offs = WKUP_MOD,
1113 			.idlest_reg_id = 1,
1114 			.idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1115 		},
1116 	},
1117 	.dev_attr	= &sr2_dev_attr,
1118 };
1119 
1120 /*
1121  * 'mailbox' class
1122  * mailbox module allowing communication between the on-chip processors
1123  * using a queued mailbox-interrupt mechanism.
1124  */
1125 
1126 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1127 	.rev_offs	= 0x000,
1128 	.sysc_offs	= 0x010,
1129 	.syss_offs	= 0x014,
1130 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1131 				SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1132 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1133 	.sysc_fields	= &omap_hwmod_sysc_type1,
1134 };
1135 
1136 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1137 	.name = "mailbox",
1138 	.sysc = &omap3xxx_mailbox_sysc,
1139 };
1140 
1141 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1142 	.name		= "mailbox",
1143 	.class		= &omap3xxx_mailbox_hwmod_class,
1144 	.main_clk	= "mailboxes_ick",
1145 	.prcm		= {
1146 		.omap2 = {
1147 			.module_offs = CORE_MOD,
1148 			.idlest_reg_id = 1,
1149 			.idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1150 		},
1151 	},
1152 };
1153 
1154 /*
1155  * 'mcspi' class
1156  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1157  * bus
1158  */
1159 
1160 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1161 	.rev_offs	= 0x0000,
1162 	.sysc_offs	= 0x0010,
1163 	.syss_offs	= 0x0014,
1164 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1165 				SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1166 				SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1167 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1168 	.sysc_fields    = &omap_hwmod_sysc_type1,
1169 };
1170 
1171 static struct omap_hwmod_class omap34xx_mcspi_class = {
1172 	.name = "mcspi",
1173 	.sysc = &omap34xx_mcspi_sysc,
1174 };
1175 
1176 /* mcspi1 */
1177 static struct omap_hwmod omap34xx_mcspi1 = {
1178 	.name		= "mcspi1",
1179 	.main_clk	= "mcspi1_fck",
1180 	.prcm		= {
1181 		.omap2 = {
1182 			.module_offs = CORE_MOD,
1183 			.idlest_reg_id = 1,
1184 			.idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1185 		},
1186 	},
1187 	.class		= &omap34xx_mcspi_class,
1188 };
1189 
1190 /* mcspi2 */
1191 static struct omap_hwmod omap34xx_mcspi2 = {
1192 	.name		= "mcspi2",
1193 	.main_clk	= "mcspi2_fck",
1194 	.prcm		= {
1195 		.omap2 = {
1196 			.module_offs = CORE_MOD,
1197 			.idlest_reg_id = 1,
1198 			.idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1199 		},
1200 	},
1201 	.class		= &omap34xx_mcspi_class,
1202 };
1203 
1204 /* mcspi3 */
1205 static struct omap_hwmod omap34xx_mcspi3 = {
1206 	.name		= "mcspi3",
1207 	.main_clk	= "mcspi3_fck",
1208 	.prcm		= {
1209 		.omap2 = {
1210 			.module_offs = CORE_MOD,
1211 			.idlest_reg_id = 1,
1212 			.idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1213 		},
1214 	},
1215 	.class		= &omap34xx_mcspi_class,
1216 };
1217 
1218 /* mcspi4 */
1219 static struct omap_hwmod omap34xx_mcspi4 = {
1220 	.name		= "mcspi4",
1221 	.main_clk	= "mcspi4_fck",
1222 	.prcm		= {
1223 		.omap2 = {
1224 			.module_offs = CORE_MOD,
1225 			.idlest_reg_id = 1,
1226 			.idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1227 		},
1228 	},
1229 	.class		= &omap34xx_mcspi_class,
1230 };
1231 
1232 /* usbhsotg */
1233 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1234 	.rev_offs	= 0x0400,
1235 	.sysc_offs	= 0x0404,
1236 	.syss_offs	= 0x0408,
1237 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1238 			  SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1239 			  SYSC_HAS_AUTOIDLE),
1240 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1241 			  MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1242 	.sysc_fields	= &omap_hwmod_sysc_type1,
1243 };
1244 
1245 static struct omap_hwmod_class usbotg_class = {
1246 	.name = "usbotg",
1247 	.sysc = &omap3xxx_usbhsotg_sysc,
1248 };
1249 
1250 /* usb_otg_hs */
1251 
1252 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1253 	.name		= "usb_otg_hs",
1254 	.main_clk	= "hsotgusb_ick",
1255 	.prcm		= {
1256 		.omap2 = {
1257 			.module_offs = CORE_MOD,
1258 			.idlest_reg_id = 1,
1259 			.idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1260 		},
1261 	},
1262 	.class		= &usbotg_class,
1263 
1264 	/*
1265 	 * Erratum ID: i479  idle_req / idle_ack mechanism potentially
1266 	 * broken when autoidle is enabled
1267 	 * workaround is to disable the autoidle bit at module level.
1268 	 *
1269 	 * Enabling the device in any other MIDLEMODE setting but force-idle
1270 	 * causes core_pwrdm not enter idle states at least on OMAP3630.
1271 	 * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY
1272 	 * signal when MIDLEMODE is set to force-idle.
1273 	 */
1274 	.flags		= HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE |
1275 			  HWMOD_FORCE_MSTANDBY | HWMOD_RECONFIG_IO_CHAIN,
1276 };
1277 
1278 /* usb_otg_hs */
1279 
1280 static struct omap_hwmod_class am35xx_usbotg_class = {
1281 	.name = "am35xx_usbotg",
1282 };
1283 
1284 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1285 	.name		= "am35x_otg_hs",
1286 	.main_clk	= "hsotgusb_fck",
1287 	.class		= &am35xx_usbotg_class,
1288 	.flags		= HWMOD_NO_IDLEST,
1289 };
1290 
1291 /* MMC/SD/SDIO common */
1292 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1293 	.rev_offs	= 0x1fc,
1294 	.sysc_offs	= 0x10,
1295 	.syss_offs	= 0x14,
1296 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1297 			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1298 			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1299 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1300 	.sysc_fields    = &omap_hwmod_sysc_type1,
1301 };
1302 
1303 static struct omap_hwmod_class omap34xx_mmc_class = {
1304 	.name = "mmc",
1305 	.sysc = &omap34xx_mmc_sysc,
1306 };
1307 
1308 /* MMC/SD/SDIO1 */
1309 
1310 
1311 
1312 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1313 	{ .role = "dbck", .clk = "omap_32k_fck", },
1314 };
1315 
1316 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1317 	.flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1318 };
1319 
1320 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1321 static struct omap_hsmmc_dev_attr mmc1_pre_es3_dev_attr = {
1322 	.flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1323 		  OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1324 };
1325 
1326 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1327 	.name		= "mmc1",
1328 	.opt_clks	= omap34xx_mmc1_opt_clks,
1329 	.opt_clks_cnt	= ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1330 	.main_clk	= "mmchs1_fck",
1331 	.prcm		= {
1332 		.omap2 = {
1333 			.module_offs = CORE_MOD,
1334 			.idlest_reg_id = 1,
1335 			.idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1336 		},
1337 	},
1338 	.dev_attr	= &mmc1_pre_es3_dev_attr,
1339 	.class		= &omap34xx_mmc_class,
1340 };
1341 
1342 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1343 	.name		= "mmc1",
1344 	.opt_clks	= omap34xx_mmc1_opt_clks,
1345 	.opt_clks_cnt	= ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1346 	.main_clk	= "mmchs1_fck",
1347 	.prcm		= {
1348 		.omap2 = {
1349 			.module_offs = CORE_MOD,
1350 			.idlest_reg_id = 1,
1351 			.idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1352 		},
1353 	},
1354 	.dev_attr	= &mmc1_dev_attr,
1355 	.class		= &omap34xx_mmc_class,
1356 };
1357 
1358 /* MMC/SD/SDIO2 */
1359 
1360 
1361 
1362 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1363 	{ .role = "dbck", .clk = "omap_32k_fck", },
1364 };
1365 
1366 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1367 static struct omap_hsmmc_dev_attr mmc2_pre_es3_dev_attr = {
1368 	.flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1369 };
1370 
1371 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1372 	.name		= "mmc2",
1373 	.opt_clks	= omap34xx_mmc2_opt_clks,
1374 	.opt_clks_cnt	= ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1375 	.main_clk	= "mmchs2_fck",
1376 	.prcm		= {
1377 		.omap2 = {
1378 			.module_offs = CORE_MOD,
1379 			.idlest_reg_id = 1,
1380 			.idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1381 		},
1382 	},
1383 	.dev_attr	= &mmc2_pre_es3_dev_attr,
1384 	.class		= &omap34xx_mmc_class,
1385 };
1386 
1387 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1388 	.name		= "mmc2",
1389 	.opt_clks	= omap34xx_mmc2_opt_clks,
1390 	.opt_clks_cnt	= ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1391 	.main_clk	= "mmchs2_fck",
1392 	.prcm		= {
1393 		.omap2 = {
1394 			.module_offs = CORE_MOD,
1395 			.idlest_reg_id = 1,
1396 			.idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1397 		},
1398 	},
1399 	.class		= &omap34xx_mmc_class,
1400 };
1401 
1402 /* MMC/SD/SDIO3 */
1403 
1404 
1405 
1406 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1407 	{ .role = "dbck", .clk = "omap_32k_fck", },
1408 };
1409 
1410 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1411 	.name		= "mmc3",
1412 	.opt_clks	= omap34xx_mmc3_opt_clks,
1413 	.opt_clks_cnt	= ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1414 	.main_clk	= "mmchs3_fck",
1415 	.prcm		= {
1416 		.omap2 = {
1417 			.module_offs = CORE_MOD,
1418 			.idlest_reg_id = 1,
1419 			.idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1420 		},
1421 	},
1422 	.class		= &omap34xx_mmc_class,
1423 };
1424 
1425 /*
1426  * 'usb_host_hs' class
1427  * high-speed multi-port usb host controller
1428  */
1429 
1430 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1431 	.rev_offs	= 0x0000,
1432 	.sysc_offs	= 0x0010,
1433 	.syss_offs	= 0x0014,
1434 	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1435 			   SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1436 			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1437 			   SYSS_HAS_RESET_STATUS),
1438 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1439 			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1440 	.sysc_fields	= &omap_hwmod_sysc_type1,
1441 };
1442 
1443 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1444 	.name = "usb_host_hs",
1445 	.sysc = &omap3xxx_usb_host_hs_sysc,
1446 };
1447 
1448 
1449 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1450 	.name		= "usb_host_hs",
1451 	.class		= &omap3xxx_usb_host_hs_hwmod_class,
1452 	.clkdm_name	= "usbhost_clkdm",
1453 	.main_clk	= "usbhost_48m_fck",
1454 	.prcm = {
1455 		.omap2 = {
1456 			.module_offs = OMAP3430ES2_USBHOST_MOD,
1457 			.idlest_reg_id = 1,
1458 			.idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1459 		},
1460 	},
1461 
1462 	/*
1463 	 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1464 	 * id: i660
1465 	 *
1466 	 * Description:
1467 	 * In the following configuration :
1468 	 * - USBHOST module is set to smart-idle mode
1469 	 * - PRCM asserts idle_req to the USBHOST module ( This typically
1470 	 *   happens when the system is going to a low power mode : all ports
1471 	 *   have been suspended, the master part of the USBHOST module has
1472 	 *   entered the standby state, and SW has cut the functional clocks)
1473 	 * - an USBHOST interrupt occurs before the module is able to answer
1474 	 *   idle_ack, typically a remote wakeup IRQ.
1475 	 * Then the USB HOST module will enter a deadlock situation where it
1476 	 * is no more accessible nor functional.
1477 	 *
1478 	 * Workaround:
1479 	 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1480 	 */
1481 
1482 	/*
1483 	 * Errata: USB host EHCI may stall when entering smart-standby mode
1484 	 * Id: i571
1485 	 *
1486 	 * Description:
1487 	 * When the USBHOST module is set to smart-standby mode, and when it is
1488 	 * ready to enter the standby state (i.e. all ports are suspended and
1489 	 * all attached devices are in suspend mode), then it can wrongly assert
1490 	 * the Mstandby signal too early while there are still some residual OCP
1491 	 * transactions ongoing. If this condition occurs, the internal state
1492 	 * machine may go to an undefined state and the USB link may be stuck
1493 	 * upon the next resume.
1494 	 *
1495 	 * Workaround:
1496 	 * Don't use smart standby; use only force standby,
1497 	 * hence HWMOD_SWSUP_MSTANDBY
1498 	 */
1499 
1500 	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1501 };
1502 
1503 /*
1504  * 'usb_tll_hs' class
1505  * usb_tll_hs module is the adapter on the usb_host_hs ports
1506  */
1507 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
1508 	.rev_offs	= 0x0000,
1509 	.sysc_offs	= 0x0010,
1510 	.syss_offs	= 0x0014,
1511 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1512 			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1513 			   SYSC_HAS_AUTOIDLE),
1514 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1515 	.sysc_fields	= &omap_hwmod_sysc_type1,
1516 };
1517 
1518 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
1519 	.name = "usb_tll_hs",
1520 	.sysc = &omap3xxx_usb_tll_hs_sysc,
1521 };
1522 
1523 
1524 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
1525 	.name		= "usb_tll_hs",
1526 	.class		= &omap3xxx_usb_tll_hs_hwmod_class,
1527 	.clkdm_name	= "core_l4_clkdm",
1528 	.main_clk	= "usbtll_fck",
1529 	.prcm = {
1530 		.omap2 = {
1531 			.module_offs = CORE_MOD,
1532 			.idlest_reg_id = 3,
1533 			.idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
1534 		},
1535 	},
1536 };
1537 
1538 static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
1539 	.name		= "hdq1w",
1540 	.main_clk	= "hdq_fck",
1541 	.prcm		= {
1542 		.omap2 = {
1543 			.module_offs = CORE_MOD,
1544 			.idlest_reg_id = 1,
1545 			.idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
1546 		},
1547 	},
1548 	.class		= &omap2_hdq1w_class,
1549 };
1550 
1551 /* SAD2D */
1552 static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = {
1553 	{ .name = "rst_modem_pwron_sw", .rst_shift = 0 },
1554 	{ .name = "rst_modem_sw", .rst_shift = 1 },
1555 };
1556 
1557 static struct omap_hwmod_class omap3xxx_sad2d_class = {
1558 	.name			= "sad2d",
1559 };
1560 
1561 static struct omap_hwmod omap3xxx_sad2d_hwmod = {
1562 	.name		= "sad2d",
1563 	.rst_lines	= omap3xxx_sad2d_resets,
1564 	.rst_lines_cnt	= ARRAY_SIZE(omap3xxx_sad2d_resets),
1565 	.main_clk	= "sad2d_ick",
1566 	.prcm		= {
1567 		.omap2 = {
1568 			.module_offs = CORE_MOD,
1569 			.idlest_reg_id = 1,
1570 			.idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT,
1571 		},
1572 	},
1573 	.class		= &omap3xxx_sad2d_class,
1574 };
1575 
1576 /*
1577  * '32K sync counter' class
1578  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
1579  */
1580 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
1581 	.rev_offs	= 0x0000,
1582 	.sysc_offs	= 0x0004,
1583 	.sysc_flags	= SYSC_HAS_SIDLEMODE,
1584 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO),
1585 	.sysc_fields	= &omap_hwmod_sysc_type1,
1586 };
1587 
1588 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
1589 	.name	= "counter",
1590 	.sysc	= &omap3xxx_counter_sysc,
1591 };
1592 
1593 static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
1594 	.name		= "counter_32k",
1595 	.class		= &omap3xxx_counter_hwmod_class,
1596 	.clkdm_name	= "wkup_clkdm",
1597 	.flags		= HWMOD_SWSUP_SIDLE,
1598 	.main_clk	= "wkup_32k_fck",
1599 	.prcm		= {
1600 		.omap2	= {
1601 			.module_offs = WKUP_MOD,
1602 			.idlest_reg_id = 1,
1603 			.idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
1604 		},
1605 	},
1606 };
1607 
1608 /*
1609  * 'gpmc' class
1610  * general purpose memory controller
1611  */
1612 
1613 static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
1614 	.rev_offs	= 0x0000,
1615 	.sysc_offs	= 0x0010,
1616 	.syss_offs	= 0x0014,
1617 	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1618 			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1619 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1620 	.sysc_fields	= &omap_hwmod_sysc_type1,
1621 };
1622 
1623 static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
1624 	.name	= "gpmc",
1625 	.sysc	= &omap3xxx_gpmc_sysc,
1626 };
1627 
1628 static struct omap_hwmod omap3xxx_gpmc_hwmod = {
1629 	.name		= "gpmc",
1630 	.class		= &omap3xxx_gpmc_hwmod_class,
1631 	.clkdm_name	= "core_l3_clkdm",
1632 	.main_clk	= "gpmc_fck",
1633 	/* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
1634 	.flags		= HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
1635 };
1636 
1637 /*
1638  * interfaces
1639  */
1640 
1641 /* L3 -> L4_CORE interface */
1642 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
1643 	.master	= &omap3xxx_l3_main_hwmod,
1644 	.slave	= &omap3xxx_l4_core_hwmod,
1645 	.user	= OCP_USER_MPU | OCP_USER_SDMA,
1646 };
1647 
1648 /* L3 -> L4_PER interface */
1649 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
1650 	.master = &omap3xxx_l3_main_hwmod,
1651 	.slave	= &omap3xxx_l4_per_hwmod,
1652 	.user	= OCP_USER_MPU | OCP_USER_SDMA,
1653 };
1654 
1655 
1656 /* MPU -> L3 interface */
1657 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
1658 	.master   = &omap3xxx_mpu_hwmod,
1659 	.slave    = &omap3xxx_l3_main_hwmod,
1660 	.user	= OCP_USER_MPU,
1661 };
1662 
1663 
1664 /* l3 -> debugss */
1665 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
1666 	.master		= &omap3xxx_l3_main_hwmod,
1667 	.slave		= &omap3xxx_debugss_hwmod,
1668 	.user		= OCP_USER_MPU,
1669 };
1670 
1671 /* DSS -> l3 */
1672 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
1673 	.master		= &omap3430es1_dss_core_hwmod,
1674 	.slave		= &omap3xxx_l3_main_hwmod,
1675 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1676 };
1677 
1678 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
1679 	.master		= &omap3xxx_dss_core_hwmod,
1680 	.slave		= &omap3xxx_l3_main_hwmod,
1681 	.fw = {
1682 		.omap2 = {
1683 			.l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
1684 			.flags	= OMAP_FIREWALL_L3,
1685 		},
1686 	},
1687 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1688 };
1689 
1690 /* l3_core -> usbhsotg interface */
1691 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
1692 	.master		= &omap3xxx_usbhsotg_hwmod,
1693 	.slave		= &omap3xxx_l3_main_hwmod,
1694 	.clk		= "core_l3_ick",
1695 	.user		= OCP_USER_MPU,
1696 };
1697 
1698 /* l3_core -> am35xx_usbhsotg interface */
1699 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
1700 	.master		= &am35xx_usbhsotg_hwmod,
1701 	.slave		= &omap3xxx_l3_main_hwmod,
1702 	.clk		= "hsotgusb_ick",
1703 	.user		= OCP_USER_MPU,
1704 };
1705 
1706 /* l3_core -> sad2d interface */
1707 static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = {
1708 	.master		= &omap3xxx_sad2d_hwmod,
1709 	.slave		= &omap3xxx_l3_main_hwmod,
1710 	.clk		= "core_l3_ick",
1711 	.user		= OCP_USER_MPU,
1712 };
1713 
1714 /* L4_CORE -> L4_WKUP interface */
1715 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
1716 	.master	= &omap3xxx_l4_core_hwmod,
1717 	.slave	= &omap3xxx_l4_wkup_hwmod,
1718 	.user	= OCP_USER_MPU | OCP_USER_SDMA,
1719 };
1720 
1721 /* L4 CORE -> MMC1 interface */
1722 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
1723 	.master		= &omap3xxx_l4_core_hwmod,
1724 	.slave		= &omap3xxx_pre_es3_mmc1_hwmod,
1725 	.clk		= "mmchs1_ick",
1726 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1727 	.flags		= OMAP_FIREWALL_L4,
1728 };
1729 
1730 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
1731 	.master		= &omap3xxx_l4_core_hwmod,
1732 	.slave		= &omap3xxx_es3plus_mmc1_hwmod,
1733 	.clk		= "mmchs1_ick",
1734 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1735 	.flags		= OMAP_FIREWALL_L4,
1736 };
1737 
1738 /* L4 CORE -> MMC2 interface */
1739 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
1740 	.master		= &omap3xxx_l4_core_hwmod,
1741 	.slave		= &omap3xxx_pre_es3_mmc2_hwmod,
1742 	.clk		= "mmchs2_ick",
1743 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1744 	.flags		= OMAP_FIREWALL_L4,
1745 };
1746 
1747 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
1748 	.master		= &omap3xxx_l4_core_hwmod,
1749 	.slave		= &omap3xxx_es3plus_mmc2_hwmod,
1750 	.clk		= "mmchs2_ick",
1751 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1752 	.flags		= OMAP_FIREWALL_L4,
1753 };
1754 
1755 /* L4 CORE -> MMC3 interface */
1756 
1757 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
1758 	.master		= &omap3xxx_l4_core_hwmod,
1759 	.slave		= &omap3xxx_mmc3_hwmod,
1760 	.clk		= "mmchs3_ick",
1761 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1762 	.flags		= OMAP_FIREWALL_L4,
1763 };
1764 
1765 /* L4 CORE -> UART1 interface */
1766 
1767 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
1768 	.master		= &omap3xxx_l4_core_hwmod,
1769 	.slave		= &omap3xxx_uart1_hwmod,
1770 	.clk		= "uart1_ick",
1771 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1772 };
1773 
1774 /* L4 CORE -> UART2 interface */
1775 
1776 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
1777 	.master		= &omap3xxx_l4_core_hwmod,
1778 	.slave		= &omap3xxx_uart2_hwmod,
1779 	.clk		= "uart2_ick",
1780 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1781 };
1782 
1783 /* L4 PER -> UART3 interface */
1784 
1785 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
1786 	.master		= &omap3xxx_l4_per_hwmod,
1787 	.slave		= &omap3xxx_uart3_hwmod,
1788 	.clk		= "uart3_ick",
1789 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1790 };
1791 
1792 /* L4 PER -> UART4 interface */
1793 
1794 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
1795 	.master		= &omap3xxx_l4_per_hwmod,
1796 	.slave		= &omap36xx_uart4_hwmod,
1797 	.clk		= "uart4_ick",
1798 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1799 };
1800 
1801 /* AM35xx: L4 CORE -> UART4 interface */
1802 
1803 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
1804 	.master		= &omap3xxx_l4_core_hwmod,
1805 	.slave		= &am35xx_uart4_hwmod,
1806 	.clk		= "uart4_ick",
1807 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1808 };
1809 
1810 /* L4 CORE -> I2C1 interface */
1811 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
1812 	.master		= &omap3xxx_l4_core_hwmod,
1813 	.slave		= &omap3xxx_i2c1_hwmod,
1814 	.clk		= "i2c1_ick",
1815 	.fw = {
1816 		.omap2 = {
1817 			.l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
1818 			.l4_prot_group = 7,
1819 			.flags	= OMAP_FIREWALL_L4,
1820 		},
1821 	},
1822 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1823 };
1824 
1825 /* L4 CORE -> I2C2 interface */
1826 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
1827 	.master		= &omap3xxx_l4_core_hwmod,
1828 	.slave		= &omap3xxx_i2c2_hwmod,
1829 	.clk		= "i2c2_ick",
1830 	.fw = {
1831 		.omap2 = {
1832 			.l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
1833 			.l4_prot_group = 7,
1834 			.flags = OMAP_FIREWALL_L4,
1835 		},
1836 	},
1837 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1838 };
1839 
1840 /* L4 CORE -> I2C3 interface */
1841 
1842 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
1843 	.master		= &omap3xxx_l4_core_hwmod,
1844 	.slave		= &omap3xxx_i2c3_hwmod,
1845 	.clk		= "i2c3_ick",
1846 	.fw = {
1847 		.omap2 = {
1848 			.l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
1849 			.l4_prot_group = 7,
1850 			.flags = OMAP_FIREWALL_L4,
1851 		},
1852 	},
1853 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1854 };
1855 
1856 /* L4 CORE -> SR1 interface */
1857 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
1858 	.master		= &omap3xxx_l4_core_hwmod,
1859 	.slave		= &omap34xx_sr1_hwmod,
1860 	.clk		= "sr_l4_ick",
1861 	.user		= OCP_USER_MPU,
1862 };
1863 
1864 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
1865 	.master		= &omap3xxx_l4_core_hwmod,
1866 	.slave		= &omap36xx_sr1_hwmod,
1867 	.clk		= "sr_l4_ick",
1868 	.user		= OCP_USER_MPU,
1869 };
1870 
1871 /* L4 CORE -> SR2 interface */
1872 
1873 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
1874 	.master		= &omap3xxx_l4_core_hwmod,
1875 	.slave		= &omap34xx_sr2_hwmod,
1876 	.clk		= "sr_l4_ick",
1877 	.user		= OCP_USER_MPU,
1878 };
1879 
1880 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
1881 	.master		= &omap3xxx_l4_core_hwmod,
1882 	.slave		= &omap36xx_sr2_hwmod,
1883 	.clk		= "sr_l4_ick",
1884 	.user		= OCP_USER_MPU,
1885 };
1886 
1887 
1888 /* l4_core -> usbhsotg  */
1889 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
1890 	.master		= &omap3xxx_l4_core_hwmod,
1891 	.slave		= &omap3xxx_usbhsotg_hwmod,
1892 	.clk		= "l4_ick",
1893 	.user		= OCP_USER_MPU,
1894 };
1895 
1896 
1897 /* l4_core -> usbhsotg  */
1898 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
1899 	.master		= &omap3xxx_l4_core_hwmod,
1900 	.slave		= &am35xx_usbhsotg_hwmod,
1901 	.clk		= "hsotgusb_ick",
1902 	.user		= OCP_USER_MPU,
1903 };
1904 
1905 /* L4_WKUP -> L4_SEC interface */
1906 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
1907 	.master = &omap3xxx_l4_wkup_hwmod,
1908 	.slave	= &omap3xxx_l4_sec_hwmod,
1909 	.user	= OCP_USER_MPU | OCP_USER_SDMA,
1910 };
1911 
1912 /* IVA2 <- L3 interface */
1913 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
1914 	.master		= &omap3xxx_l3_main_hwmod,
1915 	.slave		= &omap3xxx_iva_hwmod,
1916 	.clk		= "core_l3_ick",
1917 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1918 };
1919 
1920 
1921 /* l4_wkup -> timer1 */
1922 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
1923 	.master		= &omap3xxx_l4_wkup_hwmod,
1924 	.slave		= &omap3xxx_timer1_hwmod,
1925 	.clk		= "gpt1_ick",
1926 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1927 };
1928 
1929 
1930 /* l4_per -> timer2 */
1931 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
1932 	.master		= &omap3xxx_l4_per_hwmod,
1933 	.slave		= &omap3xxx_timer2_hwmod,
1934 	.clk		= "gpt2_ick",
1935 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1936 };
1937 
1938 
1939 /* l4_per -> timer3 */
1940 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
1941 	.master		= &omap3xxx_l4_per_hwmod,
1942 	.slave		= &omap3xxx_timer3_hwmod,
1943 	.clk		= "gpt3_ick",
1944 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1945 };
1946 
1947 
1948 /* l4_per -> timer4 */
1949 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
1950 	.master		= &omap3xxx_l4_per_hwmod,
1951 	.slave		= &omap3xxx_timer4_hwmod,
1952 	.clk		= "gpt4_ick",
1953 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1954 };
1955 
1956 
1957 /* l4_per -> timer5 */
1958 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
1959 	.master		= &omap3xxx_l4_per_hwmod,
1960 	.slave		= &omap3xxx_timer5_hwmod,
1961 	.clk		= "gpt5_ick",
1962 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1963 };
1964 
1965 
1966 /* l4_per -> timer6 */
1967 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
1968 	.master		= &omap3xxx_l4_per_hwmod,
1969 	.slave		= &omap3xxx_timer6_hwmod,
1970 	.clk		= "gpt6_ick",
1971 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1972 };
1973 
1974 
1975 /* l4_per -> timer7 */
1976 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
1977 	.master		= &omap3xxx_l4_per_hwmod,
1978 	.slave		= &omap3xxx_timer7_hwmod,
1979 	.clk		= "gpt7_ick",
1980 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1981 };
1982 
1983 
1984 /* l4_per -> timer8 */
1985 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
1986 	.master		= &omap3xxx_l4_per_hwmod,
1987 	.slave		= &omap3xxx_timer8_hwmod,
1988 	.clk		= "gpt8_ick",
1989 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1990 };
1991 
1992 
1993 /* l4_per -> timer9 */
1994 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
1995 	.master		= &omap3xxx_l4_per_hwmod,
1996 	.slave		= &omap3xxx_timer9_hwmod,
1997 	.clk		= "gpt9_ick",
1998 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1999 };
2000 
2001 /* l4_core -> timer10 */
2002 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2003 	.master		= &omap3xxx_l4_core_hwmod,
2004 	.slave		= &omap3xxx_timer10_hwmod,
2005 	.clk		= "gpt10_ick",
2006 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2007 };
2008 
2009 /* l4_core -> timer11 */
2010 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2011 	.master		= &omap3xxx_l4_core_hwmod,
2012 	.slave		= &omap3xxx_timer11_hwmod,
2013 	.clk		= "gpt11_ick",
2014 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2015 };
2016 
2017 
2018 /* l4_core -> timer12 */
2019 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2020 	.master		= &omap3xxx_l4_sec_hwmod,
2021 	.slave		= &omap3xxx_timer12_hwmod,
2022 	.clk		= "gpt12_ick",
2023 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2024 };
2025 
2026 /* l4_wkup -> wd_timer2 */
2027 
2028 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2029 	.master		= &omap3xxx_l4_wkup_hwmod,
2030 	.slave		= &omap3xxx_wd_timer2_hwmod,
2031 	.clk		= "wdt2_ick",
2032 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2033 };
2034 
2035 /* l4_core -> dss */
2036 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2037 	.master		= &omap3xxx_l4_core_hwmod,
2038 	.slave		= &omap3430es1_dss_core_hwmod,
2039 	.clk		= "dss_ick",
2040 	.fw = {
2041 		.omap2 = {
2042 			.l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2043 			.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2044 			.flags	= OMAP_FIREWALL_L4,
2045 		},
2046 	},
2047 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2048 };
2049 
2050 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2051 	.master		= &omap3xxx_l4_core_hwmod,
2052 	.slave		= &omap3xxx_dss_core_hwmod,
2053 	.clk		= "dss_ick",
2054 	.fw = {
2055 		.omap2 = {
2056 			.l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2057 			.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2058 			.flags	= OMAP_FIREWALL_L4,
2059 		},
2060 	},
2061 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2062 };
2063 
2064 /* l4_core -> dss_dispc */
2065 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2066 	.master		= &omap3xxx_l4_core_hwmod,
2067 	.slave		= &omap3xxx_dss_dispc_hwmod,
2068 	.clk		= "dss_ick",
2069 	.fw = {
2070 		.omap2 = {
2071 			.l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2072 			.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2073 			.flags	= OMAP_FIREWALL_L4,
2074 		},
2075 	},
2076 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2077 };
2078 
2079 /* l4_core -> dss_dsi1 */
2080 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2081 	.master		= &omap3xxx_l4_core_hwmod,
2082 	.slave		= &omap3xxx_dss_dsi1_hwmod,
2083 	.clk		= "dss_ick",
2084 	.fw = {
2085 		.omap2 = {
2086 			.l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2087 			.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2088 			.flags	= OMAP_FIREWALL_L4,
2089 		},
2090 	},
2091 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2092 };
2093 
2094 /* l4_core -> dss_rfbi */
2095 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2096 	.master		= &omap3xxx_l4_core_hwmod,
2097 	.slave		= &omap3xxx_dss_rfbi_hwmod,
2098 	.clk		= "dss_ick",
2099 	.fw = {
2100 		.omap2 = {
2101 			.l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2102 			.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2103 			.flags	= OMAP_FIREWALL_L4,
2104 		},
2105 	},
2106 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2107 };
2108 
2109 /* l4_core -> dss_venc */
2110 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2111 	.master		= &omap3xxx_l4_core_hwmod,
2112 	.slave		= &omap3xxx_dss_venc_hwmod,
2113 	.clk		= "dss_ick",
2114 	.fw = {
2115 		.omap2 = {
2116 			.l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2117 			.l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2118 			.flags	= OMAP_FIREWALL_L4,
2119 		},
2120 	},
2121 	.flags		= OCPIF_SWSUP_IDLE,
2122 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2123 };
2124 
2125 /* l4_wkup -> gpio1 */
2126 
2127 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2128 	.master		= &omap3xxx_l4_wkup_hwmod,
2129 	.slave		= &omap3xxx_gpio1_hwmod,
2130 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2131 };
2132 
2133 /* l4_per -> gpio2 */
2134 
2135 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2136 	.master		= &omap3xxx_l4_per_hwmod,
2137 	.slave		= &omap3xxx_gpio2_hwmod,
2138 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2139 };
2140 
2141 /* l4_per -> gpio3 */
2142 
2143 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2144 	.master		= &omap3xxx_l4_per_hwmod,
2145 	.slave		= &omap3xxx_gpio3_hwmod,
2146 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2147 };
2148 
2149 /*
2150  * 'mmu' class
2151  * The memory management unit performs virtual to physical address translation
2152  * for its requestors.
2153  */
2154 
2155 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2156 	.rev_offs	= 0x000,
2157 	.sysc_offs	= 0x010,
2158 	.syss_offs	= 0x014,
2159 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2160 			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2161 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2162 	.sysc_fields	= &omap_hwmod_sysc_type1,
2163 };
2164 
2165 static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
2166 	.name = "mmu",
2167 	.sysc = &mmu_sysc,
2168 };
2169 
2170 /* mmu isp */
2171 static struct omap_hwmod omap3xxx_mmu_isp_hwmod;
2172 
2173 /* l4_core -> mmu isp */
2174 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = {
2175 	.master		= &omap3xxx_l4_core_hwmod,
2176 	.slave		= &omap3xxx_mmu_isp_hwmod,
2177 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2178 };
2179 
2180 static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
2181 	.name		= "mmu_isp",
2182 	.class		= &omap3xxx_mmu_hwmod_class,
2183 	.main_clk	= "cam_ick",
2184 	.flags		= HWMOD_NO_IDLEST,
2185 };
2186 
2187 /* mmu iva */
2188 
2189 static struct omap_hwmod omap3xxx_mmu_iva_hwmod;
2190 
2191 static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = {
2192 	{ .name = "mmu", .rst_shift = 1, .st_shift = 9 },
2193 };
2194 
2195 /* l3_main -> iva mmu */
2196 static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = {
2197 	.master		= &omap3xxx_l3_main_hwmod,
2198 	.slave		= &omap3xxx_mmu_iva_hwmod,
2199 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2200 };
2201 
2202 static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
2203 	.name		= "mmu_iva",
2204 	.class		= &omap3xxx_mmu_hwmod_class,
2205 	.clkdm_name	= "iva2_clkdm",
2206 	.rst_lines	= omap3xxx_mmu_iva_resets,
2207 	.rst_lines_cnt	= ARRAY_SIZE(omap3xxx_mmu_iva_resets),
2208 	.main_clk	= "iva2_ck",
2209 	.prcm = {
2210 		.omap2 = {
2211 			.module_offs = OMAP3430_IVA2_MOD,
2212 			.idlest_reg_id = 1,
2213 			.idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
2214 		},
2215 	},
2216 	.flags		= HWMOD_NO_IDLEST,
2217 };
2218 
2219 /* l4_per -> gpio4 */
2220 
2221 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
2222 	.master		= &omap3xxx_l4_per_hwmod,
2223 	.slave		= &omap3xxx_gpio4_hwmod,
2224 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2225 };
2226 
2227 /* l4_per -> gpio5 */
2228 
2229 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
2230 	.master		= &omap3xxx_l4_per_hwmod,
2231 	.slave		= &omap3xxx_gpio5_hwmod,
2232 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2233 };
2234 
2235 /* l4_per -> gpio6 */
2236 
2237 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2238 	.master		= &omap3xxx_l4_per_hwmod,
2239 	.slave		= &omap3xxx_gpio6_hwmod,
2240 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2241 };
2242 
2243 /* dma_system -> L3 */
2244 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2245 	.master		= &omap3xxx_dma_system_hwmod,
2246 	.slave		= &omap3xxx_l3_main_hwmod,
2247 	.clk		= "core_l3_ick",
2248 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2249 };
2250 
2251 /* l4_cfg -> dma_system */
2252 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2253 	.master		= &omap3xxx_l4_core_hwmod,
2254 	.slave		= &omap3xxx_dma_system_hwmod,
2255 	.clk		= "core_l4_ick",
2256 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2257 };
2258 
2259 
2260 /* l4_core -> mcbsp1 */
2261 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2262 	.master		= &omap3xxx_l4_core_hwmod,
2263 	.slave		= &omap3xxx_mcbsp1_hwmod,
2264 	.clk		= "mcbsp1_ick",
2265 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2266 };
2267 
2268 
2269 /* l4_per -> mcbsp2 */
2270 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2271 	.master		= &omap3xxx_l4_per_hwmod,
2272 	.slave		= &omap3xxx_mcbsp2_hwmod,
2273 	.clk		= "mcbsp2_ick",
2274 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2275 };
2276 
2277 
2278 /* l4_per -> mcbsp3 */
2279 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2280 	.master		= &omap3xxx_l4_per_hwmod,
2281 	.slave		= &omap3xxx_mcbsp3_hwmod,
2282 	.clk		= "mcbsp3_ick",
2283 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2284 };
2285 
2286 
2287 /* l4_per -> mcbsp4 */
2288 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2289 	.master		= &omap3xxx_l4_per_hwmod,
2290 	.slave		= &omap3xxx_mcbsp4_hwmod,
2291 	.clk		= "mcbsp4_ick",
2292 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2293 };
2294 
2295 
2296 /* l4_core -> mcbsp5 */
2297 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2298 	.master		= &omap3xxx_l4_core_hwmod,
2299 	.slave		= &omap3xxx_mcbsp5_hwmod,
2300 	.clk		= "mcbsp5_ick",
2301 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2302 };
2303 
2304 
2305 /* l4_per -> mcbsp2_sidetone */
2306 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2307 	.master		= &omap3xxx_l4_per_hwmod,
2308 	.slave		= &omap3xxx_mcbsp2_sidetone_hwmod,
2309 	.clk		= "mcbsp2_ick",
2310 	.user		= OCP_USER_MPU,
2311 };
2312 
2313 
2314 /* l4_per -> mcbsp3_sidetone */
2315 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2316 	.master		= &omap3xxx_l4_per_hwmod,
2317 	.slave		= &omap3xxx_mcbsp3_sidetone_hwmod,
2318 	.clk		= "mcbsp3_ick",
2319 	.user		= OCP_USER_MPU,
2320 };
2321 
2322 /* l4_core -> mailbox */
2323 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2324 	.master		= &omap3xxx_l4_core_hwmod,
2325 	.slave		= &omap3xxx_mailbox_hwmod,
2326 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2327 };
2328 
2329 /* l4 core -> mcspi1 interface */
2330 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2331 	.master		= &omap3xxx_l4_core_hwmod,
2332 	.slave		= &omap34xx_mcspi1,
2333 	.clk		= "mcspi1_ick",
2334 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2335 };
2336 
2337 /* l4 core -> mcspi2 interface */
2338 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2339 	.master		= &omap3xxx_l4_core_hwmod,
2340 	.slave		= &omap34xx_mcspi2,
2341 	.clk		= "mcspi2_ick",
2342 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2343 };
2344 
2345 /* l4 core -> mcspi3 interface */
2346 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2347 	.master		= &omap3xxx_l4_core_hwmod,
2348 	.slave		= &omap34xx_mcspi3,
2349 	.clk		= "mcspi3_ick",
2350 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2351 };
2352 
2353 /* l4 core -> mcspi4 interface */
2354 
2355 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2356 	.master		= &omap3xxx_l4_core_hwmod,
2357 	.slave		= &omap34xx_mcspi4,
2358 	.clk		= "mcspi4_ick",
2359 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2360 };
2361 
2362 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
2363 	.master		= &omap3xxx_usb_host_hs_hwmod,
2364 	.slave		= &omap3xxx_l3_main_hwmod,
2365 	.clk		= "core_l3_ick",
2366 	.user		= OCP_USER_MPU,
2367 };
2368 
2369 
2370 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
2371 	.master		= &omap3xxx_l4_core_hwmod,
2372 	.slave		= &omap3xxx_usb_host_hs_hwmod,
2373 	.clk		= "usbhost_ick",
2374 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2375 };
2376 
2377 
2378 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
2379 	.master		= &omap3xxx_l4_core_hwmod,
2380 	.slave		= &omap3xxx_usb_tll_hs_hwmod,
2381 	.clk		= "usbtll_ick",
2382 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2383 };
2384 
2385 /* l4_core -> hdq1w interface */
2386 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
2387 	.master		= &omap3xxx_l4_core_hwmod,
2388 	.slave		= &omap3xxx_hdq1w_hwmod,
2389 	.clk		= "hdq_ick",
2390 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2391 	.flags		= OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
2392 };
2393 
2394 /* l4_wkup -> 32ksync_counter */
2395 
2396 
2397 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
2398 	.master		= &omap3xxx_l4_wkup_hwmod,
2399 	.slave		= &omap3xxx_counter_32k_hwmod,
2400 	.clk		= "omap_32ksync_ick",
2401 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2402 };
2403 
2404 /* am35xx has Davinci MDIO & EMAC */
2405 static struct omap_hwmod_class am35xx_mdio_class = {
2406 	.name = "davinci_mdio",
2407 };
2408 
2409 static struct omap_hwmod am35xx_mdio_hwmod = {
2410 	.name		= "davinci_mdio",
2411 	.class		= &am35xx_mdio_class,
2412 	.flags		= HWMOD_NO_IDLEST,
2413 };
2414 
2415 /*
2416  * XXX Should be connected to an IPSS hwmod, not the L3 directly;
2417  * but this will probably require some additional hwmod core support,
2418  * so is left as a future to-do item.
2419  */
2420 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
2421 	.master		= &am35xx_mdio_hwmod,
2422 	.slave		= &omap3xxx_l3_main_hwmod,
2423 	.clk		= "emac_fck",
2424 	.user		= OCP_USER_MPU,
2425 };
2426 
2427 /* l4_core -> davinci mdio  */
2428 /*
2429  * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
2430  * but this will probably require some additional hwmod core support,
2431  * so is left as a future to-do item.
2432  */
2433 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
2434 	.master		= &omap3xxx_l4_core_hwmod,
2435 	.slave		= &am35xx_mdio_hwmod,
2436 	.clk		= "emac_fck",
2437 	.user		= OCP_USER_MPU,
2438 };
2439 
2440 static struct omap_hwmod_class am35xx_emac_class = {
2441 	.name = "davinci_emac",
2442 };
2443 
2444 static struct omap_hwmod am35xx_emac_hwmod = {
2445 	.name		= "davinci_emac",
2446 	.class		= &am35xx_emac_class,
2447 	/*
2448 	 * According to Mark Greer, the MPU will not return from WFI
2449 	 * when the EMAC signals an interrupt.
2450 	 * http://www.spinics.net/lists/arm-kernel/msg174734.html
2451 	 */
2452 	.flags		= (HWMOD_NO_IDLEST | HWMOD_BLOCK_WFI),
2453 };
2454 
2455 /* l3_core -> davinci emac interface */
2456 /*
2457  * XXX Should be connected to an IPSS hwmod, not the L3 directly;
2458  * but this will probably require some additional hwmod core support,
2459  * so is left as a future to-do item.
2460  */
2461 static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
2462 	.master		= &am35xx_emac_hwmod,
2463 	.slave		= &omap3xxx_l3_main_hwmod,
2464 	.clk		= "emac_ick",
2465 	.user		= OCP_USER_MPU,
2466 };
2467 
2468 /* l4_core -> davinci emac  */
2469 /*
2470  * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
2471  * but this will probably require some additional hwmod core support,
2472  * so is left as a future to-do item.
2473  */
2474 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
2475 	.master		= &omap3xxx_l4_core_hwmod,
2476 	.slave		= &am35xx_emac_hwmod,
2477 	.clk		= "emac_ick",
2478 	.user		= OCP_USER_MPU,
2479 };
2480 
2481 static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
2482 	.master		= &omap3xxx_l3_main_hwmod,
2483 	.slave		= &omap3xxx_gpmc_hwmod,
2484 	.clk		= "core_l3_ick",
2485 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2486 };
2487 
2488 /* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */
2489 static struct omap_hwmod_class_sysconfig omap3_sham_sysc = {
2490 	.rev_offs	= 0x5c,
2491 	.sysc_offs	= 0x60,
2492 	.syss_offs	= 0x64,
2493 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2494 			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2495 	.sysc_fields	= &omap3_sham_sysc_fields,
2496 };
2497 
2498 static struct omap_hwmod_class omap3xxx_sham_class = {
2499 	.name	= "sham",
2500 	.sysc	= &omap3_sham_sysc,
2501 };
2502 
2503 
2504 
2505 static struct omap_hwmod omap3xxx_sham_hwmod = {
2506 	.name		= "sham",
2507 	.main_clk	= "sha12_ick",
2508 	.prcm		= {
2509 		.omap2 = {
2510 			.module_offs = CORE_MOD,
2511 			.idlest_reg_id = 1,
2512 			.idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT,
2513 		},
2514 	},
2515 	.class		= &omap3xxx_sham_class,
2516 };
2517 
2518 
2519 static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
2520 	.master		= &omap3xxx_l4_core_hwmod,
2521 	.slave		= &omap3xxx_sham_hwmod,
2522 	.clk		= "sha12_ick",
2523 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2524 };
2525 
2526 /* l4_core -> AES */
2527 static struct omap_hwmod_class_sysconfig omap3_aes_sysc = {
2528 	.rev_offs	= 0x44,
2529 	.sysc_offs	= 0x48,
2530 	.syss_offs	= 0x4c,
2531 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2532 			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2533 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2534 	.sysc_fields	= &omap3xxx_aes_sysc_fields,
2535 };
2536 
2537 static struct omap_hwmod_class omap3xxx_aes_class = {
2538 	.name	= "aes",
2539 	.sysc	= &omap3_aes_sysc,
2540 };
2541 
2542 
2543 static struct omap_hwmod omap3xxx_aes_hwmod = {
2544 	.name		= "aes",
2545 	.main_clk	= "aes2_ick",
2546 	.prcm		= {
2547 		.omap2 = {
2548 			.module_offs = CORE_MOD,
2549 			.idlest_reg_id = 1,
2550 			.idlest_idle_bit = OMAP3430_ST_AES2_SHIFT,
2551 		},
2552 	},
2553 	.class		= &omap3xxx_aes_class,
2554 };
2555 
2556 
2557 static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = {
2558 	.master		= &omap3xxx_l4_core_hwmod,
2559 	.slave		= &omap3xxx_aes_hwmod,
2560 	.clk		= "aes2_ick",
2561 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2562 };
2563 
2564 /*
2565  * 'ssi' class
2566  * synchronous serial interface (multichannel and full-duplex serial if)
2567  */
2568 
2569 static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = {
2570 	.rev_offs	= 0x0000,
2571 	.sysc_offs	= 0x0010,
2572 	.syss_offs	= 0x0014,
2573 	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_MIDLEMODE |
2574 			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2575 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2576 	.sysc_fields	= &omap_hwmod_sysc_type1,
2577 };
2578 
2579 static struct omap_hwmod_class omap3xxx_ssi_hwmod_class = {
2580 	.name	= "ssi",
2581 	.sysc	= &omap34xx_ssi_sysc,
2582 };
2583 
2584 static struct omap_hwmod omap3xxx_ssi_hwmod = {
2585 	.name		= "ssi",
2586 	.class		= &omap3xxx_ssi_hwmod_class,
2587 	.clkdm_name	= "core_l4_clkdm",
2588 	.main_clk	= "ssi_ssr_fck",
2589 	.prcm		= {
2590 		.omap2 = {
2591 			.module_offs		= CORE_MOD,
2592 			.idlest_reg_id		= 1,
2593 			.idlest_idle_bit	= OMAP3430ES2_ST_SSI_IDLE_SHIFT,
2594 		},
2595 	},
2596 };
2597 
2598 /* L4 CORE -> SSI */
2599 static struct omap_hwmod_ocp_if omap3xxx_l4_core__ssi = {
2600 	.master		= &omap3xxx_l4_core_hwmod,
2601 	.slave		= &omap3xxx_ssi_hwmod,
2602 	.clk		= "ssi_ick",
2603 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2604 };
2605 
2606 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
2607 	&omap3xxx_l3_main__l4_core,
2608 	&omap3xxx_l3_main__l4_per,
2609 	&omap3xxx_mpu__l3_main,
2610 	&omap3xxx_l3_main__l4_debugss,
2611 	&omap3xxx_l4_core__l4_wkup,
2612 	&omap3xxx_l4_core__mmc3,
2613 	&omap3_l4_core__uart1,
2614 	&omap3_l4_core__uart2,
2615 	&omap3_l4_per__uart3,
2616 	&omap3_l4_core__i2c1,
2617 	&omap3_l4_core__i2c2,
2618 	&omap3_l4_core__i2c3,
2619 	&omap3xxx_l4_wkup__l4_sec,
2620 	&omap3xxx_l4_wkup__timer1,
2621 	&omap3xxx_l4_per__timer2,
2622 	&omap3xxx_l4_per__timer3,
2623 	&omap3xxx_l4_per__timer4,
2624 	&omap3xxx_l4_per__timer5,
2625 	&omap3xxx_l4_per__timer6,
2626 	&omap3xxx_l4_per__timer7,
2627 	&omap3xxx_l4_per__timer8,
2628 	&omap3xxx_l4_per__timer9,
2629 	&omap3xxx_l4_core__timer10,
2630 	&omap3xxx_l4_core__timer11,
2631 	&omap3xxx_l4_wkup__wd_timer2,
2632 	&omap3xxx_l4_wkup__gpio1,
2633 	&omap3xxx_l4_per__gpio2,
2634 	&omap3xxx_l4_per__gpio3,
2635 	&omap3xxx_l4_per__gpio4,
2636 	&omap3xxx_l4_per__gpio5,
2637 	&omap3xxx_l4_per__gpio6,
2638 	&omap3xxx_dma_system__l3,
2639 	&omap3xxx_l4_core__dma_system,
2640 	&omap3xxx_l4_core__mcbsp1,
2641 	&omap3xxx_l4_per__mcbsp2,
2642 	&omap3xxx_l4_per__mcbsp3,
2643 	&omap3xxx_l4_per__mcbsp4,
2644 	&omap3xxx_l4_core__mcbsp5,
2645 	&omap3xxx_l4_per__mcbsp2_sidetone,
2646 	&omap3xxx_l4_per__mcbsp3_sidetone,
2647 	&omap34xx_l4_core__mcspi1,
2648 	&omap34xx_l4_core__mcspi2,
2649 	&omap34xx_l4_core__mcspi3,
2650 	&omap34xx_l4_core__mcspi4,
2651 	&omap3xxx_l4_wkup__counter_32k,
2652 	&omap3xxx_l3_main__gpmc,
2653 	NULL,
2654 };
2655 
2656 /* GP-only hwmod links */
2657 static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = {
2658 	&omap3xxx_l4_sec__timer12,
2659 	NULL,
2660 };
2661 
2662 static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = {
2663 	&omap3xxx_l4_sec__timer12,
2664 	NULL,
2665 };
2666 
2667 static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = {
2668 	&omap3xxx_l4_sec__timer12,
2669 	NULL,
2670 };
2671 
2672 /* crypto hwmod links */
2673 static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = {
2674 	&omap3xxx_l4_core__sham,
2675 	NULL,
2676 };
2677 
2678 static struct omap_hwmod_ocp_if *omap34xx_aes_hwmod_ocp_ifs[] __initdata = {
2679 	&omap3xxx_l4_core__aes,
2680 	NULL,
2681 };
2682 
2683 static struct omap_hwmod_ocp_if *omap36xx_sham_hwmod_ocp_ifs[] __initdata = {
2684 	&omap3xxx_l4_core__sham,
2685 	NULL
2686 };
2687 
2688 static struct omap_hwmod_ocp_if *omap36xx_aes_hwmod_ocp_ifs[] __initdata = {
2689 	&omap3xxx_l4_core__aes,
2690 	NULL
2691 };
2692 
2693 /*
2694  * Apparently the SHA/MD5 and AES accelerator IP blocks are
2695  * only present on some AM35xx chips, and no one knows which
2696  * ones.  See
2697  * http://www.spinics.net/lists/arm-kernel/msg215466.html So
2698  * if you need these IP blocks on an AM35xx, try uncommenting
2699  * the following lines.
2700  */
2701 static struct omap_hwmod_ocp_if *am35xx_sham_hwmod_ocp_ifs[] __initdata = {
2702 	/* &omap3xxx_l4_core__sham, */
2703 	NULL
2704 };
2705 
2706 static struct omap_hwmod_ocp_if *am35xx_aes_hwmod_ocp_ifs[] __initdata = {
2707 	/* &omap3xxx_l4_core__aes, */
2708 	NULL,
2709 };
2710 
2711 /* 3430ES1-only hwmod links */
2712 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
2713 	&omap3430es1_dss__l3,
2714 	&omap3430es1_l4_core__dss,
2715 	NULL,
2716 };
2717 
2718 /* 3430ES2+-only hwmod links */
2719 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
2720 	&omap3xxx_dss__l3,
2721 	&omap3xxx_l4_core__dss,
2722 	&omap3xxx_usbhsotg__l3,
2723 	&omap3xxx_l4_core__usbhsotg,
2724 	&omap3xxx_usb_host_hs__l3_main_2,
2725 	&omap3xxx_l4_core__usb_host_hs,
2726 	&omap3xxx_l4_core__usb_tll_hs,
2727 	NULL,
2728 };
2729 
2730 /* <= 3430ES3-only hwmod links */
2731 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
2732 	&omap3xxx_l4_core__pre_es3_mmc1,
2733 	&omap3xxx_l4_core__pre_es3_mmc2,
2734 	NULL,
2735 };
2736 
2737 /* 3430ES3+-only hwmod links */
2738 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
2739 	&omap3xxx_l4_core__es3plus_mmc1,
2740 	&omap3xxx_l4_core__es3plus_mmc2,
2741 	NULL,
2742 };
2743 
2744 /* 34xx-only hwmod links (all ES revisions) */
2745 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
2746 	&omap3xxx_l3__iva,
2747 	&omap34xx_l4_core__sr1,
2748 	&omap34xx_l4_core__sr2,
2749 	&omap3xxx_l4_core__mailbox,
2750 	&omap3xxx_l4_core__hdq1w,
2751 	&omap3xxx_sad2d__l3,
2752 	&omap3xxx_l4_core__mmu_isp,
2753 	&omap3xxx_l3_main__mmu_iva,
2754 	&omap3xxx_l4_core__ssi,
2755 	NULL,
2756 };
2757 
2758 /* 36xx-only hwmod links (all ES revisions) */
2759 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
2760 	&omap3xxx_l3__iva,
2761 	&omap36xx_l4_per__uart4,
2762 	&omap3xxx_dss__l3,
2763 	&omap3xxx_l4_core__dss,
2764 	&omap36xx_l4_core__sr1,
2765 	&omap36xx_l4_core__sr2,
2766 	&omap3xxx_usbhsotg__l3,
2767 	&omap3xxx_l4_core__usbhsotg,
2768 	&omap3xxx_l4_core__mailbox,
2769 	&omap3xxx_usb_host_hs__l3_main_2,
2770 	&omap3xxx_l4_core__usb_host_hs,
2771 	&omap3xxx_l4_core__usb_tll_hs,
2772 	&omap3xxx_l4_core__es3plus_mmc1,
2773 	&omap3xxx_l4_core__es3plus_mmc2,
2774 	&omap3xxx_l4_core__hdq1w,
2775 	&omap3xxx_sad2d__l3,
2776 	&omap3xxx_l4_core__mmu_isp,
2777 	&omap3xxx_l3_main__mmu_iva,
2778 	&omap3xxx_l4_core__ssi,
2779 	NULL,
2780 };
2781 
2782 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
2783 	&omap3xxx_dss__l3,
2784 	&omap3xxx_l4_core__dss,
2785 	&am35xx_usbhsotg__l3,
2786 	&am35xx_l4_core__usbhsotg,
2787 	&am35xx_l4_core__uart4,
2788 	&omap3xxx_usb_host_hs__l3_main_2,
2789 	&omap3xxx_l4_core__usb_host_hs,
2790 	&omap3xxx_l4_core__usb_tll_hs,
2791 	&omap3xxx_l4_core__es3plus_mmc1,
2792 	&omap3xxx_l4_core__es3plus_mmc2,
2793 	&omap3xxx_l4_core__hdq1w,
2794 	&am35xx_mdio__l3,
2795 	&am35xx_l4_core__mdio,
2796 	&am35xx_emac__l3,
2797 	&am35xx_l4_core__emac,
2798 	NULL,
2799 };
2800 
2801 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
2802 	&omap3xxx_l4_core__dss_dispc,
2803 	&omap3xxx_l4_core__dss_dsi1,
2804 	&omap3xxx_l4_core__dss_rfbi,
2805 	&omap3xxx_l4_core__dss_venc,
2806 	NULL,
2807 };
2808 
2809 /**
2810  * omap3xxx_hwmod_is_hs_ip_block_usable - is a security IP block accessible?
2811  * @bus: struct device_node * for the top-level OMAP DT data
2812  * @dev_name: device name used in the DT file
2813  *
2814  * Determine whether a "secure" IP block @dev_name is usable by Linux.
2815  * There doesn't appear to be a 100% reliable way to determine this,
2816  * so we rely on heuristics.  If @bus is null, meaning there's no DT
2817  * data, then we only assume the IP block is accessible if the OMAP is
2818  * fused as a 'general-purpose' SoC.  If however DT data is present,
2819  * test to see if the IP block is described in the DT data and set to
2820  * 'status = "okay"'.  If so then we assume the ODM has configured the
2821  * OMAP firewalls to allow access to the IP block.
2822  *
2823  * Return: 0 if device named @dev_name is not likely to be accessible,
2824  * or 1 if it is likely to be accessible.
2825  */
2826 static bool __init omap3xxx_hwmod_is_hs_ip_block_usable(struct device_node *bus,
2827 							const char *dev_name)
2828 {
2829 	struct device_node *node;
2830 	bool available;
2831 
2832 	if (!bus)
2833 		return omap_type() == OMAP2_DEVICE_TYPE_GP;
2834 
2835 	node = of_get_child_by_name(bus, dev_name);
2836 	available = of_device_is_available(node);
2837 	of_node_put(node);
2838 
2839 	return available;
2840 }
2841 
2842 int __init omap3xxx_hwmod_init(void)
2843 {
2844 	int r;
2845 	struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL, **h_sham = NULL;
2846 	struct omap_hwmod_ocp_if **h_aes = NULL;
2847 	struct device_node *bus;
2848 	unsigned int rev;
2849 
2850 	omap_hwmod_init();
2851 
2852 	/* Register hwmod links common to all OMAP3 */
2853 	r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
2854 	if (r < 0)
2855 		return r;
2856 
2857 	rev = omap_rev();
2858 
2859 	/*
2860 	 * Register hwmod links common to individual OMAP3 families, all
2861 	 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
2862 	 * All possible revisions should be included in this conditional.
2863 	 */
2864 	if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
2865 	    rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
2866 	    rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
2867 		h = omap34xx_hwmod_ocp_ifs;
2868 		h_gp = omap34xx_gp_hwmod_ocp_ifs;
2869 		h_sham = omap34xx_sham_hwmod_ocp_ifs;
2870 		h_aes = omap34xx_aes_hwmod_ocp_ifs;
2871 	} else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
2872 		h = am35xx_hwmod_ocp_ifs;
2873 		h_gp = am35xx_gp_hwmod_ocp_ifs;
2874 		h_sham = am35xx_sham_hwmod_ocp_ifs;
2875 		h_aes = am35xx_aes_hwmod_ocp_ifs;
2876 	} else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
2877 		   rev == OMAP3630_REV_ES1_2) {
2878 		h = omap36xx_hwmod_ocp_ifs;
2879 		h_gp = omap36xx_gp_hwmod_ocp_ifs;
2880 		h_sham = omap36xx_sham_hwmod_ocp_ifs;
2881 		h_aes = omap36xx_aes_hwmod_ocp_ifs;
2882 	} else {
2883 		WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
2884 		return -EINVAL;
2885 	}
2886 
2887 	r = omap_hwmod_register_links(h);
2888 	if (r < 0)
2889 		return r;
2890 
2891 	/* Register GP-only hwmod links. */
2892 	if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) {
2893 		r = omap_hwmod_register_links(h_gp);
2894 		if (r < 0)
2895 			return r;
2896 	}
2897 
2898 	/*
2899 	 * Register crypto hwmod links only if they are not disabled in DT.
2900 	 * If DT information is missing, enable them only for GP devices.
2901 	 */
2902 
2903 	bus = of_find_node_by_name(NULL, "ocp");
2904 
2905 	if (h_sham && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "sham")) {
2906 		r = omap_hwmod_register_links(h_sham);
2907 		if (r < 0)
2908 			goto put_node;
2909 	}
2910 
2911 	if (h_aes && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "aes")) {
2912 		r = omap_hwmod_register_links(h_aes);
2913 		if (r < 0)
2914 			goto put_node;
2915 	}
2916 	of_node_put(bus);
2917 
2918 	/*
2919 	 * Register hwmod links specific to certain ES levels of a
2920 	 * particular family of silicon (e.g., 34xx ES1.0)
2921 	 */
2922 	h = NULL;
2923 	if (rev == OMAP3430_REV_ES1_0) {
2924 		h = omap3430es1_hwmod_ocp_ifs;
2925 	} else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
2926 		   rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
2927 		   rev == OMAP3430_REV_ES3_1_2) {
2928 		h = omap3430es2plus_hwmod_ocp_ifs;
2929 	}
2930 
2931 	if (h) {
2932 		r = omap_hwmod_register_links(h);
2933 		if (r < 0)
2934 			return r;
2935 	}
2936 
2937 	h = NULL;
2938 	if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
2939 	    rev == OMAP3430_REV_ES2_1) {
2940 		h = omap3430_pre_es3_hwmod_ocp_ifs;
2941 	} else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
2942 		   rev == OMAP3430_REV_ES3_1_2) {
2943 		h = omap3430_es3plus_hwmod_ocp_ifs;
2944 	}
2945 
2946 	if (h)
2947 		r = omap_hwmod_register_links(h);
2948 	if (r < 0)
2949 		return r;
2950 
2951 	/*
2952 	 * DSS code presumes that dss_core hwmod is handled first,
2953 	 * _before_ any other DSS related hwmods so register common
2954 	 * DSS hwmod links last to ensure that dss_core is already
2955 	 * registered.  Otherwise some change things may happen, for
2956 	 * ex. if dispc is handled before dss_core and DSS is enabled
2957 	 * in bootloader DISPC will be reset with outputs enabled
2958 	 * which sometimes leads to unrecoverable L3 error.  XXX The
2959 	 * long-term fix to this is to ensure hwmods are set up in
2960 	 * dependency order in the hwmod core code.
2961 	 */
2962 	r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
2963 
2964 	return r;
2965 
2966 put_node:
2967 	of_node_put(bus);
2968 	return r;
2969 }
2970