1 /* 2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips 3 * 4 * Copyright (C) 2009-2011 Nokia Corporation 5 * Copyright (C) 2012 Texas Instruments, Inc. 6 * Paul Walmsley 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * The data in this file should be completely autogeneratable from 13 * the TI hardware database or other technical documentation. 14 * 15 * XXX these should be marked initdata for multi-OMAP kernels 16 */ 17 18 #include <linux/i2c-omap.h> 19 #include <linux/power/smartreflex.h> 20 #include <linux/platform_data/gpio-omap.h> 21 #include <linux/platform_data/hsmmc-omap.h> 22 23 #include <linux/omap-dma.h> 24 #include "l3_3xxx.h" 25 #include "l4_3xxx.h" 26 #include <linux/platform_data/asoc-ti-mcbsp.h> 27 #include <linux/platform_data/spi-omap2-mcspi.h> 28 #include <plat/dmtimer.h> 29 30 #include "soc.h" 31 #include "omap_hwmod.h" 32 #include "omap_hwmod_common_data.h" 33 #include "prm-regbits-34xx.h" 34 #include "cm-regbits-34xx.h" 35 36 #include "i2c.h" 37 #include "wd_timer.h" 38 #include "serial.h" 39 40 /* 41 * OMAP3xxx hardware module integration data 42 * 43 * All of the data in this section should be autogeneratable from the 44 * TI hardware database or other technical documentation. Data that 45 * is driver-specific or driver-kernel integration-specific belongs 46 * elsewhere. 47 */ 48 49 #define AM35XX_IPSS_USBOTGSS_BASE 0x5C040000 50 51 /* 52 * IP blocks 53 */ 54 55 /* L3 */ 56 57 static struct omap_hwmod omap3xxx_l3_main_hwmod = { 58 .name = "l3_main", 59 .class = &l3_hwmod_class, 60 .flags = HWMOD_NO_IDLEST, 61 }; 62 63 /* L4 CORE */ 64 static struct omap_hwmod omap3xxx_l4_core_hwmod = { 65 .name = "l4_core", 66 .class = &l4_hwmod_class, 67 .flags = HWMOD_NO_IDLEST, 68 }; 69 70 /* L4 PER */ 71 static struct omap_hwmod omap3xxx_l4_per_hwmod = { 72 .name = "l4_per", 73 .class = &l4_hwmod_class, 74 .flags = HWMOD_NO_IDLEST, 75 }; 76 77 /* L4 WKUP */ 78 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = { 79 .name = "l4_wkup", 80 .class = &l4_hwmod_class, 81 .flags = HWMOD_NO_IDLEST, 82 }; 83 84 /* L4 SEC */ 85 static struct omap_hwmod omap3xxx_l4_sec_hwmod = { 86 .name = "l4_sec", 87 .class = &l4_hwmod_class, 88 .flags = HWMOD_NO_IDLEST, 89 }; 90 91 /* MPU */ 92 93 static struct omap_hwmod omap3xxx_mpu_hwmod = { 94 .name = "mpu", 95 .class = &mpu_hwmod_class, 96 .main_clk = "arm_fck", 97 }; 98 99 /* IVA2 (IVA2) */ 100 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = { 101 { .name = "logic", .rst_shift = 0, .st_shift = 8 }, 102 { .name = "seq0", .rst_shift = 1, .st_shift = 9 }, 103 { .name = "seq1", .rst_shift = 2, .st_shift = 10 }, 104 }; 105 106 static struct omap_hwmod omap3xxx_iva_hwmod = { 107 .name = "iva", 108 .class = &iva_hwmod_class, 109 .clkdm_name = "iva2_clkdm", 110 .rst_lines = omap3xxx_iva_resets, 111 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets), 112 .main_clk = "iva2_ck", 113 .prcm = { 114 .omap2 = { 115 .module_offs = OMAP3430_IVA2_MOD, 116 .prcm_reg_id = 1, 117 .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, 118 .idlest_reg_id = 1, 119 .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT, 120 }, 121 }, 122 }; 123 124 /* 125 * 'debugss' class 126 * debug and emulation sub system 127 */ 128 129 static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = { 130 .name = "debugss", 131 }; 132 133 /* debugss */ 134 static struct omap_hwmod omap3xxx_debugss_hwmod = { 135 .name = "debugss", 136 .class = &omap3xxx_debugss_hwmod_class, 137 .clkdm_name = "emu_clkdm", 138 .main_clk = "emu_src_ck", 139 .flags = HWMOD_NO_IDLEST, 140 }; 141 142 /* timer class */ 143 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { 144 .rev_offs = 0x0000, 145 .sysc_offs = 0x0010, 146 .syss_offs = 0x0014, 147 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | 148 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 149 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | 150 SYSS_HAS_RESET_STATUS), 151 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 152 .clockact = CLOCKACT_TEST_ICLK, 153 .sysc_fields = &omap_hwmod_sysc_type1, 154 }; 155 156 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { 157 .name = "timer", 158 .sysc = &omap3xxx_timer_sysc, 159 }; 160 161 /* secure timers dev attribute */ 162 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = { 163 .timer_capability = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE, 164 }; 165 166 /* always-on timers dev attribute */ 167 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { 168 .timer_capability = OMAP_TIMER_ALWON, 169 }; 170 171 /* pwm timers dev attribute */ 172 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { 173 .timer_capability = OMAP_TIMER_HAS_PWM, 174 }; 175 176 /* timers with DSP interrupt dev attribute */ 177 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = { 178 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ, 179 }; 180 181 /* pwm timers with DSP interrupt dev attribute */ 182 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = { 183 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM, 184 }; 185 186 /* timer1 */ 187 static struct omap_hwmod omap3xxx_timer1_hwmod = { 188 .name = "timer1", 189 .main_clk = "gpt1_fck", 190 .prcm = { 191 .omap2 = { 192 .prcm_reg_id = 1, 193 .module_bit = OMAP3430_EN_GPT1_SHIFT, 194 .module_offs = WKUP_MOD, 195 .idlest_reg_id = 1, 196 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT, 197 }, 198 }, 199 .dev_attr = &capability_alwon_dev_attr, 200 .class = &omap3xxx_timer_hwmod_class, 201 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 202 }; 203 204 /* timer2 */ 205 static struct omap_hwmod omap3xxx_timer2_hwmod = { 206 .name = "timer2", 207 .main_clk = "gpt2_fck", 208 .prcm = { 209 .omap2 = { 210 .prcm_reg_id = 1, 211 .module_bit = OMAP3430_EN_GPT2_SHIFT, 212 .module_offs = OMAP3430_PER_MOD, 213 .idlest_reg_id = 1, 214 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT, 215 }, 216 }, 217 .class = &omap3xxx_timer_hwmod_class, 218 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 219 }; 220 221 /* timer3 */ 222 static struct omap_hwmod omap3xxx_timer3_hwmod = { 223 .name = "timer3", 224 .main_clk = "gpt3_fck", 225 .prcm = { 226 .omap2 = { 227 .prcm_reg_id = 1, 228 .module_bit = OMAP3430_EN_GPT3_SHIFT, 229 .module_offs = OMAP3430_PER_MOD, 230 .idlest_reg_id = 1, 231 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT, 232 }, 233 }, 234 .class = &omap3xxx_timer_hwmod_class, 235 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 236 }; 237 238 /* timer4 */ 239 static struct omap_hwmod omap3xxx_timer4_hwmod = { 240 .name = "timer4", 241 .main_clk = "gpt4_fck", 242 .prcm = { 243 .omap2 = { 244 .prcm_reg_id = 1, 245 .module_bit = OMAP3430_EN_GPT4_SHIFT, 246 .module_offs = OMAP3430_PER_MOD, 247 .idlest_reg_id = 1, 248 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT, 249 }, 250 }, 251 .class = &omap3xxx_timer_hwmod_class, 252 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 253 }; 254 255 /* timer5 */ 256 static struct omap_hwmod omap3xxx_timer5_hwmod = { 257 .name = "timer5", 258 .main_clk = "gpt5_fck", 259 .prcm = { 260 .omap2 = { 261 .prcm_reg_id = 1, 262 .module_bit = OMAP3430_EN_GPT5_SHIFT, 263 .module_offs = OMAP3430_PER_MOD, 264 .idlest_reg_id = 1, 265 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT, 266 }, 267 }, 268 .dev_attr = &capability_dsp_dev_attr, 269 .class = &omap3xxx_timer_hwmod_class, 270 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 271 }; 272 273 /* timer6 */ 274 static struct omap_hwmod omap3xxx_timer6_hwmod = { 275 .name = "timer6", 276 .main_clk = "gpt6_fck", 277 .prcm = { 278 .omap2 = { 279 .prcm_reg_id = 1, 280 .module_bit = OMAP3430_EN_GPT6_SHIFT, 281 .module_offs = OMAP3430_PER_MOD, 282 .idlest_reg_id = 1, 283 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT, 284 }, 285 }, 286 .dev_attr = &capability_dsp_dev_attr, 287 .class = &omap3xxx_timer_hwmod_class, 288 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 289 }; 290 291 /* timer7 */ 292 static struct omap_hwmod omap3xxx_timer7_hwmod = { 293 .name = "timer7", 294 .main_clk = "gpt7_fck", 295 .prcm = { 296 .omap2 = { 297 .prcm_reg_id = 1, 298 .module_bit = OMAP3430_EN_GPT7_SHIFT, 299 .module_offs = OMAP3430_PER_MOD, 300 .idlest_reg_id = 1, 301 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT, 302 }, 303 }, 304 .dev_attr = &capability_dsp_dev_attr, 305 .class = &omap3xxx_timer_hwmod_class, 306 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 307 }; 308 309 /* timer8 */ 310 static struct omap_hwmod omap3xxx_timer8_hwmod = { 311 .name = "timer8", 312 .main_clk = "gpt8_fck", 313 .prcm = { 314 .omap2 = { 315 .prcm_reg_id = 1, 316 .module_bit = OMAP3430_EN_GPT8_SHIFT, 317 .module_offs = OMAP3430_PER_MOD, 318 .idlest_reg_id = 1, 319 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT, 320 }, 321 }, 322 .dev_attr = &capability_dsp_pwm_dev_attr, 323 .class = &omap3xxx_timer_hwmod_class, 324 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 325 }; 326 327 /* timer9 */ 328 static struct omap_hwmod omap3xxx_timer9_hwmod = { 329 .name = "timer9", 330 .main_clk = "gpt9_fck", 331 .prcm = { 332 .omap2 = { 333 .prcm_reg_id = 1, 334 .module_bit = OMAP3430_EN_GPT9_SHIFT, 335 .module_offs = OMAP3430_PER_MOD, 336 .idlest_reg_id = 1, 337 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT, 338 }, 339 }, 340 .dev_attr = &capability_pwm_dev_attr, 341 .class = &omap3xxx_timer_hwmod_class, 342 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 343 }; 344 345 /* timer10 */ 346 static struct omap_hwmod omap3xxx_timer10_hwmod = { 347 .name = "timer10", 348 .main_clk = "gpt10_fck", 349 .prcm = { 350 .omap2 = { 351 .prcm_reg_id = 1, 352 .module_bit = OMAP3430_EN_GPT10_SHIFT, 353 .module_offs = CORE_MOD, 354 .idlest_reg_id = 1, 355 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT, 356 }, 357 }, 358 .dev_attr = &capability_pwm_dev_attr, 359 .class = &omap3xxx_timer_hwmod_class, 360 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 361 }; 362 363 /* timer11 */ 364 static struct omap_hwmod omap3xxx_timer11_hwmod = { 365 .name = "timer11", 366 .main_clk = "gpt11_fck", 367 .prcm = { 368 .omap2 = { 369 .prcm_reg_id = 1, 370 .module_bit = OMAP3430_EN_GPT11_SHIFT, 371 .module_offs = CORE_MOD, 372 .idlest_reg_id = 1, 373 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT, 374 }, 375 }, 376 .dev_attr = &capability_pwm_dev_attr, 377 .class = &omap3xxx_timer_hwmod_class, 378 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 379 }; 380 381 /* timer12 */ 382 383 static struct omap_hwmod omap3xxx_timer12_hwmod = { 384 .name = "timer12", 385 .main_clk = "gpt12_fck", 386 .prcm = { 387 .omap2 = { 388 .prcm_reg_id = 1, 389 .module_bit = OMAP3430_EN_GPT12_SHIFT, 390 .module_offs = WKUP_MOD, 391 .idlest_reg_id = 1, 392 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT, 393 }, 394 }, 395 .dev_attr = &capability_secure_dev_attr, 396 .class = &omap3xxx_timer_hwmod_class, 397 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 398 }; 399 400 /* 401 * 'wd_timer' class 402 * 32-bit watchdog upward counter that generates a pulse on the reset pin on 403 * overflow condition 404 */ 405 406 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { 407 .rev_offs = 0x0000, 408 .sysc_offs = 0x0010, 409 .syss_offs = 0x0014, 410 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | 411 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 412 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | 413 SYSS_HAS_RESET_STATUS), 414 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 415 .sysc_fields = &omap_hwmod_sysc_type1, 416 }; 417 418 /* I2C common */ 419 static struct omap_hwmod_class_sysconfig i2c_sysc = { 420 .rev_offs = 0x00, 421 .sysc_offs = 0x20, 422 .syss_offs = 0x10, 423 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 424 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 425 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 426 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 427 .clockact = CLOCKACT_TEST_ICLK, 428 .sysc_fields = &omap_hwmod_sysc_type1, 429 }; 430 431 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { 432 .name = "wd_timer", 433 .sysc = &omap3xxx_wd_timer_sysc, 434 .pre_shutdown = &omap2_wd_timer_disable, 435 .reset = &omap2_wd_timer_reset, 436 }; 437 438 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { 439 .name = "wd_timer2", 440 .class = &omap3xxx_wd_timer_hwmod_class, 441 .main_clk = "wdt2_fck", 442 .prcm = { 443 .omap2 = { 444 .prcm_reg_id = 1, 445 .module_bit = OMAP3430_EN_WDT2_SHIFT, 446 .module_offs = WKUP_MOD, 447 .idlest_reg_id = 1, 448 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, 449 }, 450 }, 451 /* 452 * XXX: Use software supervised mode, HW supervised smartidle seems to 453 * block CORE power domain idle transitions. Maybe a HW bug in wdt2? 454 */ 455 .flags = HWMOD_SWSUP_SIDLE, 456 }; 457 458 /* UART1 */ 459 static struct omap_hwmod omap3xxx_uart1_hwmod = { 460 .name = "uart1", 461 .main_clk = "uart1_fck", 462 .flags = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE, 463 .prcm = { 464 .omap2 = { 465 .module_offs = CORE_MOD, 466 .prcm_reg_id = 1, 467 .module_bit = OMAP3430_EN_UART1_SHIFT, 468 .idlest_reg_id = 1, 469 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, 470 }, 471 }, 472 .class = &omap2_uart_class, 473 }; 474 475 /* UART2 */ 476 static struct omap_hwmod omap3xxx_uart2_hwmod = { 477 .name = "uart2", 478 .main_clk = "uart2_fck", 479 .flags = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE, 480 .prcm = { 481 .omap2 = { 482 .module_offs = CORE_MOD, 483 .prcm_reg_id = 1, 484 .module_bit = OMAP3430_EN_UART2_SHIFT, 485 .idlest_reg_id = 1, 486 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, 487 }, 488 }, 489 .class = &omap2_uart_class, 490 }; 491 492 /* UART3 */ 493 static struct omap_hwmod omap3xxx_uart3_hwmod = { 494 .name = "uart3", 495 .main_clk = "uart3_fck", 496 .flags = DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS | 497 HWMOD_SWSUP_SIDLE, 498 .prcm = { 499 .omap2 = { 500 .module_offs = OMAP3430_PER_MOD, 501 .prcm_reg_id = 1, 502 .module_bit = OMAP3430_EN_UART3_SHIFT, 503 .idlest_reg_id = 1, 504 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, 505 }, 506 }, 507 .class = &omap2_uart_class, 508 }; 509 510 /* UART4 */ 511 512 513 static struct omap_hwmod omap36xx_uart4_hwmod = { 514 .name = "uart4", 515 .main_clk = "uart4_fck", 516 .flags = DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE, 517 .prcm = { 518 .omap2 = { 519 .module_offs = OMAP3430_PER_MOD, 520 .prcm_reg_id = 1, 521 .module_bit = OMAP3630_EN_UART4_SHIFT, 522 .idlest_reg_id = 1, 523 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, 524 }, 525 }, 526 .class = &omap2_uart_class, 527 }; 528 529 530 531 /* 532 * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or 533 * uart2_fck being enabled. So we add uart1_fck as an optional clock, 534 * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET. This really 535 * should not be needed. The functional clock structure of the AM35xx 536 * UART4 is extremely unclear and opaque; it is unclear what the role 537 * of uart1/2_fck is for the UART4. Any clarification from either 538 * empirical testing or the AM3505/3517 hardware designers would be 539 * most welcome. 540 */ 541 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = { 542 { .role = "softreset_uart1_fck", .clk = "uart1_fck" }, 543 }; 544 545 static struct omap_hwmod am35xx_uart4_hwmod = { 546 .name = "uart4", 547 .main_clk = "uart4_fck", 548 .prcm = { 549 .omap2 = { 550 .module_offs = CORE_MOD, 551 .prcm_reg_id = 1, 552 .module_bit = AM35XX_EN_UART4_SHIFT, 553 .idlest_reg_id = 1, 554 .idlest_idle_bit = AM35XX_ST_UART4_SHIFT, 555 }, 556 }, 557 .opt_clks = am35xx_uart4_opt_clks, 558 .opt_clks_cnt = ARRAY_SIZE(am35xx_uart4_opt_clks), 559 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 560 .class = &omap2_uart_class, 561 }; 562 563 static struct omap_hwmod_class i2c_class = { 564 .name = "i2c", 565 .sysc = &i2c_sysc, 566 .rev = OMAP_I2C_IP_VERSION_1, 567 .reset = &omap_i2c_reset, 568 }; 569 570 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { 571 { .name = "dispc", .dma_req = 5 }, 572 { .name = "dsi1", .dma_req = 74 }, 573 { .dma_req = -1, }, 574 }; 575 576 /* dss */ 577 static struct omap_hwmod_opt_clk dss_opt_clks[] = { 578 /* 579 * The DSS HW needs all DSS clocks enabled during reset. The dss_core 580 * driver does not use these clocks. 581 */ 582 { .role = "sys_clk", .clk = "dss2_alwon_fck" }, 583 { .role = "tv_clk", .clk = "dss_tv_fck" }, 584 /* required only on OMAP3430 */ 585 { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, 586 }; 587 588 static struct omap_hwmod omap3430es1_dss_core_hwmod = { 589 .name = "dss_core", 590 .class = &omap2_dss_hwmod_class, 591 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ 592 .sdma_reqs = omap3xxx_dss_sdma_chs, 593 .prcm = { 594 .omap2 = { 595 .prcm_reg_id = 1, 596 .module_bit = OMAP3430_EN_DSS1_SHIFT, 597 .module_offs = OMAP3430_DSS_MOD, 598 .idlest_reg_id = 1, 599 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT, 600 }, 601 }, 602 .opt_clks = dss_opt_clks, 603 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), 604 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, 605 }; 606 607 static struct omap_hwmod omap3xxx_dss_core_hwmod = { 608 .name = "dss_core", 609 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 610 .class = &omap2_dss_hwmod_class, 611 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ 612 .sdma_reqs = omap3xxx_dss_sdma_chs, 613 .prcm = { 614 .omap2 = { 615 .prcm_reg_id = 1, 616 .module_bit = OMAP3430_EN_DSS1_SHIFT, 617 .module_offs = OMAP3430_DSS_MOD, 618 .idlest_reg_id = 1, 619 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT, 620 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT, 621 }, 622 }, 623 .opt_clks = dss_opt_clks, 624 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), 625 }; 626 627 /* 628 * 'dispc' class 629 * display controller 630 */ 631 632 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = { 633 .rev_offs = 0x0000, 634 .sysc_offs = 0x0010, 635 .syss_offs = 0x0014, 636 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | 637 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | 638 SYSC_HAS_ENAWAKEUP), 639 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 640 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 641 .sysc_fields = &omap_hwmod_sysc_type1, 642 }; 643 644 static struct omap_hwmod_class omap3_dispc_hwmod_class = { 645 .name = "dispc", 646 .sysc = &omap3_dispc_sysc, 647 }; 648 649 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { 650 .name = "dss_dispc", 651 .class = &omap3_dispc_hwmod_class, 652 .mpu_irqs = omap2_dispc_irqs, 653 .main_clk = "dss1_alwon_fck", 654 .prcm = { 655 .omap2 = { 656 .prcm_reg_id = 1, 657 .module_bit = OMAP3430_EN_DSS1_SHIFT, 658 .module_offs = OMAP3430_DSS_MOD, 659 }, 660 }, 661 .flags = HWMOD_NO_IDLEST, 662 .dev_attr = &omap2_3_dss_dispc_dev_attr, 663 }; 664 665 /* 666 * 'dsi' class 667 * display serial interface controller 668 */ 669 670 static struct omap_hwmod_class_sysconfig omap3xxx_dsi_sysc = { 671 .rev_offs = 0x0000, 672 .sysc_offs = 0x0010, 673 .syss_offs = 0x0014, 674 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | 675 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | 676 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 677 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 678 .sysc_fields = &omap_hwmod_sysc_type1, 679 }; 680 681 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = { 682 .name = "dsi", 683 .sysc = &omap3xxx_dsi_sysc, 684 }; 685 686 /* dss_dsi1 */ 687 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { 688 { .role = "sys_clk", .clk = "dss2_alwon_fck" }, 689 }; 690 691 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { 692 .name = "dss_dsi1", 693 .class = &omap3xxx_dsi_hwmod_class, 694 .main_clk = "dss1_alwon_fck", 695 .prcm = { 696 .omap2 = { 697 .prcm_reg_id = 1, 698 .module_bit = OMAP3430_EN_DSS1_SHIFT, 699 .module_offs = OMAP3430_DSS_MOD, 700 }, 701 }, 702 .opt_clks = dss_dsi1_opt_clks, 703 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), 704 .flags = HWMOD_NO_IDLEST, 705 }; 706 707 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { 708 { .role = "ick", .clk = "dss_ick" }, 709 }; 710 711 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { 712 .name = "dss_rfbi", 713 .class = &omap2_rfbi_hwmod_class, 714 .main_clk = "dss1_alwon_fck", 715 .prcm = { 716 .omap2 = { 717 .prcm_reg_id = 1, 718 .module_bit = OMAP3430_EN_DSS1_SHIFT, 719 .module_offs = OMAP3430_DSS_MOD, 720 }, 721 }, 722 .opt_clks = dss_rfbi_opt_clks, 723 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), 724 .flags = HWMOD_NO_IDLEST, 725 }; 726 727 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = { 728 /* required only on OMAP3430 */ 729 { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, 730 }; 731 732 static struct omap_hwmod omap3xxx_dss_venc_hwmod = { 733 .name = "dss_venc", 734 .class = &omap2_venc_hwmod_class, 735 .main_clk = "dss_tv_fck", 736 .prcm = { 737 .omap2 = { 738 .prcm_reg_id = 1, 739 .module_bit = OMAP3430_EN_DSS1_SHIFT, 740 .module_offs = OMAP3430_DSS_MOD, 741 }, 742 }, 743 .opt_clks = dss_venc_opt_clks, 744 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks), 745 .flags = HWMOD_NO_IDLEST, 746 }; 747 748 /* I2C1 */ 749 static struct omap_i2c_dev_attr i2c1_dev_attr = { 750 .fifo_depth = 8, /* bytes */ 751 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2, 752 }; 753 754 static struct omap_hwmod omap3xxx_i2c1_hwmod = { 755 .name = "i2c1", 756 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 757 .main_clk = "i2c1_fck", 758 .prcm = { 759 .omap2 = { 760 .module_offs = CORE_MOD, 761 .prcm_reg_id = 1, 762 .module_bit = OMAP3430_EN_I2C1_SHIFT, 763 .idlest_reg_id = 1, 764 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT, 765 }, 766 }, 767 .class = &i2c_class, 768 .dev_attr = &i2c1_dev_attr, 769 }; 770 771 /* I2C2 */ 772 static struct omap_i2c_dev_attr i2c2_dev_attr = { 773 .fifo_depth = 8, /* bytes */ 774 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2, 775 }; 776 777 static struct omap_hwmod omap3xxx_i2c2_hwmod = { 778 .name = "i2c2", 779 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 780 .main_clk = "i2c2_fck", 781 .prcm = { 782 .omap2 = { 783 .module_offs = CORE_MOD, 784 .prcm_reg_id = 1, 785 .module_bit = OMAP3430_EN_I2C2_SHIFT, 786 .idlest_reg_id = 1, 787 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT, 788 }, 789 }, 790 .class = &i2c_class, 791 .dev_attr = &i2c2_dev_attr, 792 }; 793 794 /* I2C3 */ 795 static struct omap_i2c_dev_attr i2c3_dev_attr = { 796 .fifo_depth = 64, /* bytes */ 797 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2, 798 }; 799 800 801 802 static struct omap_hwmod omap3xxx_i2c3_hwmod = { 803 .name = "i2c3", 804 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 805 .main_clk = "i2c3_fck", 806 .prcm = { 807 .omap2 = { 808 .module_offs = CORE_MOD, 809 .prcm_reg_id = 1, 810 .module_bit = OMAP3430_EN_I2C3_SHIFT, 811 .idlest_reg_id = 1, 812 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT, 813 }, 814 }, 815 .class = &i2c_class, 816 .dev_attr = &i2c3_dev_attr, 817 }; 818 819 /* 820 * 'gpio' class 821 * general purpose io module 822 */ 823 824 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = { 825 .rev_offs = 0x0000, 826 .sysc_offs = 0x0010, 827 .syss_offs = 0x0014, 828 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | 829 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | 830 SYSS_HAS_RESET_STATUS), 831 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 832 .sysc_fields = &omap_hwmod_sysc_type1, 833 }; 834 835 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = { 836 .name = "gpio", 837 .sysc = &omap3xxx_gpio_sysc, 838 .rev = 1, 839 }; 840 841 /* gpio_dev_attr */ 842 static struct omap_gpio_dev_attr gpio_dev_attr = { 843 .bank_width = 32, 844 .dbck_flag = true, 845 }; 846 847 /* gpio1 */ 848 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { 849 { .role = "dbclk", .clk = "gpio1_dbck", }, 850 }; 851 852 static struct omap_hwmod omap3xxx_gpio1_hwmod = { 853 .name = "gpio1", 854 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 855 .main_clk = "gpio1_ick", 856 .opt_clks = gpio1_opt_clks, 857 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), 858 .prcm = { 859 .omap2 = { 860 .prcm_reg_id = 1, 861 .module_bit = OMAP3430_EN_GPIO1_SHIFT, 862 .module_offs = WKUP_MOD, 863 .idlest_reg_id = 1, 864 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT, 865 }, 866 }, 867 .class = &omap3xxx_gpio_hwmod_class, 868 .dev_attr = &gpio_dev_attr, 869 }; 870 871 /* gpio2 */ 872 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { 873 { .role = "dbclk", .clk = "gpio2_dbck", }, 874 }; 875 876 static struct omap_hwmod omap3xxx_gpio2_hwmod = { 877 .name = "gpio2", 878 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 879 .main_clk = "gpio2_ick", 880 .opt_clks = gpio2_opt_clks, 881 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), 882 .prcm = { 883 .omap2 = { 884 .prcm_reg_id = 1, 885 .module_bit = OMAP3430_EN_GPIO2_SHIFT, 886 .module_offs = OMAP3430_PER_MOD, 887 .idlest_reg_id = 1, 888 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT, 889 }, 890 }, 891 .class = &omap3xxx_gpio_hwmod_class, 892 .dev_attr = &gpio_dev_attr, 893 }; 894 895 /* gpio3 */ 896 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { 897 { .role = "dbclk", .clk = "gpio3_dbck", }, 898 }; 899 900 static struct omap_hwmod omap3xxx_gpio3_hwmod = { 901 .name = "gpio3", 902 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 903 .main_clk = "gpio3_ick", 904 .opt_clks = gpio3_opt_clks, 905 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), 906 .prcm = { 907 .omap2 = { 908 .prcm_reg_id = 1, 909 .module_bit = OMAP3430_EN_GPIO3_SHIFT, 910 .module_offs = OMAP3430_PER_MOD, 911 .idlest_reg_id = 1, 912 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT, 913 }, 914 }, 915 .class = &omap3xxx_gpio_hwmod_class, 916 .dev_attr = &gpio_dev_attr, 917 }; 918 919 /* gpio4 */ 920 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { 921 { .role = "dbclk", .clk = "gpio4_dbck", }, 922 }; 923 924 static struct omap_hwmod omap3xxx_gpio4_hwmod = { 925 .name = "gpio4", 926 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 927 .main_clk = "gpio4_ick", 928 .opt_clks = gpio4_opt_clks, 929 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), 930 .prcm = { 931 .omap2 = { 932 .prcm_reg_id = 1, 933 .module_bit = OMAP3430_EN_GPIO4_SHIFT, 934 .module_offs = OMAP3430_PER_MOD, 935 .idlest_reg_id = 1, 936 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT, 937 }, 938 }, 939 .class = &omap3xxx_gpio_hwmod_class, 940 .dev_attr = &gpio_dev_attr, 941 }; 942 943 /* gpio5 */ 944 945 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { 946 { .role = "dbclk", .clk = "gpio5_dbck", }, 947 }; 948 949 static struct omap_hwmod omap3xxx_gpio5_hwmod = { 950 .name = "gpio5", 951 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 952 .main_clk = "gpio5_ick", 953 .opt_clks = gpio5_opt_clks, 954 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), 955 .prcm = { 956 .omap2 = { 957 .prcm_reg_id = 1, 958 .module_bit = OMAP3430_EN_GPIO5_SHIFT, 959 .module_offs = OMAP3430_PER_MOD, 960 .idlest_reg_id = 1, 961 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT, 962 }, 963 }, 964 .class = &omap3xxx_gpio_hwmod_class, 965 .dev_attr = &gpio_dev_attr, 966 }; 967 968 /* gpio6 */ 969 970 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { 971 { .role = "dbclk", .clk = "gpio6_dbck", }, 972 }; 973 974 static struct omap_hwmod omap3xxx_gpio6_hwmod = { 975 .name = "gpio6", 976 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 977 .main_clk = "gpio6_ick", 978 .opt_clks = gpio6_opt_clks, 979 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), 980 .prcm = { 981 .omap2 = { 982 .prcm_reg_id = 1, 983 .module_bit = OMAP3430_EN_GPIO6_SHIFT, 984 .module_offs = OMAP3430_PER_MOD, 985 .idlest_reg_id = 1, 986 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT, 987 }, 988 }, 989 .class = &omap3xxx_gpio_hwmod_class, 990 .dev_attr = &gpio_dev_attr, 991 }; 992 993 /* dma attributes */ 994 static struct omap_dma_dev_attr dma_dev_attr = { 995 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | 996 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, 997 .lch_count = 32, 998 }; 999 1000 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = { 1001 .rev_offs = 0x0000, 1002 .sysc_offs = 0x002c, 1003 .syss_offs = 0x0028, 1004 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 1005 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | 1006 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE | 1007 SYSS_HAS_RESET_STATUS), 1008 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 1009 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 1010 .sysc_fields = &omap_hwmod_sysc_type1, 1011 }; 1012 1013 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = { 1014 .name = "dma", 1015 .sysc = &omap3xxx_dma_sysc, 1016 }; 1017 1018 /* dma_system */ 1019 static struct omap_hwmod omap3xxx_dma_system_hwmod = { 1020 .name = "dma", 1021 .class = &omap3xxx_dma_hwmod_class, 1022 .mpu_irqs = omap2_dma_system_irqs, 1023 .main_clk = "core_l3_ick", 1024 .prcm = { 1025 .omap2 = { 1026 .module_offs = CORE_MOD, 1027 .prcm_reg_id = 1, 1028 .module_bit = OMAP3430_ST_SDMA_SHIFT, 1029 .idlest_reg_id = 1, 1030 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT, 1031 }, 1032 }, 1033 .dev_attr = &dma_dev_attr, 1034 .flags = HWMOD_NO_IDLEST, 1035 }; 1036 1037 /* 1038 * 'mcbsp' class 1039 * multi channel buffered serial port controller 1040 */ 1041 1042 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = { 1043 .sysc_offs = 0x008c, 1044 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | 1045 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), 1046 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1047 .sysc_fields = &omap_hwmod_sysc_type1, 1048 .clockact = 0x2, 1049 }; 1050 1051 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = { 1052 .name = "mcbsp", 1053 .sysc = &omap3xxx_mcbsp_sysc, 1054 .rev = MCBSP_CONFIG_TYPE3, 1055 }; 1056 1057 /* McBSP functional clock mapping */ 1058 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = { 1059 { .role = "pad_fck", .clk = "mcbsp_clks" }, 1060 { .role = "prcm_fck", .clk = "core_96m_fck" }, 1061 }; 1062 1063 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = { 1064 { .role = "pad_fck", .clk = "mcbsp_clks" }, 1065 { .role = "prcm_fck", .clk = "per_96m_fck" }, 1066 }; 1067 1068 /* mcbsp1 */ 1069 1070 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { 1071 .name = "mcbsp1", 1072 .class = &omap3xxx_mcbsp_hwmod_class, 1073 .main_clk = "mcbsp1_fck", 1074 .prcm = { 1075 .omap2 = { 1076 .prcm_reg_id = 1, 1077 .module_bit = OMAP3430_EN_MCBSP1_SHIFT, 1078 .module_offs = CORE_MOD, 1079 .idlest_reg_id = 1, 1080 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, 1081 }, 1082 }, 1083 .opt_clks = mcbsp15_opt_clks, 1084 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks), 1085 }; 1086 1087 /* mcbsp2 */ 1088 1089 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { 1090 .sidetone = "mcbsp2_sidetone", 1091 }; 1092 1093 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { 1094 .name = "mcbsp2", 1095 .class = &omap3xxx_mcbsp_hwmod_class, 1096 .main_clk = "mcbsp2_fck", 1097 .prcm = { 1098 .omap2 = { 1099 .prcm_reg_id = 1, 1100 .module_bit = OMAP3430_EN_MCBSP2_SHIFT, 1101 .module_offs = OMAP3430_PER_MOD, 1102 .idlest_reg_id = 1, 1103 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, 1104 }, 1105 }, 1106 .opt_clks = mcbsp234_opt_clks, 1107 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), 1108 .dev_attr = &omap34xx_mcbsp2_dev_attr, 1109 }; 1110 1111 /* mcbsp3 */ 1112 1113 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { 1114 .sidetone = "mcbsp3_sidetone", 1115 }; 1116 1117 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { 1118 .name = "mcbsp3", 1119 .class = &omap3xxx_mcbsp_hwmod_class, 1120 .main_clk = "mcbsp3_fck", 1121 .prcm = { 1122 .omap2 = { 1123 .prcm_reg_id = 1, 1124 .module_bit = OMAP3430_EN_MCBSP3_SHIFT, 1125 .module_offs = OMAP3430_PER_MOD, 1126 .idlest_reg_id = 1, 1127 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, 1128 }, 1129 }, 1130 .opt_clks = mcbsp234_opt_clks, 1131 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), 1132 .dev_attr = &omap34xx_mcbsp3_dev_attr, 1133 }; 1134 1135 /* mcbsp4 */ 1136 1137 1138 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { 1139 .name = "mcbsp4", 1140 .class = &omap3xxx_mcbsp_hwmod_class, 1141 .main_clk = "mcbsp4_fck", 1142 .prcm = { 1143 .omap2 = { 1144 .prcm_reg_id = 1, 1145 .module_bit = OMAP3430_EN_MCBSP4_SHIFT, 1146 .module_offs = OMAP3430_PER_MOD, 1147 .idlest_reg_id = 1, 1148 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, 1149 }, 1150 }, 1151 .opt_clks = mcbsp234_opt_clks, 1152 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), 1153 }; 1154 1155 /* mcbsp5 */ 1156 1157 1158 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { 1159 .name = "mcbsp5", 1160 .class = &omap3xxx_mcbsp_hwmod_class, 1161 .main_clk = "mcbsp5_fck", 1162 .prcm = { 1163 .omap2 = { 1164 .prcm_reg_id = 1, 1165 .module_bit = OMAP3430_EN_MCBSP5_SHIFT, 1166 .module_offs = CORE_MOD, 1167 .idlest_reg_id = 1, 1168 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, 1169 }, 1170 }, 1171 .opt_clks = mcbsp15_opt_clks, 1172 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks), 1173 }; 1174 1175 /* 'mcbsp sidetone' class */ 1176 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = { 1177 .sysc_offs = 0x0010, 1178 .sysc_flags = SYSC_HAS_AUTOIDLE, 1179 .sysc_fields = &omap_hwmod_sysc_type1, 1180 }; 1181 1182 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = { 1183 .name = "mcbsp_sidetone", 1184 .sysc = &omap3xxx_mcbsp_sidetone_sysc, 1185 }; 1186 1187 /* mcbsp2_sidetone */ 1188 1189 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { 1190 .name = "mcbsp2_sidetone", 1191 .class = &omap3xxx_mcbsp_sidetone_hwmod_class, 1192 .main_clk = "mcbsp2_ick", 1193 .flags = HWMOD_NO_IDLEST, 1194 }; 1195 1196 /* mcbsp3_sidetone */ 1197 1198 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { 1199 .name = "mcbsp3_sidetone", 1200 .class = &omap3xxx_mcbsp_sidetone_hwmod_class, 1201 .main_clk = "mcbsp3_ick", 1202 .flags = HWMOD_NO_IDLEST, 1203 }; 1204 1205 /* SR common */ 1206 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { 1207 .clkact_shift = 20, 1208 }; 1209 1210 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = { 1211 .sysc_offs = 0x24, 1212 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE), 1213 .clockact = CLOCKACT_TEST_ICLK, 1214 .sysc_fields = &omap34xx_sr_sysc_fields, 1215 }; 1216 1217 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = { 1218 .name = "smartreflex", 1219 .sysc = &omap34xx_sr_sysc, 1220 .rev = 1, 1221 }; 1222 1223 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = { 1224 .sidle_shift = 24, 1225 .enwkup_shift = 26, 1226 }; 1227 1228 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = { 1229 .sysc_offs = 0x38, 1230 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1231 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | 1232 SYSC_NO_CACHE), 1233 .sysc_fields = &omap36xx_sr_sysc_fields, 1234 }; 1235 1236 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = { 1237 .name = "smartreflex", 1238 .sysc = &omap36xx_sr_sysc, 1239 .rev = 2, 1240 }; 1241 1242 /* SR1 */ 1243 static struct omap_smartreflex_dev_attr sr1_dev_attr = { 1244 .sensor_voltdm_name = "mpu_iva", 1245 }; 1246 1247 1248 static struct omap_hwmod omap34xx_sr1_hwmod = { 1249 .name = "smartreflex_mpu_iva", 1250 .class = &omap34xx_smartreflex_hwmod_class, 1251 .main_clk = "sr1_fck", 1252 .prcm = { 1253 .omap2 = { 1254 .prcm_reg_id = 1, 1255 .module_bit = OMAP3430_EN_SR1_SHIFT, 1256 .module_offs = WKUP_MOD, 1257 .idlest_reg_id = 1, 1258 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, 1259 }, 1260 }, 1261 .dev_attr = &sr1_dev_attr, 1262 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 1263 }; 1264 1265 static struct omap_hwmod omap36xx_sr1_hwmod = { 1266 .name = "smartreflex_mpu_iva", 1267 .class = &omap36xx_smartreflex_hwmod_class, 1268 .main_clk = "sr1_fck", 1269 .prcm = { 1270 .omap2 = { 1271 .prcm_reg_id = 1, 1272 .module_bit = OMAP3430_EN_SR1_SHIFT, 1273 .module_offs = WKUP_MOD, 1274 .idlest_reg_id = 1, 1275 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT, 1276 }, 1277 }, 1278 .dev_attr = &sr1_dev_attr, 1279 }; 1280 1281 /* SR2 */ 1282 static struct omap_smartreflex_dev_attr sr2_dev_attr = { 1283 .sensor_voltdm_name = "core", 1284 }; 1285 1286 1287 static struct omap_hwmod omap34xx_sr2_hwmod = { 1288 .name = "smartreflex_core", 1289 .class = &omap34xx_smartreflex_hwmod_class, 1290 .main_clk = "sr2_fck", 1291 .prcm = { 1292 .omap2 = { 1293 .prcm_reg_id = 1, 1294 .module_bit = OMAP3430_EN_SR2_SHIFT, 1295 .module_offs = WKUP_MOD, 1296 .idlest_reg_id = 1, 1297 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, 1298 }, 1299 }, 1300 .dev_attr = &sr2_dev_attr, 1301 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 1302 }; 1303 1304 static struct omap_hwmod omap36xx_sr2_hwmod = { 1305 .name = "smartreflex_core", 1306 .class = &omap36xx_smartreflex_hwmod_class, 1307 .main_clk = "sr2_fck", 1308 .prcm = { 1309 .omap2 = { 1310 .prcm_reg_id = 1, 1311 .module_bit = OMAP3430_EN_SR2_SHIFT, 1312 .module_offs = WKUP_MOD, 1313 .idlest_reg_id = 1, 1314 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT, 1315 }, 1316 }, 1317 .dev_attr = &sr2_dev_attr, 1318 }; 1319 1320 /* 1321 * 'mailbox' class 1322 * mailbox module allowing communication between the on-chip processors 1323 * using a queued mailbox-interrupt mechanism. 1324 */ 1325 1326 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = { 1327 .rev_offs = 0x000, 1328 .sysc_offs = 0x010, 1329 .syss_offs = 0x014, 1330 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1331 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), 1332 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1333 .sysc_fields = &omap_hwmod_sysc_type1, 1334 }; 1335 1336 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = { 1337 .name = "mailbox", 1338 .sysc = &omap3xxx_mailbox_sysc, 1339 }; 1340 1341 static struct omap_hwmod omap3xxx_mailbox_hwmod = { 1342 .name = "mailbox", 1343 .class = &omap3xxx_mailbox_hwmod_class, 1344 .main_clk = "mailboxes_ick", 1345 .prcm = { 1346 .omap2 = { 1347 .prcm_reg_id = 1, 1348 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT, 1349 .module_offs = CORE_MOD, 1350 .idlest_reg_id = 1, 1351 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT, 1352 }, 1353 }, 1354 }; 1355 1356 /* 1357 * 'mcspi' class 1358 * multichannel serial port interface (mcspi) / master/slave synchronous serial 1359 * bus 1360 */ 1361 1362 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = { 1363 .rev_offs = 0x0000, 1364 .sysc_offs = 0x0010, 1365 .syss_offs = 0x0014, 1366 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1367 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 1368 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 1369 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1370 .sysc_fields = &omap_hwmod_sysc_type1, 1371 }; 1372 1373 static struct omap_hwmod_class omap34xx_mcspi_class = { 1374 .name = "mcspi", 1375 .sysc = &omap34xx_mcspi_sysc, 1376 .rev = OMAP3_MCSPI_REV, 1377 }; 1378 1379 /* mcspi1 */ 1380 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { 1381 .num_chipselect = 4, 1382 }; 1383 1384 static struct omap_hwmod omap34xx_mcspi1 = { 1385 .name = "mcspi1", 1386 .main_clk = "mcspi1_fck", 1387 .prcm = { 1388 .omap2 = { 1389 .module_offs = CORE_MOD, 1390 .prcm_reg_id = 1, 1391 .module_bit = OMAP3430_EN_MCSPI1_SHIFT, 1392 .idlest_reg_id = 1, 1393 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT, 1394 }, 1395 }, 1396 .class = &omap34xx_mcspi_class, 1397 .dev_attr = &omap_mcspi1_dev_attr, 1398 }; 1399 1400 /* mcspi2 */ 1401 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { 1402 .num_chipselect = 2, 1403 }; 1404 1405 static struct omap_hwmod omap34xx_mcspi2 = { 1406 .name = "mcspi2", 1407 .main_clk = "mcspi2_fck", 1408 .prcm = { 1409 .omap2 = { 1410 .module_offs = CORE_MOD, 1411 .prcm_reg_id = 1, 1412 .module_bit = OMAP3430_EN_MCSPI2_SHIFT, 1413 .idlest_reg_id = 1, 1414 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT, 1415 }, 1416 }, 1417 .class = &omap34xx_mcspi_class, 1418 .dev_attr = &omap_mcspi2_dev_attr, 1419 }; 1420 1421 /* mcspi3 */ 1422 1423 1424 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { 1425 .num_chipselect = 2, 1426 }; 1427 1428 static struct omap_hwmod omap34xx_mcspi3 = { 1429 .name = "mcspi3", 1430 .main_clk = "mcspi3_fck", 1431 .prcm = { 1432 .omap2 = { 1433 .module_offs = CORE_MOD, 1434 .prcm_reg_id = 1, 1435 .module_bit = OMAP3430_EN_MCSPI3_SHIFT, 1436 .idlest_reg_id = 1, 1437 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT, 1438 }, 1439 }, 1440 .class = &omap34xx_mcspi_class, 1441 .dev_attr = &omap_mcspi3_dev_attr, 1442 }; 1443 1444 /* mcspi4 */ 1445 1446 1447 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { 1448 .num_chipselect = 1, 1449 }; 1450 1451 static struct omap_hwmod omap34xx_mcspi4 = { 1452 .name = "mcspi4", 1453 .main_clk = "mcspi4_fck", 1454 .prcm = { 1455 .omap2 = { 1456 .module_offs = CORE_MOD, 1457 .prcm_reg_id = 1, 1458 .module_bit = OMAP3430_EN_MCSPI4_SHIFT, 1459 .idlest_reg_id = 1, 1460 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT, 1461 }, 1462 }, 1463 .class = &omap34xx_mcspi_class, 1464 .dev_attr = &omap_mcspi4_dev_attr, 1465 }; 1466 1467 /* usbhsotg */ 1468 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = { 1469 .rev_offs = 0x0400, 1470 .sysc_offs = 0x0404, 1471 .syss_offs = 0x0408, 1472 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| 1473 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 1474 SYSC_HAS_AUTOIDLE), 1475 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 1476 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 1477 .sysc_fields = &omap_hwmod_sysc_type1, 1478 }; 1479 1480 static struct omap_hwmod_class usbotg_class = { 1481 .name = "usbotg", 1482 .sysc = &omap3xxx_usbhsotg_sysc, 1483 }; 1484 1485 /* usb_otg_hs */ 1486 1487 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { 1488 .name = "usb_otg_hs", 1489 .main_clk = "hsotgusb_ick", 1490 .prcm = { 1491 .omap2 = { 1492 .prcm_reg_id = 1, 1493 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT, 1494 .module_offs = CORE_MOD, 1495 .idlest_reg_id = 1, 1496 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT, 1497 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT, 1498 }, 1499 }, 1500 .class = &usbotg_class, 1501 1502 /* 1503 * Erratum ID: i479 idle_req / idle_ack mechanism potentially 1504 * broken when autoidle is enabled 1505 * workaround is to disable the autoidle bit at module level. 1506 * 1507 * Enabling the device in any other MIDLEMODE setting but force-idle 1508 * causes core_pwrdm not enter idle states at least on OMAP3630. 1509 * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY 1510 * signal when MIDLEMODE is set to force-idle. 1511 */ 1512 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE | 1513 HWMOD_FORCE_MSTANDBY | HWMOD_RECONFIG_IO_CHAIN, 1514 }; 1515 1516 /* usb_otg_hs */ 1517 1518 static struct omap_hwmod_class am35xx_usbotg_class = { 1519 .name = "am35xx_usbotg", 1520 }; 1521 1522 static struct omap_hwmod am35xx_usbhsotg_hwmod = { 1523 .name = "am35x_otg_hs", 1524 .main_clk = "hsotgusb_fck", 1525 .class = &am35xx_usbotg_class, 1526 .flags = HWMOD_NO_IDLEST, 1527 }; 1528 1529 /* MMC/SD/SDIO common */ 1530 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = { 1531 .rev_offs = 0x1fc, 1532 .sysc_offs = 0x10, 1533 .syss_offs = 0x14, 1534 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1535 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 1536 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 1537 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1538 .sysc_fields = &omap_hwmod_sysc_type1, 1539 }; 1540 1541 static struct omap_hwmod_class omap34xx_mmc_class = { 1542 .name = "mmc", 1543 .sysc = &omap34xx_mmc_sysc, 1544 }; 1545 1546 /* MMC/SD/SDIO1 */ 1547 1548 1549 1550 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = { 1551 { .role = "dbck", .clk = "omap_32k_fck", }, 1552 }; 1553 1554 static struct omap_hsmmc_dev_attr mmc1_dev_attr = { 1555 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, 1556 }; 1557 1558 /* See 35xx errata 2.1.1.128 in SPRZ278F */ 1559 static struct omap_hsmmc_dev_attr mmc1_pre_es3_dev_attr = { 1560 .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT | 1561 OMAP_HSMMC_BROKEN_MULTIBLOCK_READ), 1562 }; 1563 1564 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = { 1565 .name = "mmc1", 1566 .opt_clks = omap34xx_mmc1_opt_clks, 1567 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), 1568 .main_clk = "mmchs1_fck", 1569 .prcm = { 1570 .omap2 = { 1571 .module_offs = CORE_MOD, 1572 .prcm_reg_id = 1, 1573 .module_bit = OMAP3430_EN_MMC1_SHIFT, 1574 .idlest_reg_id = 1, 1575 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, 1576 }, 1577 }, 1578 .dev_attr = &mmc1_pre_es3_dev_attr, 1579 .class = &omap34xx_mmc_class, 1580 }; 1581 1582 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = { 1583 .name = "mmc1", 1584 .opt_clks = omap34xx_mmc1_opt_clks, 1585 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), 1586 .main_clk = "mmchs1_fck", 1587 .prcm = { 1588 .omap2 = { 1589 .module_offs = CORE_MOD, 1590 .prcm_reg_id = 1, 1591 .module_bit = OMAP3430_EN_MMC1_SHIFT, 1592 .idlest_reg_id = 1, 1593 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, 1594 }, 1595 }, 1596 .dev_attr = &mmc1_dev_attr, 1597 .class = &omap34xx_mmc_class, 1598 }; 1599 1600 /* MMC/SD/SDIO2 */ 1601 1602 1603 1604 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = { 1605 { .role = "dbck", .clk = "omap_32k_fck", }, 1606 }; 1607 1608 /* See 35xx errata 2.1.1.128 in SPRZ278F */ 1609 static struct omap_hsmmc_dev_attr mmc2_pre_es3_dev_attr = { 1610 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, 1611 }; 1612 1613 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = { 1614 .name = "mmc2", 1615 .opt_clks = omap34xx_mmc2_opt_clks, 1616 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), 1617 .main_clk = "mmchs2_fck", 1618 .prcm = { 1619 .omap2 = { 1620 .module_offs = CORE_MOD, 1621 .prcm_reg_id = 1, 1622 .module_bit = OMAP3430_EN_MMC2_SHIFT, 1623 .idlest_reg_id = 1, 1624 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, 1625 }, 1626 }, 1627 .dev_attr = &mmc2_pre_es3_dev_attr, 1628 .class = &omap34xx_mmc_class, 1629 }; 1630 1631 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = { 1632 .name = "mmc2", 1633 .opt_clks = omap34xx_mmc2_opt_clks, 1634 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), 1635 .main_clk = "mmchs2_fck", 1636 .prcm = { 1637 .omap2 = { 1638 .module_offs = CORE_MOD, 1639 .prcm_reg_id = 1, 1640 .module_bit = OMAP3430_EN_MMC2_SHIFT, 1641 .idlest_reg_id = 1, 1642 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, 1643 }, 1644 }, 1645 .class = &omap34xx_mmc_class, 1646 }; 1647 1648 /* MMC/SD/SDIO3 */ 1649 1650 1651 1652 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = { 1653 { .role = "dbck", .clk = "omap_32k_fck", }, 1654 }; 1655 1656 static struct omap_hwmod omap3xxx_mmc3_hwmod = { 1657 .name = "mmc3", 1658 .opt_clks = omap34xx_mmc3_opt_clks, 1659 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks), 1660 .main_clk = "mmchs3_fck", 1661 .prcm = { 1662 .omap2 = { 1663 .prcm_reg_id = 1, 1664 .module_bit = OMAP3430_EN_MMC3_SHIFT, 1665 .idlest_reg_id = 1, 1666 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT, 1667 }, 1668 }, 1669 .class = &omap34xx_mmc_class, 1670 }; 1671 1672 /* 1673 * 'usb_host_hs' class 1674 * high-speed multi-port usb host controller 1675 */ 1676 1677 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = { 1678 .rev_offs = 0x0000, 1679 .sysc_offs = 0x0010, 1680 .syss_offs = 0x0014, 1681 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY | 1682 SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | 1683 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | 1684 SYSS_HAS_RESET_STATUS), 1685 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 1686 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 1687 .sysc_fields = &omap_hwmod_sysc_type1, 1688 }; 1689 1690 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = { 1691 .name = "usb_host_hs", 1692 .sysc = &omap3xxx_usb_host_hs_sysc, 1693 }; 1694 1695 1696 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = { 1697 .name = "usb_host_hs", 1698 .class = &omap3xxx_usb_host_hs_hwmod_class, 1699 .clkdm_name = "usbhost_clkdm", 1700 .main_clk = "usbhost_48m_fck", 1701 .prcm = { 1702 .omap2 = { 1703 .module_offs = OMAP3430ES2_USBHOST_MOD, 1704 .prcm_reg_id = 1, 1705 .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, 1706 .idlest_reg_id = 1, 1707 .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT, 1708 .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT, 1709 }, 1710 }, 1711 1712 /* 1713 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock 1714 * id: i660 1715 * 1716 * Description: 1717 * In the following configuration : 1718 * - USBHOST module is set to smart-idle mode 1719 * - PRCM asserts idle_req to the USBHOST module ( This typically 1720 * happens when the system is going to a low power mode : all ports 1721 * have been suspended, the master part of the USBHOST module has 1722 * entered the standby state, and SW has cut the functional clocks) 1723 * - an USBHOST interrupt occurs before the module is able to answer 1724 * idle_ack, typically a remote wakeup IRQ. 1725 * Then the USB HOST module will enter a deadlock situation where it 1726 * is no more accessible nor functional. 1727 * 1728 * Workaround: 1729 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE 1730 */ 1731 1732 /* 1733 * Errata: USB host EHCI may stall when entering smart-standby mode 1734 * Id: i571 1735 * 1736 * Description: 1737 * When the USBHOST module is set to smart-standby mode, and when it is 1738 * ready to enter the standby state (i.e. all ports are suspended and 1739 * all attached devices are in suspend mode), then it can wrongly assert 1740 * the Mstandby signal too early while there are still some residual OCP 1741 * transactions ongoing. If this condition occurs, the internal state 1742 * machine may go to an undefined state and the USB link may be stuck 1743 * upon the next resume. 1744 * 1745 * Workaround: 1746 * Don't use smart standby; use only force standby, 1747 * hence HWMOD_SWSUP_MSTANDBY 1748 */ 1749 1750 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, 1751 }; 1752 1753 /* 1754 * 'usb_tll_hs' class 1755 * usb_tll_hs module is the adapter on the usb_host_hs ports 1756 */ 1757 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = { 1758 .rev_offs = 0x0000, 1759 .sysc_offs = 0x0010, 1760 .syss_offs = 0x0014, 1761 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1762 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 1763 SYSC_HAS_AUTOIDLE), 1764 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1765 .sysc_fields = &omap_hwmod_sysc_type1, 1766 }; 1767 1768 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = { 1769 .name = "usb_tll_hs", 1770 .sysc = &omap3xxx_usb_tll_hs_sysc, 1771 }; 1772 1773 1774 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { 1775 .name = "usb_tll_hs", 1776 .class = &omap3xxx_usb_tll_hs_hwmod_class, 1777 .clkdm_name = "core_l4_clkdm", 1778 .main_clk = "usbtll_fck", 1779 .prcm = { 1780 .omap2 = { 1781 .module_offs = CORE_MOD, 1782 .prcm_reg_id = 3, 1783 .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT, 1784 .idlest_reg_id = 3, 1785 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT, 1786 }, 1787 }, 1788 }; 1789 1790 static struct omap_hwmod omap3xxx_hdq1w_hwmod = { 1791 .name = "hdq1w", 1792 .main_clk = "hdq_fck", 1793 .prcm = { 1794 .omap2 = { 1795 .module_offs = CORE_MOD, 1796 .prcm_reg_id = 1, 1797 .module_bit = OMAP3430_EN_HDQ_SHIFT, 1798 .idlest_reg_id = 1, 1799 .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT, 1800 }, 1801 }, 1802 .class = &omap2_hdq1w_class, 1803 }; 1804 1805 /* SAD2D */ 1806 static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = { 1807 { .name = "rst_modem_pwron_sw", .rst_shift = 0 }, 1808 { .name = "rst_modem_sw", .rst_shift = 1 }, 1809 }; 1810 1811 static struct omap_hwmod_class omap3xxx_sad2d_class = { 1812 .name = "sad2d", 1813 }; 1814 1815 static struct omap_hwmod omap3xxx_sad2d_hwmod = { 1816 .name = "sad2d", 1817 .rst_lines = omap3xxx_sad2d_resets, 1818 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_sad2d_resets), 1819 .main_clk = "sad2d_ick", 1820 .prcm = { 1821 .omap2 = { 1822 .module_offs = CORE_MOD, 1823 .prcm_reg_id = 1, 1824 .module_bit = OMAP3430_EN_SAD2D_SHIFT, 1825 .idlest_reg_id = 1, 1826 .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT, 1827 }, 1828 }, 1829 .class = &omap3xxx_sad2d_class, 1830 }; 1831 1832 /* 1833 * '32K sync counter' class 1834 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock 1835 */ 1836 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = { 1837 .rev_offs = 0x0000, 1838 .sysc_offs = 0x0004, 1839 .sysc_flags = SYSC_HAS_SIDLEMODE, 1840 .idlemodes = (SIDLE_FORCE | SIDLE_NO), 1841 .sysc_fields = &omap_hwmod_sysc_type1, 1842 }; 1843 1844 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = { 1845 .name = "counter", 1846 .sysc = &omap3xxx_counter_sysc, 1847 }; 1848 1849 static struct omap_hwmod omap3xxx_counter_32k_hwmod = { 1850 .name = "counter_32k", 1851 .class = &omap3xxx_counter_hwmod_class, 1852 .clkdm_name = "wkup_clkdm", 1853 .flags = HWMOD_SWSUP_SIDLE, 1854 .main_clk = "wkup_32k_fck", 1855 .prcm = { 1856 .omap2 = { 1857 .module_offs = WKUP_MOD, 1858 .prcm_reg_id = 1, 1859 .module_bit = OMAP3430_ST_32KSYNC_SHIFT, 1860 .idlest_reg_id = 1, 1861 .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT, 1862 }, 1863 }, 1864 }; 1865 1866 /* 1867 * 'gpmc' class 1868 * general purpose memory controller 1869 */ 1870 1871 static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = { 1872 .rev_offs = 0x0000, 1873 .sysc_offs = 0x0010, 1874 .syss_offs = 0x0014, 1875 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | 1876 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 1877 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1878 .sysc_fields = &omap_hwmod_sysc_type1, 1879 }; 1880 1881 static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = { 1882 .name = "gpmc", 1883 .sysc = &omap3xxx_gpmc_sysc, 1884 }; 1885 1886 static struct omap_hwmod omap3xxx_gpmc_hwmod = { 1887 .name = "gpmc", 1888 .class = &omap3xxx_gpmc_hwmod_class, 1889 .clkdm_name = "core_l3_clkdm", 1890 .main_clk = "gpmc_fck", 1891 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */ 1892 .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS, 1893 }; 1894 1895 /* 1896 * interfaces 1897 */ 1898 1899 /* L3 -> L4_CORE interface */ 1900 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { 1901 .master = &omap3xxx_l3_main_hwmod, 1902 .slave = &omap3xxx_l4_core_hwmod, 1903 .user = OCP_USER_MPU | OCP_USER_SDMA, 1904 }; 1905 1906 /* L3 -> L4_PER interface */ 1907 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = { 1908 .master = &omap3xxx_l3_main_hwmod, 1909 .slave = &omap3xxx_l4_per_hwmod, 1910 .user = OCP_USER_MPU | OCP_USER_SDMA, 1911 }; 1912 1913 1914 /* MPU -> L3 interface */ 1915 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { 1916 .master = &omap3xxx_mpu_hwmod, 1917 .slave = &omap3xxx_l3_main_hwmod, 1918 .user = OCP_USER_MPU, 1919 }; 1920 1921 1922 /* l3 -> debugss */ 1923 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = { 1924 .master = &omap3xxx_l3_main_hwmod, 1925 .slave = &omap3xxx_debugss_hwmod, 1926 .user = OCP_USER_MPU, 1927 }; 1928 1929 /* DSS -> l3 */ 1930 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = { 1931 .master = &omap3430es1_dss_core_hwmod, 1932 .slave = &omap3xxx_l3_main_hwmod, 1933 .user = OCP_USER_MPU | OCP_USER_SDMA, 1934 }; 1935 1936 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = { 1937 .master = &omap3xxx_dss_core_hwmod, 1938 .slave = &omap3xxx_l3_main_hwmod, 1939 .fw = { 1940 .omap2 = { 1941 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS, 1942 .flags = OMAP_FIREWALL_L3, 1943 }, 1944 }, 1945 .user = OCP_USER_MPU | OCP_USER_SDMA, 1946 }; 1947 1948 /* l3_core -> usbhsotg interface */ 1949 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { 1950 .master = &omap3xxx_usbhsotg_hwmod, 1951 .slave = &omap3xxx_l3_main_hwmod, 1952 .clk = "core_l3_ick", 1953 .user = OCP_USER_MPU, 1954 }; 1955 1956 /* l3_core -> am35xx_usbhsotg interface */ 1957 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { 1958 .master = &am35xx_usbhsotg_hwmod, 1959 .slave = &omap3xxx_l3_main_hwmod, 1960 .clk = "hsotgusb_ick", 1961 .user = OCP_USER_MPU, 1962 }; 1963 1964 /* l3_core -> sad2d interface */ 1965 static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = { 1966 .master = &omap3xxx_sad2d_hwmod, 1967 .slave = &omap3xxx_l3_main_hwmod, 1968 .clk = "core_l3_ick", 1969 .user = OCP_USER_MPU, 1970 }; 1971 1972 /* L4_CORE -> L4_WKUP interface */ 1973 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { 1974 .master = &omap3xxx_l4_core_hwmod, 1975 .slave = &omap3xxx_l4_wkup_hwmod, 1976 .user = OCP_USER_MPU | OCP_USER_SDMA, 1977 }; 1978 1979 /* L4 CORE -> MMC1 interface */ 1980 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = { 1981 .master = &omap3xxx_l4_core_hwmod, 1982 .slave = &omap3xxx_pre_es3_mmc1_hwmod, 1983 .clk = "mmchs1_ick", 1984 .user = OCP_USER_MPU | OCP_USER_SDMA, 1985 .flags = OMAP_FIREWALL_L4, 1986 }; 1987 1988 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = { 1989 .master = &omap3xxx_l4_core_hwmod, 1990 .slave = &omap3xxx_es3plus_mmc1_hwmod, 1991 .clk = "mmchs1_ick", 1992 .user = OCP_USER_MPU | OCP_USER_SDMA, 1993 .flags = OMAP_FIREWALL_L4, 1994 }; 1995 1996 /* L4 CORE -> MMC2 interface */ 1997 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = { 1998 .master = &omap3xxx_l4_core_hwmod, 1999 .slave = &omap3xxx_pre_es3_mmc2_hwmod, 2000 .clk = "mmchs2_ick", 2001 .user = OCP_USER_MPU | OCP_USER_SDMA, 2002 .flags = OMAP_FIREWALL_L4, 2003 }; 2004 2005 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = { 2006 .master = &omap3xxx_l4_core_hwmod, 2007 .slave = &omap3xxx_es3plus_mmc2_hwmod, 2008 .clk = "mmchs2_ick", 2009 .user = OCP_USER_MPU | OCP_USER_SDMA, 2010 .flags = OMAP_FIREWALL_L4, 2011 }; 2012 2013 /* L4 CORE -> MMC3 interface */ 2014 2015 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { 2016 .master = &omap3xxx_l4_core_hwmod, 2017 .slave = &omap3xxx_mmc3_hwmod, 2018 .clk = "mmchs3_ick", 2019 .user = OCP_USER_MPU | OCP_USER_SDMA, 2020 .flags = OMAP_FIREWALL_L4, 2021 }; 2022 2023 /* L4 CORE -> UART1 interface */ 2024 2025 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { 2026 .master = &omap3xxx_l4_core_hwmod, 2027 .slave = &omap3xxx_uart1_hwmod, 2028 .clk = "uart1_ick", 2029 .user = OCP_USER_MPU | OCP_USER_SDMA, 2030 }; 2031 2032 /* L4 CORE -> UART2 interface */ 2033 2034 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { 2035 .master = &omap3xxx_l4_core_hwmod, 2036 .slave = &omap3xxx_uart2_hwmod, 2037 .clk = "uart2_ick", 2038 .user = OCP_USER_MPU | OCP_USER_SDMA, 2039 }; 2040 2041 /* L4 PER -> UART3 interface */ 2042 2043 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { 2044 .master = &omap3xxx_l4_per_hwmod, 2045 .slave = &omap3xxx_uart3_hwmod, 2046 .clk = "uart3_ick", 2047 .user = OCP_USER_MPU | OCP_USER_SDMA, 2048 }; 2049 2050 /* L4 PER -> UART4 interface */ 2051 2052 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = { 2053 .master = &omap3xxx_l4_per_hwmod, 2054 .slave = &omap36xx_uart4_hwmod, 2055 .clk = "uart4_ick", 2056 .user = OCP_USER_MPU | OCP_USER_SDMA, 2057 }; 2058 2059 /* AM35xx: L4 CORE -> UART4 interface */ 2060 2061 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = { 2062 .master = &omap3xxx_l4_core_hwmod, 2063 .slave = &am35xx_uart4_hwmod, 2064 .clk = "uart4_ick", 2065 .user = OCP_USER_MPU | OCP_USER_SDMA, 2066 }; 2067 2068 /* L4 CORE -> I2C1 interface */ 2069 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { 2070 .master = &omap3xxx_l4_core_hwmod, 2071 .slave = &omap3xxx_i2c1_hwmod, 2072 .clk = "i2c1_ick", 2073 .fw = { 2074 .omap2 = { 2075 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, 2076 .l4_prot_group = 7, 2077 .flags = OMAP_FIREWALL_L4, 2078 }, 2079 }, 2080 .user = OCP_USER_MPU | OCP_USER_SDMA, 2081 }; 2082 2083 /* L4 CORE -> I2C2 interface */ 2084 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { 2085 .master = &omap3xxx_l4_core_hwmod, 2086 .slave = &omap3xxx_i2c2_hwmod, 2087 .clk = "i2c2_ick", 2088 .fw = { 2089 .omap2 = { 2090 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, 2091 .l4_prot_group = 7, 2092 .flags = OMAP_FIREWALL_L4, 2093 }, 2094 }, 2095 .user = OCP_USER_MPU | OCP_USER_SDMA, 2096 }; 2097 2098 /* L4 CORE -> I2C3 interface */ 2099 2100 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { 2101 .master = &omap3xxx_l4_core_hwmod, 2102 .slave = &omap3xxx_i2c3_hwmod, 2103 .clk = "i2c3_ick", 2104 .fw = { 2105 .omap2 = { 2106 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, 2107 .l4_prot_group = 7, 2108 .flags = OMAP_FIREWALL_L4, 2109 }, 2110 }, 2111 .user = OCP_USER_MPU | OCP_USER_SDMA, 2112 }; 2113 2114 /* L4 CORE -> SR1 interface */ 2115 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = { 2116 { 2117 .pa_start = OMAP34XX_SR1_BASE, 2118 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1, 2119 .flags = ADDR_TYPE_RT, 2120 }, 2121 { }, 2122 }; 2123 2124 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = { 2125 .master = &omap3xxx_l4_core_hwmod, 2126 .slave = &omap34xx_sr1_hwmod, 2127 .clk = "sr_l4_ick", 2128 .addr = omap3_sr1_addr_space, 2129 .user = OCP_USER_MPU, 2130 }; 2131 2132 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = { 2133 .master = &omap3xxx_l4_core_hwmod, 2134 .slave = &omap36xx_sr1_hwmod, 2135 .clk = "sr_l4_ick", 2136 .addr = omap3_sr1_addr_space, 2137 .user = OCP_USER_MPU, 2138 }; 2139 2140 /* L4 CORE -> SR1 interface */ 2141 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = { 2142 { 2143 .pa_start = OMAP34XX_SR2_BASE, 2144 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1, 2145 .flags = ADDR_TYPE_RT, 2146 }, 2147 { }, 2148 }; 2149 2150 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = { 2151 .master = &omap3xxx_l4_core_hwmod, 2152 .slave = &omap34xx_sr2_hwmod, 2153 .clk = "sr_l4_ick", 2154 .addr = omap3_sr2_addr_space, 2155 .user = OCP_USER_MPU, 2156 }; 2157 2158 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = { 2159 .master = &omap3xxx_l4_core_hwmod, 2160 .slave = &omap36xx_sr2_hwmod, 2161 .clk = "sr_l4_ick", 2162 .addr = omap3_sr2_addr_space, 2163 .user = OCP_USER_MPU, 2164 }; 2165 2166 2167 /* l4_core -> usbhsotg */ 2168 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { 2169 .master = &omap3xxx_l4_core_hwmod, 2170 .slave = &omap3xxx_usbhsotg_hwmod, 2171 .clk = "l4_ick", 2172 .user = OCP_USER_MPU, 2173 }; 2174 2175 2176 /* l4_core -> usbhsotg */ 2177 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { 2178 .master = &omap3xxx_l4_core_hwmod, 2179 .slave = &am35xx_usbhsotg_hwmod, 2180 .clk = "hsotgusb_ick", 2181 .user = OCP_USER_MPU, 2182 }; 2183 2184 /* L4_WKUP -> L4_SEC interface */ 2185 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = { 2186 .master = &omap3xxx_l4_wkup_hwmod, 2187 .slave = &omap3xxx_l4_sec_hwmod, 2188 .user = OCP_USER_MPU | OCP_USER_SDMA, 2189 }; 2190 2191 /* IVA2 <- L3 interface */ 2192 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = { 2193 .master = &omap3xxx_l3_main_hwmod, 2194 .slave = &omap3xxx_iva_hwmod, 2195 .clk = "core_l3_ick", 2196 .user = OCP_USER_MPU | OCP_USER_SDMA, 2197 }; 2198 2199 2200 /* l4_wkup -> timer1 */ 2201 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = { 2202 .master = &omap3xxx_l4_wkup_hwmod, 2203 .slave = &omap3xxx_timer1_hwmod, 2204 .clk = "gpt1_ick", 2205 .user = OCP_USER_MPU | OCP_USER_SDMA, 2206 }; 2207 2208 2209 /* l4_per -> timer2 */ 2210 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = { 2211 .master = &omap3xxx_l4_per_hwmod, 2212 .slave = &omap3xxx_timer2_hwmod, 2213 .clk = "gpt2_ick", 2214 .user = OCP_USER_MPU | OCP_USER_SDMA, 2215 }; 2216 2217 2218 /* l4_per -> timer3 */ 2219 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = { 2220 .master = &omap3xxx_l4_per_hwmod, 2221 .slave = &omap3xxx_timer3_hwmod, 2222 .clk = "gpt3_ick", 2223 .user = OCP_USER_MPU | OCP_USER_SDMA, 2224 }; 2225 2226 2227 /* l4_per -> timer4 */ 2228 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = { 2229 .master = &omap3xxx_l4_per_hwmod, 2230 .slave = &omap3xxx_timer4_hwmod, 2231 .clk = "gpt4_ick", 2232 .user = OCP_USER_MPU | OCP_USER_SDMA, 2233 }; 2234 2235 2236 /* l4_per -> timer5 */ 2237 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = { 2238 .master = &omap3xxx_l4_per_hwmod, 2239 .slave = &omap3xxx_timer5_hwmod, 2240 .clk = "gpt5_ick", 2241 .user = OCP_USER_MPU | OCP_USER_SDMA, 2242 }; 2243 2244 2245 /* l4_per -> timer6 */ 2246 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = { 2247 .master = &omap3xxx_l4_per_hwmod, 2248 .slave = &omap3xxx_timer6_hwmod, 2249 .clk = "gpt6_ick", 2250 .user = OCP_USER_MPU | OCP_USER_SDMA, 2251 }; 2252 2253 2254 /* l4_per -> timer7 */ 2255 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = { 2256 .master = &omap3xxx_l4_per_hwmod, 2257 .slave = &omap3xxx_timer7_hwmod, 2258 .clk = "gpt7_ick", 2259 .user = OCP_USER_MPU | OCP_USER_SDMA, 2260 }; 2261 2262 2263 /* l4_per -> timer8 */ 2264 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = { 2265 .master = &omap3xxx_l4_per_hwmod, 2266 .slave = &omap3xxx_timer8_hwmod, 2267 .clk = "gpt8_ick", 2268 .user = OCP_USER_MPU | OCP_USER_SDMA, 2269 }; 2270 2271 2272 /* l4_per -> timer9 */ 2273 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = { 2274 .master = &omap3xxx_l4_per_hwmod, 2275 .slave = &omap3xxx_timer9_hwmod, 2276 .clk = "gpt9_ick", 2277 .user = OCP_USER_MPU | OCP_USER_SDMA, 2278 }; 2279 2280 /* l4_core -> timer10 */ 2281 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = { 2282 .master = &omap3xxx_l4_core_hwmod, 2283 .slave = &omap3xxx_timer10_hwmod, 2284 .clk = "gpt10_ick", 2285 .user = OCP_USER_MPU | OCP_USER_SDMA, 2286 }; 2287 2288 /* l4_core -> timer11 */ 2289 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { 2290 .master = &omap3xxx_l4_core_hwmod, 2291 .slave = &omap3xxx_timer11_hwmod, 2292 .clk = "gpt11_ick", 2293 .user = OCP_USER_MPU | OCP_USER_SDMA, 2294 }; 2295 2296 2297 /* l4_core -> timer12 */ 2298 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = { 2299 .master = &omap3xxx_l4_sec_hwmod, 2300 .slave = &omap3xxx_timer12_hwmod, 2301 .clk = "gpt12_ick", 2302 .user = OCP_USER_MPU | OCP_USER_SDMA, 2303 }; 2304 2305 /* l4_wkup -> wd_timer2 */ 2306 2307 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { 2308 .master = &omap3xxx_l4_wkup_hwmod, 2309 .slave = &omap3xxx_wd_timer2_hwmod, 2310 .clk = "wdt2_ick", 2311 .user = OCP_USER_MPU | OCP_USER_SDMA, 2312 }; 2313 2314 /* l4_core -> dss */ 2315 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { 2316 .master = &omap3xxx_l4_core_hwmod, 2317 .slave = &omap3430es1_dss_core_hwmod, 2318 .clk = "dss_ick", 2319 .fw = { 2320 .omap2 = { 2321 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, 2322 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 2323 .flags = OMAP_FIREWALL_L4, 2324 }, 2325 }, 2326 .user = OCP_USER_MPU | OCP_USER_SDMA, 2327 }; 2328 2329 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = { 2330 .master = &omap3xxx_l4_core_hwmod, 2331 .slave = &omap3xxx_dss_core_hwmod, 2332 .clk = "dss_ick", 2333 .fw = { 2334 .omap2 = { 2335 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, 2336 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 2337 .flags = OMAP_FIREWALL_L4, 2338 }, 2339 }, 2340 .user = OCP_USER_MPU | OCP_USER_SDMA, 2341 }; 2342 2343 /* l4_core -> dss_dispc */ 2344 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { 2345 .master = &omap3xxx_l4_core_hwmod, 2346 .slave = &omap3xxx_dss_dispc_hwmod, 2347 .clk = "dss_ick", 2348 .fw = { 2349 .omap2 = { 2350 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, 2351 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 2352 .flags = OMAP_FIREWALL_L4, 2353 }, 2354 }, 2355 .user = OCP_USER_MPU | OCP_USER_SDMA, 2356 }; 2357 2358 /* l4_core -> dss_dsi1 */ 2359 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { 2360 .master = &omap3xxx_l4_core_hwmod, 2361 .slave = &omap3xxx_dss_dsi1_hwmod, 2362 .clk = "dss_ick", 2363 .fw = { 2364 .omap2 = { 2365 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, 2366 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 2367 .flags = OMAP_FIREWALL_L4, 2368 }, 2369 }, 2370 .user = OCP_USER_MPU | OCP_USER_SDMA, 2371 }; 2372 2373 /* l4_core -> dss_rfbi */ 2374 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { 2375 .master = &omap3xxx_l4_core_hwmod, 2376 .slave = &omap3xxx_dss_rfbi_hwmod, 2377 .clk = "dss_ick", 2378 .fw = { 2379 .omap2 = { 2380 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, 2381 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP , 2382 .flags = OMAP_FIREWALL_L4, 2383 }, 2384 }, 2385 .user = OCP_USER_MPU | OCP_USER_SDMA, 2386 }; 2387 2388 /* l4_core -> dss_venc */ 2389 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { 2390 .master = &omap3xxx_l4_core_hwmod, 2391 .slave = &omap3xxx_dss_venc_hwmod, 2392 .clk = "dss_ick", 2393 .fw = { 2394 .omap2 = { 2395 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, 2396 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, 2397 .flags = OMAP_FIREWALL_L4, 2398 }, 2399 }, 2400 .flags = OCPIF_SWSUP_IDLE, 2401 .user = OCP_USER_MPU | OCP_USER_SDMA, 2402 }; 2403 2404 /* l4_wkup -> gpio1 */ 2405 2406 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { 2407 .master = &omap3xxx_l4_wkup_hwmod, 2408 .slave = &omap3xxx_gpio1_hwmod, 2409 .user = OCP_USER_MPU | OCP_USER_SDMA, 2410 }; 2411 2412 /* l4_per -> gpio2 */ 2413 2414 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { 2415 .master = &omap3xxx_l4_per_hwmod, 2416 .slave = &omap3xxx_gpio2_hwmod, 2417 .user = OCP_USER_MPU | OCP_USER_SDMA, 2418 }; 2419 2420 /* l4_per -> gpio3 */ 2421 2422 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { 2423 .master = &omap3xxx_l4_per_hwmod, 2424 .slave = &omap3xxx_gpio3_hwmod, 2425 .user = OCP_USER_MPU | OCP_USER_SDMA, 2426 }; 2427 2428 /* 2429 * 'mmu' class 2430 * The memory management unit performs virtual to physical address translation 2431 * for its requestors. 2432 */ 2433 2434 static struct omap_hwmod_class_sysconfig mmu_sysc = { 2435 .rev_offs = 0x000, 2436 .sysc_offs = 0x010, 2437 .syss_offs = 0x014, 2438 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 2439 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), 2440 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 2441 .sysc_fields = &omap_hwmod_sysc_type1, 2442 }; 2443 2444 static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = { 2445 .name = "mmu", 2446 .sysc = &mmu_sysc, 2447 }; 2448 2449 /* mmu isp */ 2450 static struct omap_hwmod omap3xxx_mmu_isp_hwmod; 2451 2452 /* l4_core -> mmu isp */ 2453 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = { 2454 .master = &omap3xxx_l4_core_hwmod, 2455 .slave = &omap3xxx_mmu_isp_hwmod, 2456 .user = OCP_USER_MPU | OCP_USER_SDMA, 2457 }; 2458 2459 static struct omap_hwmod omap3xxx_mmu_isp_hwmod = { 2460 .name = "mmu_isp", 2461 .class = &omap3xxx_mmu_hwmod_class, 2462 .main_clk = "cam_ick", 2463 .flags = HWMOD_NO_IDLEST, 2464 }; 2465 2466 /* mmu iva */ 2467 2468 static struct omap_hwmod omap3xxx_mmu_iva_hwmod; 2469 2470 static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = { 2471 { .name = "mmu", .rst_shift = 1, .st_shift = 9 }, 2472 }; 2473 2474 /* l3_main -> iva mmu */ 2475 static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = { 2476 .master = &omap3xxx_l3_main_hwmod, 2477 .slave = &omap3xxx_mmu_iva_hwmod, 2478 .user = OCP_USER_MPU | OCP_USER_SDMA, 2479 }; 2480 2481 static struct omap_hwmod omap3xxx_mmu_iva_hwmod = { 2482 .name = "mmu_iva", 2483 .class = &omap3xxx_mmu_hwmod_class, 2484 .clkdm_name = "iva2_clkdm", 2485 .rst_lines = omap3xxx_mmu_iva_resets, 2486 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_mmu_iva_resets), 2487 .main_clk = "iva2_ck", 2488 .prcm = { 2489 .omap2 = { 2490 .module_offs = OMAP3430_IVA2_MOD, 2491 .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, 2492 .idlest_reg_id = 1, 2493 .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT, 2494 }, 2495 }, 2496 .flags = HWMOD_NO_IDLEST, 2497 }; 2498 2499 /* l4_per -> gpio4 */ 2500 2501 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { 2502 .master = &omap3xxx_l4_per_hwmod, 2503 .slave = &omap3xxx_gpio4_hwmod, 2504 .user = OCP_USER_MPU | OCP_USER_SDMA, 2505 }; 2506 2507 /* l4_per -> gpio5 */ 2508 2509 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { 2510 .master = &omap3xxx_l4_per_hwmod, 2511 .slave = &omap3xxx_gpio5_hwmod, 2512 .user = OCP_USER_MPU | OCP_USER_SDMA, 2513 }; 2514 2515 /* l4_per -> gpio6 */ 2516 2517 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { 2518 .master = &omap3xxx_l4_per_hwmod, 2519 .slave = &omap3xxx_gpio6_hwmod, 2520 .user = OCP_USER_MPU | OCP_USER_SDMA, 2521 }; 2522 2523 /* dma_system -> L3 */ 2524 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = { 2525 .master = &omap3xxx_dma_system_hwmod, 2526 .slave = &omap3xxx_l3_main_hwmod, 2527 .clk = "core_l3_ick", 2528 .user = OCP_USER_MPU | OCP_USER_SDMA, 2529 }; 2530 2531 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { 2532 { 2533 .pa_start = 0x48056000, 2534 .pa_end = 0x48056fff, 2535 .flags = ADDR_TYPE_RT, 2536 }, 2537 { }, 2538 }; 2539 2540 /* l4_cfg -> dma_system */ 2541 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = { 2542 .master = &omap3xxx_l4_core_hwmod, 2543 .slave = &omap3xxx_dma_system_hwmod, 2544 .clk = "core_l4_ick", 2545 .addr = omap3xxx_dma_system_addrs, 2546 .user = OCP_USER_MPU | OCP_USER_SDMA, 2547 }; 2548 2549 2550 /* l4_core -> mcbsp1 */ 2551 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = { 2552 .master = &omap3xxx_l4_core_hwmod, 2553 .slave = &omap3xxx_mcbsp1_hwmod, 2554 .clk = "mcbsp1_ick", 2555 .user = OCP_USER_MPU | OCP_USER_SDMA, 2556 }; 2557 2558 2559 /* l4_per -> mcbsp2 */ 2560 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = { 2561 .master = &omap3xxx_l4_per_hwmod, 2562 .slave = &omap3xxx_mcbsp2_hwmod, 2563 .clk = "mcbsp2_ick", 2564 .user = OCP_USER_MPU | OCP_USER_SDMA, 2565 }; 2566 2567 2568 /* l4_per -> mcbsp3 */ 2569 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = { 2570 .master = &omap3xxx_l4_per_hwmod, 2571 .slave = &omap3xxx_mcbsp3_hwmod, 2572 .clk = "mcbsp3_ick", 2573 .user = OCP_USER_MPU | OCP_USER_SDMA, 2574 }; 2575 2576 2577 /* l4_per -> mcbsp4 */ 2578 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = { 2579 .master = &omap3xxx_l4_per_hwmod, 2580 .slave = &omap3xxx_mcbsp4_hwmod, 2581 .clk = "mcbsp4_ick", 2582 .user = OCP_USER_MPU | OCP_USER_SDMA, 2583 }; 2584 2585 2586 /* l4_core -> mcbsp5 */ 2587 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = { 2588 .master = &omap3xxx_l4_core_hwmod, 2589 .slave = &omap3xxx_mcbsp5_hwmod, 2590 .clk = "mcbsp5_ick", 2591 .user = OCP_USER_MPU | OCP_USER_SDMA, 2592 }; 2593 2594 2595 /* l4_per -> mcbsp2_sidetone */ 2596 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = { 2597 .master = &omap3xxx_l4_per_hwmod, 2598 .slave = &omap3xxx_mcbsp2_sidetone_hwmod, 2599 .clk = "mcbsp2_ick", 2600 .user = OCP_USER_MPU, 2601 }; 2602 2603 2604 /* l4_per -> mcbsp3_sidetone */ 2605 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = { 2606 .master = &omap3xxx_l4_per_hwmod, 2607 .slave = &omap3xxx_mcbsp3_sidetone_hwmod, 2608 .clk = "mcbsp3_ick", 2609 .user = OCP_USER_MPU, 2610 }; 2611 2612 /* l4_core -> mailbox */ 2613 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = { 2614 .master = &omap3xxx_l4_core_hwmod, 2615 .slave = &omap3xxx_mailbox_hwmod, 2616 .user = OCP_USER_MPU | OCP_USER_SDMA, 2617 }; 2618 2619 /* l4 core -> mcspi1 interface */ 2620 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { 2621 .master = &omap3xxx_l4_core_hwmod, 2622 .slave = &omap34xx_mcspi1, 2623 .clk = "mcspi1_ick", 2624 .user = OCP_USER_MPU | OCP_USER_SDMA, 2625 }; 2626 2627 /* l4 core -> mcspi2 interface */ 2628 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { 2629 .master = &omap3xxx_l4_core_hwmod, 2630 .slave = &omap34xx_mcspi2, 2631 .clk = "mcspi2_ick", 2632 .user = OCP_USER_MPU | OCP_USER_SDMA, 2633 }; 2634 2635 /* l4 core -> mcspi3 interface */ 2636 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { 2637 .master = &omap3xxx_l4_core_hwmod, 2638 .slave = &omap34xx_mcspi3, 2639 .clk = "mcspi3_ick", 2640 .user = OCP_USER_MPU | OCP_USER_SDMA, 2641 }; 2642 2643 /* l4 core -> mcspi4 interface */ 2644 2645 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { 2646 .master = &omap3xxx_l4_core_hwmod, 2647 .slave = &omap34xx_mcspi4, 2648 .clk = "mcspi4_ick", 2649 .user = OCP_USER_MPU | OCP_USER_SDMA, 2650 }; 2651 2652 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = { 2653 .master = &omap3xxx_usb_host_hs_hwmod, 2654 .slave = &omap3xxx_l3_main_hwmod, 2655 .clk = "core_l3_ick", 2656 .user = OCP_USER_MPU, 2657 }; 2658 2659 2660 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = { 2661 .master = &omap3xxx_l4_core_hwmod, 2662 .slave = &omap3xxx_usb_host_hs_hwmod, 2663 .clk = "usbhost_ick", 2664 .user = OCP_USER_MPU | OCP_USER_SDMA, 2665 }; 2666 2667 2668 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = { 2669 .master = &omap3xxx_l4_core_hwmod, 2670 .slave = &omap3xxx_usb_tll_hs_hwmod, 2671 .clk = "usbtll_ick", 2672 .user = OCP_USER_MPU | OCP_USER_SDMA, 2673 }; 2674 2675 /* l4_core -> hdq1w interface */ 2676 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = { 2677 .master = &omap3xxx_l4_core_hwmod, 2678 .slave = &omap3xxx_hdq1w_hwmod, 2679 .clk = "hdq_ick", 2680 .user = OCP_USER_MPU | OCP_USER_SDMA, 2681 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, 2682 }; 2683 2684 /* l4_wkup -> 32ksync_counter */ 2685 2686 2687 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = { 2688 .master = &omap3xxx_l4_wkup_hwmod, 2689 .slave = &omap3xxx_counter_32k_hwmod, 2690 .clk = "omap_32ksync_ick", 2691 .user = OCP_USER_MPU | OCP_USER_SDMA, 2692 }; 2693 2694 /* am35xx has Davinci MDIO & EMAC */ 2695 static struct omap_hwmod_class am35xx_mdio_class = { 2696 .name = "davinci_mdio", 2697 }; 2698 2699 static struct omap_hwmod am35xx_mdio_hwmod = { 2700 .name = "davinci_mdio", 2701 .class = &am35xx_mdio_class, 2702 .flags = HWMOD_NO_IDLEST, 2703 }; 2704 2705 /* 2706 * XXX Should be connected to an IPSS hwmod, not the L3 directly; 2707 * but this will probably require some additional hwmod core support, 2708 * so is left as a future to-do item. 2709 */ 2710 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = { 2711 .master = &am35xx_mdio_hwmod, 2712 .slave = &omap3xxx_l3_main_hwmod, 2713 .clk = "emac_fck", 2714 .user = OCP_USER_MPU, 2715 }; 2716 2717 /* l4_core -> davinci mdio */ 2718 /* 2719 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly; 2720 * but this will probably require some additional hwmod core support, 2721 * so is left as a future to-do item. 2722 */ 2723 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = { 2724 .master = &omap3xxx_l4_core_hwmod, 2725 .slave = &am35xx_mdio_hwmod, 2726 .clk = "emac_fck", 2727 .user = OCP_USER_MPU, 2728 }; 2729 2730 static struct omap_hwmod_class am35xx_emac_class = { 2731 .name = "davinci_emac", 2732 }; 2733 2734 static struct omap_hwmod am35xx_emac_hwmod = { 2735 .name = "davinci_emac", 2736 .class = &am35xx_emac_class, 2737 /* 2738 * According to Mark Greer, the MPU will not return from WFI 2739 * when the EMAC signals an interrupt. 2740 * http://www.spinics.net/lists/arm-kernel/msg174734.html 2741 */ 2742 .flags = (HWMOD_NO_IDLEST | HWMOD_BLOCK_WFI), 2743 }; 2744 2745 /* l3_core -> davinci emac interface */ 2746 /* 2747 * XXX Should be connected to an IPSS hwmod, not the L3 directly; 2748 * but this will probably require some additional hwmod core support, 2749 * so is left as a future to-do item. 2750 */ 2751 static struct omap_hwmod_ocp_if am35xx_emac__l3 = { 2752 .master = &am35xx_emac_hwmod, 2753 .slave = &omap3xxx_l3_main_hwmod, 2754 .clk = "emac_ick", 2755 .user = OCP_USER_MPU, 2756 }; 2757 2758 /* l4_core -> davinci emac */ 2759 /* 2760 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly; 2761 * but this will probably require some additional hwmod core support, 2762 * so is left as a future to-do item. 2763 */ 2764 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = { 2765 .master = &omap3xxx_l4_core_hwmod, 2766 .slave = &am35xx_emac_hwmod, 2767 .clk = "emac_ick", 2768 .user = OCP_USER_MPU, 2769 }; 2770 2771 static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = { 2772 .master = &omap3xxx_l3_main_hwmod, 2773 .slave = &omap3xxx_gpmc_hwmod, 2774 .clk = "core_l3_ick", 2775 .user = OCP_USER_MPU | OCP_USER_SDMA, 2776 }; 2777 2778 /* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */ 2779 static struct omap_hwmod_sysc_fields omap3_sham_sysc_fields = { 2780 .sidle_shift = 4, 2781 .srst_shift = 1, 2782 .autoidle_shift = 0, 2783 }; 2784 2785 static struct omap_hwmod_class_sysconfig omap3_sham_sysc = { 2786 .rev_offs = 0x5c, 2787 .sysc_offs = 0x60, 2788 .syss_offs = 0x64, 2789 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 2790 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 2791 .sysc_fields = &omap3_sham_sysc_fields, 2792 }; 2793 2794 static struct omap_hwmod_class omap3xxx_sham_class = { 2795 .name = "sham", 2796 .sysc = &omap3_sham_sysc, 2797 }; 2798 2799 2800 2801 static struct omap_hwmod omap3xxx_sham_hwmod = { 2802 .name = "sham", 2803 .main_clk = "sha12_ick", 2804 .prcm = { 2805 .omap2 = { 2806 .module_offs = CORE_MOD, 2807 .prcm_reg_id = 1, 2808 .module_bit = OMAP3430_EN_SHA12_SHIFT, 2809 .idlest_reg_id = 1, 2810 .idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT, 2811 }, 2812 }, 2813 .class = &omap3xxx_sham_class, 2814 }; 2815 2816 2817 static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = { 2818 .master = &omap3xxx_l4_core_hwmod, 2819 .slave = &omap3xxx_sham_hwmod, 2820 .clk = "sha12_ick", 2821 .user = OCP_USER_MPU | OCP_USER_SDMA, 2822 }; 2823 2824 /* l4_core -> AES */ 2825 static struct omap_hwmod_sysc_fields omap3xxx_aes_sysc_fields = { 2826 .sidle_shift = 6, 2827 .srst_shift = 1, 2828 .autoidle_shift = 0, 2829 }; 2830 2831 static struct omap_hwmod_class_sysconfig omap3_aes_sysc = { 2832 .rev_offs = 0x44, 2833 .sysc_offs = 0x48, 2834 .syss_offs = 0x4c, 2835 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 2836 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 2837 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 2838 .sysc_fields = &omap3xxx_aes_sysc_fields, 2839 }; 2840 2841 static struct omap_hwmod_class omap3xxx_aes_class = { 2842 .name = "aes", 2843 .sysc = &omap3_aes_sysc, 2844 }; 2845 2846 2847 static struct omap_hwmod omap3xxx_aes_hwmod = { 2848 .name = "aes", 2849 .main_clk = "aes2_ick", 2850 .prcm = { 2851 .omap2 = { 2852 .module_offs = CORE_MOD, 2853 .prcm_reg_id = 1, 2854 .module_bit = OMAP3430_EN_AES2_SHIFT, 2855 .idlest_reg_id = 1, 2856 .idlest_idle_bit = OMAP3430_ST_AES2_SHIFT, 2857 }, 2858 }, 2859 .class = &omap3xxx_aes_class, 2860 }; 2861 2862 2863 static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = { 2864 .master = &omap3xxx_l4_core_hwmod, 2865 .slave = &omap3xxx_aes_hwmod, 2866 .clk = "aes2_ick", 2867 .user = OCP_USER_MPU | OCP_USER_SDMA, 2868 }; 2869 2870 /* 2871 * 'ssi' class 2872 * synchronous serial interface (multichannel and full-duplex serial if) 2873 */ 2874 2875 static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = { 2876 .rev_offs = 0x0000, 2877 .sysc_offs = 0x0010, 2878 .syss_offs = 0x0014, 2879 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_MIDLEMODE | 2880 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), 2881 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 2882 .sysc_fields = &omap_hwmod_sysc_type1, 2883 }; 2884 2885 static struct omap_hwmod_class omap3xxx_ssi_hwmod_class = { 2886 .name = "ssi", 2887 .sysc = &omap34xx_ssi_sysc, 2888 }; 2889 2890 static struct omap_hwmod omap3xxx_ssi_hwmod = { 2891 .name = "ssi", 2892 .class = &omap3xxx_ssi_hwmod_class, 2893 .clkdm_name = "core_l4_clkdm", 2894 .main_clk = "ssi_ssr_fck", 2895 .prcm = { 2896 .omap2 = { 2897 .prcm_reg_id = 1, 2898 .module_bit = OMAP3430_EN_SSI_SHIFT, 2899 .module_offs = CORE_MOD, 2900 .idlest_reg_id = 1, 2901 .idlest_idle_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT, 2902 }, 2903 }, 2904 }; 2905 2906 /* L4 CORE -> SSI */ 2907 static struct omap_hwmod_ocp_if omap3xxx_l4_core__ssi = { 2908 .master = &omap3xxx_l4_core_hwmod, 2909 .slave = &omap3xxx_ssi_hwmod, 2910 .clk = "ssi_ick", 2911 .user = OCP_USER_MPU | OCP_USER_SDMA, 2912 }; 2913 2914 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { 2915 &omap3xxx_l3_main__l4_core, 2916 &omap3xxx_l3_main__l4_per, 2917 &omap3xxx_mpu__l3_main, 2918 &omap3xxx_l3_main__l4_debugss, 2919 &omap3xxx_l4_core__l4_wkup, 2920 &omap3xxx_l4_core__mmc3, 2921 &omap3_l4_core__uart1, 2922 &omap3_l4_core__uart2, 2923 &omap3_l4_per__uart3, 2924 &omap3_l4_core__i2c1, 2925 &omap3_l4_core__i2c2, 2926 &omap3_l4_core__i2c3, 2927 &omap3xxx_l4_wkup__l4_sec, 2928 &omap3xxx_l4_wkup__timer1, 2929 &omap3xxx_l4_per__timer2, 2930 &omap3xxx_l4_per__timer3, 2931 &omap3xxx_l4_per__timer4, 2932 &omap3xxx_l4_per__timer5, 2933 &omap3xxx_l4_per__timer6, 2934 &omap3xxx_l4_per__timer7, 2935 &omap3xxx_l4_per__timer8, 2936 &omap3xxx_l4_per__timer9, 2937 &omap3xxx_l4_core__timer10, 2938 &omap3xxx_l4_core__timer11, 2939 &omap3xxx_l4_wkup__wd_timer2, 2940 &omap3xxx_l4_wkup__gpio1, 2941 &omap3xxx_l4_per__gpio2, 2942 &omap3xxx_l4_per__gpio3, 2943 &omap3xxx_l4_per__gpio4, 2944 &omap3xxx_l4_per__gpio5, 2945 &omap3xxx_l4_per__gpio6, 2946 &omap3xxx_dma_system__l3, 2947 &omap3xxx_l4_core__dma_system, 2948 &omap3xxx_l4_core__mcbsp1, 2949 &omap3xxx_l4_per__mcbsp2, 2950 &omap3xxx_l4_per__mcbsp3, 2951 &omap3xxx_l4_per__mcbsp4, 2952 &omap3xxx_l4_core__mcbsp5, 2953 &omap3xxx_l4_per__mcbsp2_sidetone, 2954 &omap3xxx_l4_per__mcbsp3_sidetone, 2955 &omap34xx_l4_core__mcspi1, 2956 &omap34xx_l4_core__mcspi2, 2957 &omap34xx_l4_core__mcspi3, 2958 &omap34xx_l4_core__mcspi4, 2959 &omap3xxx_l4_wkup__counter_32k, 2960 &omap3xxx_l3_main__gpmc, 2961 NULL, 2962 }; 2963 2964 /* GP-only hwmod links */ 2965 static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = { 2966 &omap3xxx_l4_sec__timer12, 2967 NULL, 2968 }; 2969 2970 static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = { 2971 &omap3xxx_l4_sec__timer12, 2972 NULL, 2973 }; 2974 2975 static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = { 2976 &omap3xxx_l4_sec__timer12, 2977 NULL, 2978 }; 2979 2980 /* crypto hwmod links */ 2981 static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = { 2982 &omap3xxx_l4_core__sham, 2983 NULL, 2984 }; 2985 2986 static struct omap_hwmod_ocp_if *omap34xx_aes_hwmod_ocp_ifs[] __initdata = { 2987 &omap3xxx_l4_core__aes, 2988 NULL, 2989 }; 2990 2991 static struct omap_hwmod_ocp_if *omap36xx_sham_hwmod_ocp_ifs[] __initdata = { 2992 &omap3xxx_l4_core__sham, 2993 NULL 2994 }; 2995 2996 static struct omap_hwmod_ocp_if *omap36xx_aes_hwmod_ocp_ifs[] __initdata = { 2997 &omap3xxx_l4_core__aes, 2998 NULL 2999 }; 3000 3001 /* 3002 * Apparently the SHA/MD5 and AES accelerator IP blocks are 3003 * only present on some AM35xx chips, and no one knows which 3004 * ones. See 3005 * http://www.spinics.net/lists/arm-kernel/msg215466.html So 3006 * if you need these IP blocks on an AM35xx, try uncommenting 3007 * the following lines. 3008 */ 3009 static struct omap_hwmod_ocp_if *am35xx_sham_hwmod_ocp_ifs[] __initdata = { 3010 /* &omap3xxx_l4_core__sham, */ 3011 NULL 3012 }; 3013 3014 static struct omap_hwmod_ocp_if *am35xx_aes_hwmod_ocp_ifs[] __initdata = { 3015 /* &omap3xxx_l4_core__aes, */ 3016 NULL, 3017 }; 3018 3019 /* 3430ES1-only hwmod links */ 3020 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = { 3021 &omap3430es1_dss__l3, 3022 &omap3430es1_l4_core__dss, 3023 NULL, 3024 }; 3025 3026 /* 3430ES2+-only hwmod links */ 3027 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = { 3028 &omap3xxx_dss__l3, 3029 &omap3xxx_l4_core__dss, 3030 &omap3xxx_usbhsotg__l3, 3031 &omap3xxx_l4_core__usbhsotg, 3032 &omap3xxx_usb_host_hs__l3_main_2, 3033 &omap3xxx_l4_core__usb_host_hs, 3034 &omap3xxx_l4_core__usb_tll_hs, 3035 NULL, 3036 }; 3037 3038 /* <= 3430ES3-only hwmod links */ 3039 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = { 3040 &omap3xxx_l4_core__pre_es3_mmc1, 3041 &omap3xxx_l4_core__pre_es3_mmc2, 3042 NULL, 3043 }; 3044 3045 /* 3430ES3+-only hwmod links */ 3046 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = { 3047 &omap3xxx_l4_core__es3plus_mmc1, 3048 &omap3xxx_l4_core__es3plus_mmc2, 3049 NULL, 3050 }; 3051 3052 /* 34xx-only hwmod links (all ES revisions) */ 3053 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = { 3054 &omap3xxx_l3__iva, 3055 &omap34xx_l4_core__sr1, 3056 &omap34xx_l4_core__sr2, 3057 &omap3xxx_l4_core__mailbox, 3058 &omap3xxx_l4_core__hdq1w, 3059 &omap3xxx_sad2d__l3, 3060 &omap3xxx_l4_core__mmu_isp, 3061 &omap3xxx_l3_main__mmu_iva, 3062 &omap3xxx_l4_core__ssi, 3063 NULL, 3064 }; 3065 3066 /* 36xx-only hwmod links (all ES revisions) */ 3067 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = { 3068 &omap3xxx_l3__iva, 3069 &omap36xx_l4_per__uart4, 3070 &omap3xxx_dss__l3, 3071 &omap3xxx_l4_core__dss, 3072 &omap36xx_l4_core__sr1, 3073 &omap36xx_l4_core__sr2, 3074 &omap3xxx_usbhsotg__l3, 3075 &omap3xxx_l4_core__usbhsotg, 3076 &omap3xxx_l4_core__mailbox, 3077 &omap3xxx_usb_host_hs__l3_main_2, 3078 &omap3xxx_l4_core__usb_host_hs, 3079 &omap3xxx_l4_core__usb_tll_hs, 3080 &omap3xxx_l4_core__es3plus_mmc1, 3081 &omap3xxx_l4_core__es3plus_mmc2, 3082 &omap3xxx_l4_core__hdq1w, 3083 &omap3xxx_sad2d__l3, 3084 &omap3xxx_l4_core__mmu_isp, 3085 &omap3xxx_l3_main__mmu_iva, 3086 &omap3xxx_l4_core__ssi, 3087 NULL, 3088 }; 3089 3090 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = { 3091 &omap3xxx_dss__l3, 3092 &omap3xxx_l4_core__dss, 3093 &am35xx_usbhsotg__l3, 3094 &am35xx_l4_core__usbhsotg, 3095 &am35xx_l4_core__uart4, 3096 &omap3xxx_usb_host_hs__l3_main_2, 3097 &omap3xxx_l4_core__usb_host_hs, 3098 &omap3xxx_l4_core__usb_tll_hs, 3099 &omap3xxx_l4_core__es3plus_mmc1, 3100 &omap3xxx_l4_core__es3plus_mmc2, 3101 &omap3xxx_l4_core__hdq1w, 3102 &am35xx_mdio__l3, 3103 &am35xx_l4_core__mdio, 3104 &am35xx_emac__l3, 3105 &am35xx_l4_core__emac, 3106 NULL, 3107 }; 3108 3109 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = { 3110 &omap3xxx_l4_core__dss_dispc, 3111 &omap3xxx_l4_core__dss_dsi1, 3112 &omap3xxx_l4_core__dss_rfbi, 3113 &omap3xxx_l4_core__dss_venc, 3114 NULL, 3115 }; 3116 3117 /** 3118 * omap3xxx_hwmod_is_hs_ip_block_usable - is a security IP block accessible? 3119 * @bus: struct device_node * for the top-level OMAP DT data 3120 * @dev_name: device name used in the DT file 3121 * 3122 * Determine whether a "secure" IP block @dev_name is usable by Linux. 3123 * There doesn't appear to be a 100% reliable way to determine this, 3124 * so we rely on heuristics. If @bus is null, meaning there's no DT 3125 * data, then we only assume the IP block is accessible if the OMAP is 3126 * fused as a 'general-purpose' SoC. If however DT data is present, 3127 * test to see if the IP block is described in the DT data and set to 3128 * 'status = "okay"'. If so then we assume the ODM has configured the 3129 * OMAP firewalls to allow access to the IP block. 3130 * 3131 * Return: 0 if device named @dev_name is not likely to be accessible, 3132 * or 1 if it is likely to be accessible. 3133 */ 3134 static bool __init omap3xxx_hwmod_is_hs_ip_block_usable(struct device_node *bus, 3135 const char *dev_name) 3136 { 3137 struct device_node *node; 3138 bool available; 3139 3140 if (!bus) 3141 return omap_type() == OMAP2_DEVICE_TYPE_GP; 3142 3143 node = of_get_child_by_name(bus, dev_name); 3144 available = of_device_is_available(node); 3145 of_node_put(node); 3146 3147 return available; 3148 } 3149 3150 int __init omap3xxx_hwmod_init(void) 3151 { 3152 int r; 3153 struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL, **h_sham = NULL; 3154 struct omap_hwmod_ocp_if **h_aes = NULL; 3155 struct device_node *bus = NULL; 3156 unsigned int rev; 3157 3158 omap_hwmod_init(); 3159 3160 /* Register hwmod links common to all OMAP3 */ 3161 r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs); 3162 if (r < 0) 3163 return r; 3164 3165 rev = omap_rev(); 3166 3167 /* 3168 * Register hwmod links common to individual OMAP3 families, all 3169 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx) 3170 * All possible revisions should be included in this conditional. 3171 */ 3172 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || 3173 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 || 3174 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) { 3175 h = omap34xx_hwmod_ocp_ifs; 3176 h_gp = omap34xx_gp_hwmod_ocp_ifs; 3177 h_sham = omap34xx_sham_hwmod_ocp_ifs; 3178 h_aes = omap34xx_aes_hwmod_ocp_ifs; 3179 } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) { 3180 h = am35xx_hwmod_ocp_ifs; 3181 h_gp = am35xx_gp_hwmod_ocp_ifs; 3182 h_sham = am35xx_sham_hwmod_ocp_ifs; 3183 h_aes = am35xx_aes_hwmod_ocp_ifs; 3184 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 || 3185 rev == OMAP3630_REV_ES1_2) { 3186 h = omap36xx_hwmod_ocp_ifs; 3187 h_gp = omap36xx_gp_hwmod_ocp_ifs; 3188 h_sham = omap36xx_sham_hwmod_ocp_ifs; 3189 h_aes = omap36xx_aes_hwmod_ocp_ifs; 3190 } else { 3191 WARN(1, "OMAP3 hwmod family init: unknown chip type\n"); 3192 return -EINVAL; 3193 } 3194 3195 r = omap_hwmod_register_links(h); 3196 if (r < 0) 3197 return r; 3198 3199 /* Register GP-only hwmod links. */ 3200 if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) { 3201 r = omap_hwmod_register_links(h_gp); 3202 if (r < 0) 3203 return r; 3204 } 3205 3206 /* 3207 * Register crypto hwmod links only if they are not disabled in DT. 3208 * If DT information is missing, enable them only for GP devices. 3209 */ 3210 3211 if (of_have_populated_dt()) 3212 bus = of_find_node_by_name(NULL, "ocp"); 3213 3214 if (h_sham && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "sham")) { 3215 r = omap_hwmod_register_links(h_sham); 3216 if (r < 0) { 3217 of_node_put(bus); 3218 return r; 3219 } 3220 } 3221 3222 if (h_aes && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "aes")) { 3223 r = omap_hwmod_register_links(h_aes); 3224 if (r < 0) { 3225 of_node_put(bus); 3226 return r; 3227 } 3228 } 3229 of_node_put(bus); 3230 3231 /* 3232 * Register hwmod links specific to certain ES levels of a 3233 * particular family of silicon (e.g., 34xx ES1.0) 3234 */ 3235 h = NULL; 3236 if (rev == OMAP3430_REV_ES1_0) { 3237 h = omap3430es1_hwmod_ocp_ifs; 3238 } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 || 3239 rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || 3240 rev == OMAP3430_REV_ES3_1_2) { 3241 h = omap3430es2plus_hwmod_ocp_ifs; 3242 } 3243 3244 if (h) { 3245 r = omap_hwmod_register_links(h); 3246 if (r < 0) 3247 return r; 3248 } 3249 3250 h = NULL; 3251 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 || 3252 rev == OMAP3430_REV_ES2_1) { 3253 h = omap3430_pre_es3_hwmod_ocp_ifs; 3254 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 || 3255 rev == OMAP3430_REV_ES3_1_2) { 3256 h = omap3430_es3plus_hwmod_ocp_ifs; 3257 } 3258 3259 if (h) 3260 r = omap_hwmod_register_links(h); 3261 if (r < 0) 3262 return r; 3263 3264 /* 3265 * DSS code presumes that dss_core hwmod is handled first, 3266 * _before_ any other DSS related hwmods so register common 3267 * DSS hwmod links last to ensure that dss_core is already 3268 * registered. Otherwise some change things may happen, for 3269 * ex. if dispc is handled before dss_core and DSS is enabled 3270 * in bootloader DISPC will be reset with outputs enabled 3271 * which sometimes leads to unrecoverable L3 error. XXX The 3272 * long-term fix to this is to ensure hwmods are set up in 3273 * dependency order in the hwmod core code. 3274 */ 3275 r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs); 3276 3277 return r; 3278 } 3279