1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
4  *
5  * Copyright (C) 2009-2011 Nokia Corporation
6  * Copyright (C) 2012 Texas Instruments, Inc.
7  * Paul Walmsley
8  *
9  * XXX handle crossbar/shared link difference for L3?
10  * XXX these should be marked initdata for multi-OMAP kernels
11  */
12 
13 #include <linux/platform_data/i2c-omap.h>
14 #include <linux/platform_data/hsmmc-omap.h>
15 
16 #include "omap_hwmod.h"
17 #include "l3_2xxx.h"
18 
19 #include "soc.h"
20 #include "omap_hwmod_common_data.h"
21 #include "prm-regbits-24xx.h"
22 #include "cm-regbits-24xx.h"
23 #include "i2c.h"
24 #include "wd_timer.h"
25 
26 /*
27  * OMAP2430 hardware module integration data
28  *
29  * All of the data in this section should be autogeneratable from the
30  * TI hardware database or other technical documentation.  Data that
31  * is driver-specific or driver-kernel integration-specific belongs
32  * elsewhere.
33  */
34 
35 /*
36  * IP blocks
37  */
38 
39 /* IVA2 (IVA2) */
40 static struct omap_hwmod_rst_info omap2430_iva_resets[] = {
41 	{ .name = "logic", .rst_shift = 0 },
42 	{ .name = "mmu", .rst_shift = 1 },
43 };
44 
45 static struct omap_hwmod omap2430_iva_hwmod = {
46 	.name		= "iva",
47 	.class		= &iva_hwmod_class,
48 	.clkdm_name	= "dsp_clkdm",
49 	.rst_lines	= omap2430_iva_resets,
50 	.rst_lines_cnt	= ARRAY_SIZE(omap2430_iva_resets),
51 	.main_clk	= "dsp_fck",
52 };
53 
54 /* I2C common */
55 static struct omap_hwmod_class_sysconfig i2c_sysc = {
56 	.rev_offs	= 0x00,
57 	.sysc_offs	= 0x20,
58 	.syss_offs	= 0x10,
59 	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
60 			   SYSS_HAS_RESET_STATUS),
61 	.sysc_fields	= &omap_hwmod_sysc_type1,
62 };
63 
64 static struct omap_hwmod_class i2c_class = {
65 	.name		= "i2c",
66 	.sysc		= &i2c_sysc,
67 	.reset		= &omap_i2c_reset,
68 };
69 
70 /* I2C1 */
71 static struct omap_hwmod omap2430_i2c1_hwmod = {
72 	.name		= "i2c1",
73 	.flags		= HWMOD_16BIT_REG,
74 	.main_clk	= "i2chs1_fck",
75 	.prcm		= {
76 		.omap2 = {
77 			/*
78 			 * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
79 			 * I2CHS IP's do not follow the usual pattern.
80 			 * prcm_reg_id alone cannot be used to program
81 			 * the iclk and fclk. Needs to be handled using
82 			 * additional flags when clk handling is moved
83 			 * to hwmod framework.
84 			 */
85 			.module_offs = CORE_MOD,
86 			.idlest_reg_id = 1,
87 			.idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
88 		},
89 	},
90 	.class		= &i2c_class,
91 };
92 
93 /* I2C2 */
94 static struct omap_hwmod omap2430_i2c2_hwmod = {
95 	.name		= "i2c2",
96 	.flags		= HWMOD_16BIT_REG,
97 	.main_clk	= "i2chs2_fck",
98 	.prcm		= {
99 		.omap2 = {
100 			.module_offs = CORE_MOD,
101 			.idlest_reg_id = 1,
102 			.idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
103 		},
104 	},
105 	.class		= &i2c_class,
106 };
107 
108 /* gpio5 */
109 static struct omap_hwmod omap2430_gpio5_hwmod = {
110 	.name		= "gpio5",
111 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
112 	.main_clk	= "gpio5_fck",
113 	.prcm		= {
114 		.omap2 = {
115 			.module_offs = CORE_MOD,
116 			.idlest_reg_id = 2,
117 			.idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
118 		},
119 	},
120 	.class		= &omap2xxx_gpio_hwmod_class,
121 };
122 
123 /* mailbox */
124 static struct omap_hwmod omap2430_mailbox_hwmod = {
125 	.name		= "mailbox",
126 	.class		= &omap2xxx_mailbox_hwmod_class,
127 	.main_clk	= "mailboxes_ick",
128 	.prcm		= {
129 		.omap2 = {
130 			.module_offs = CORE_MOD,
131 			.idlest_reg_id = 1,
132 			.idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
133 		},
134 	},
135 };
136 
137 /* mcspi3 */
138 static struct omap_hwmod omap2430_mcspi3_hwmod = {
139 	.name		= "mcspi3",
140 	.main_clk	= "mcspi3_fck",
141 	.prcm		= {
142 		.omap2 = {
143 			.module_offs = CORE_MOD,
144 			.idlest_reg_id = 2,
145 			.idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
146 		},
147 	},
148 	.class		= &omap2xxx_mcspi_class,
149 };
150 
151 /* usbhsotg */
152 static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
153 	.rev_offs	= 0x0400,
154 	.sysc_offs	= 0x0404,
155 	.syss_offs	= 0x0408,
156 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
157 			  SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
158 			  SYSC_HAS_AUTOIDLE),
159 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
160 			  MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
161 	.sysc_fields	= &omap_hwmod_sysc_type1,
162 };
163 
164 static struct omap_hwmod_class usbotg_class = {
165 	.name = "usbotg",
166 	.sysc = &omap2430_usbhsotg_sysc,
167 };
168 
169 /* usb_otg_hs */
170 static struct omap_hwmod omap2430_usbhsotg_hwmod = {
171 	.name		= "usb_otg_hs",
172 	.main_clk	= "usbhs_ick",
173 	.prcm		= {
174 		.omap2 = {
175 			.module_offs = CORE_MOD,
176 			.idlest_reg_id = 1,
177 			.idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
178 		},
179 	},
180 	.class		= &usbotg_class,
181 	/*
182 	 * Erratum ID: i479  idle_req / idle_ack mechanism potentially
183 	 * broken when autoidle is enabled
184 	 * workaround is to disable the autoidle bit at module level.
185 	 */
186 	.flags		= HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
187 				| HWMOD_SWSUP_MSTANDBY,
188 };
189 
190 /*
191  * 'mcbsp' class
192  * multi channel buffered serial port controller
193  */
194 
195 static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
196 	.rev_offs	= 0x007C,
197 	.sysc_offs	= 0x008C,
198 	.sysc_flags	= (SYSC_HAS_SOFTRESET),
199 	.sysc_fields    = &omap_hwmod_sysc_type1,
200 };
201 
202 static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
203 	.name = "mcbsp",
204 	.sysc = &omap2430_mcbsp_sysc,
205 };
206 
207 static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
208 	{ .role = "pad_fck", .clk = "mcbsp_clks" },
209 	{ .role = "prcm_fck", .clk = "func_96m_ck" },
210 };
211 
212 /* mcbsp1 */
213 static struct omap_hwmod omap2430_mcbsp1_hwmod = {
214 	.name		= "mcbsp1",
215 	.class		= &omap2430_mcbsp_hwmod_class,
216 	.main_clk	= "mcbsp1_fck",
217 	.prcm		= {
218 		.omap2 = {
219 			.module_offs = CORE_MOD,
220 			.idlest_reg_id = 1,
221 			.idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
222 		},
223 	},
224 	.opt_clks	= mcbsp_opt_clks,
225 	.opt_clks_cnt	= ARRAY_SIZE(mcbsp_opt_clks),
226 };
227 
228 /* mcbsp2 */
229 static struct omap_hwmod omap2430_mcbsp2_hwmod = {
230 	.name		= "mcbsp2",
231 	.class		= &omap2430_mcbsp_hwmod_class,
232 	.main_clk	= "mcbsp2_fck",
233 	.prcm		= {
234 		.omap2 = {
235 			.module_offs = CORE_MOD,
236 			.idlest_reg_id = 1,
237 			.idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
238 		},
239 	},
240 	.opt_clks	= mcbsp_opt_clks,
241 	.opt_clks_cnt	= ARRAY_SIZE(mcbsp_opt_clks),
242 };
243 
244 /* mcbsp3 */
245 static struct omap_hwmod omap2430_mcbsp3_hwmod = {
246 	.name		= "mcbsp3",
247 	.class		= &omap2430_mcbsp_hwmod_class,
248 	.main_clk	= "mcbsp3_fck",
249 	.prcm		= {
250 		.omap2 = {
251 			.module_offs = CORE_MOD,
252 			.idlest_reg_id = 2,
253 			.idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
254 		},
255 	},
256 	.opt_clks	= mcbsp_opt_clks,
257 	.opt_clks_cnt	= ARRAY_SIZE(mcbsp_opt_clks),
258 };
259 
260 /* mcbsp4 */
261 static struct omap_hwmod omap2430_mcbsp4_hwmod = {
262 	.name		= "mcbsp4",
263 	.class		= &omap2430_mcbsp_hwmod_class,
264 	.main_clk	= "mcbsp4_fck",
265 	.prcm		= {
266 		.omap2 = {
267 			.module_offs = CORE_MOD,
268 			.idlest_reg_id = 2,
269 			.idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
270 		},
271 	},
272 	.opt_clks	= mcbsp_opt_clks,
273 	.opt_clks_cnt	= ARRAY_SIZE(mcbsp_opt_clks),
274 };
275 
276 /* mcbsp5 */
277 static struct omap_hwmod omap2430_mcbsp5_hwmod = {
278 	.name		= "mcbsp5",
279 	.class		= &omap2430_mcbsp_hwmod_class,
280 	.main_clk	= "mcbsp5_fck",
281 	.prcm		= {
282 		.omap2 = {
283 			.module_offs = CORE_MOD,
284 			.idlest_reg_id = 2,
285 			.idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
286 		},
287 	},
288 	.opt_clks	= mcbsp_opt_clks,
289 	.opt_clks_cnt	= ARRAY_SIZE(mcbsp_opt_clks),
290 };
291 
292 /* MMC/SD/SDIO common */
293 static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
294 	.rev_offs	= 0x1fc,
295 	.sysc_offs	= 0x10,
296 	.syss_offs	= 0x14,
297 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
298 			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
299 			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
300 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
301 	.sysc_fields    = &omap_hwmod_sysc_type1,
302 };
303 
304 static struct omap_hwmod_class omap2430_mmc_class = {
305 	.name = "mmc",
306 	.sysc = &omap2430_mmc_sysc,
307 };
308 
309 /* MMC/SD/SDIO1 */
310 static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
311 	{ .role = "dbck", .clk = "mmchsdb1_fck" },
312 };
313 
314 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
315 	.flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
316 };
317 
318 static struct omap_hwmod omap2430_mmc1_hwmod = {
319 	.name		= "mmc1",
320 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
321 	.opt_clks	= omap2430_mmc1_opt_clks,
322 	.opt_clks_cnt	= ARRAY_SIZE(omap2430_mmc1_opt_clks),
323 	.main_clk	= "mmchs1_fck",
324 	.prcm		= {
325 		.omap2 = {
326 			.module_offs = CORE_MOD,
327 			.idlest_reg_id = 2,
328 			.idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
329 		},
330 	},
331 	.dev_attr	= &mmc1_dev_attr,
332 	.class		= &omap2430_mmc_class,
333 };
334 
335 /* MMC/SD/SDIO2 */
336 static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
337 	{ .role = "dbck", .clk = "mmchsdb2_fck" },
338 };
339 
340 static struct omap_hwmod omap2430_mmc2_hwmod = {
341 	.name		= "mmc2",
342 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
343 	.opt_clks	= omap2430_mmc2_opt_clks,
344 	.opt_clks_cnt	= ARRAY_SIZE(omap2430_mmc2_opt_clks),
345 	.main_clk	= "mmchs2_fck",
346 	.prcm		= {
347 		.omap2 = {
348 			.module_offs = CORE_MOD,
349 			.idlest_reg_id = 2,
350 			.idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
351 		},
352 	},
353 	.class		= &omap2430_mmc_class,
354 };
355 
356 /* HDQ1W/1-wire */
357 static struct omap_hwmod omap2430_hdq1w_hwmod = {
358 	.name		= "hdq1w",
359 	.main_clk	= "hdq_fck",
360 	.prcm		= {
361 		.omap2 = {
362 			.module_offs = CORE_MOD,
363 			.idlest_reg_id = 1,
364 			.idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
365 		},
366 	},
367 	.class		= &omap2_hdq1w_class,
368 };
369 
370 /*
371  * interfaces
372  */
373 
374 /* L3 -> L4_CORE interface */
375 /* l3_core -> usbhsotg  interface */
376 static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
377 	.master		= &omap2430_usbhsotg_hwmod,
378 	.slave		= &omap2xxx_l3_main_hwmod,
379 	.clk		= "core_l3_ck",
380 	.user		= OCP_USER_MPU,
381 };
382 
383 /* L4 CORE -> I2C1 interface */
384 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
385 	.master		= &omap2xxx_l4_core_hwmod,
386 	.slave		= &omap2430_i2c1_hwmod,
387 	.clk		= "i2c1_ick",
388 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
389 };
390 
391 /* L4 CORE -> I2C2 interface */
392 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
393 	.master		= &omap2xxx_l4_core_hwmod,
394 	.slave		= &omap2430_i2c2_hwmod,
395 	.clk		= "i2c2_ick",
396 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
397 };
398 
399 /*  l4_core ->usbhsotg  interface */
400 static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
401 	.master		= &omap2xxx_l4_core_hwmod,
402 	.slave		= &omap2430_usbhsotg_hwmod,
403 	.clk		= "usb_l4_ick",
404 	.user		= OCP_USER_MPU,
405 };
406 
407 /* L4 CORE -> MMC1 interface */
408 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
409 	.master		= &omap2xxx_l4_core_hwmod,
410 	.slave		= &omap2430_mmc1_hwmod,
411 	.clk		= "mmchs1_ick",
412 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
413 };
414 
415 /* L4 CORE -> MMC2 interface */
416 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
417 	.master		= &omap2xxx_l4_core_hwmod,
418 	.slave		= &omap2430_mmc2_hwmod,
419 	.clk		= "mmchs2_ick",
420 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
421 };
422 
423 /* l4 core -> mcspi3 interface */
424 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
425 	.master		= &omap2xxx_l4_core_hwmod,
426 	.slave		= &omap2430_mcspi3_hwmod,
427 	.clk		= "mcspi3_ick",
428 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
429 };
430 
431 /* IVA2 <- L3 interface */
432 static struct omap_hwmod_ocp_if omap2430_l3__iva = {
433 	.master		= &omap2xxx_l3_main_hwmod,
434 	.slave		= &omap2430_iva_hwmod,
435 	.clk		= "core_l3_ck",
436 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
437 };
438 
439 /* l4_wkup -> wd_timer2 */
440 static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
441 	.master		= &omap2xxx_l4_wkup_hwmod,
442 	.slave		= &omap2xxx_wd_timer2_hwmod,
443 	.clk		= "mpu_wdt_ick",
444 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
445 };
446 
447 /* l4_wkup -> gpio1 */
448 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
449 	.master		= &omap2xxx_l4_wkup_hwmod,
450 	.slave		= &omap2xxx_gpio1_hwmod,
451 	.clk		= "gpios_ick",
452 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
453 };
454 
455 /* l4_wkup -> gpio2 */
456 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
457 	.master		= &omap2xxx_l4_wkup_hwmod,
458 	.slave		= &omap2xxx_gpio2_hwmod,
459 	.clk		= "gpios_ick",
460 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
461 };
462 
463 /* l4_wkup -> gpio3 */
464 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
465 	.master		= &omap2xxx_l4_wkup_hwmod,
466 	.slave		= &omap2xxx_gpio3_hwmod,
467 	.clk		= "gpios_ick",
468 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
469 };
470 
471 /* l4_wkup -> gpio4 */
472 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
473 	.master		= &omap2xxx_l4_wkup_hwmod,
474 	.slave		= &omap2xxx_gpio4_hwmod,
475 	.clk		= "gpios_ick",
476 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
477 };
478 
479 /* l4_core -> gpio5 */
480 static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
481 	.master		= &omap2xxx_l4_core_hwmod,
482 	.slave		= &omap2430_gpio5_hwmod,
483 	.clk		= "gpio5_ick",
484 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
485 };
486 
487 /* l4_core -> mailbox */
488 static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
489 	.master		= &omap2xxx_l4_core_hwmod,
490 	.slave		= &omap2430_mailbox_hwmod,
491 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
492 };
493 
494 /* l4_core -> mcbsp1 */
495 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
496 	.master		= &omap2xxx_l4_core_hwmod,
497 	.slave		= &omap2430_mcbsp1_hwmod,
498 	.clk		= "mcbsp1_ick",
499 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
500 };
501 
502 /* l4_core -> mcbsp2 */
503 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
504 	.master		= &omap2xxx_l4_core_hwmod,
505 	.slave		= &omap2430_mcbsp2_hwmod,
506 	.clk		= "mcbsp2_ick",
507 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
508 };
509 
510 /* l4_core -> mcbsp3 */
511 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
512 	.master		= &omap2xxx_l4_core_hwmod,
513 	.slave		= &omap2430_mcbsp3_hwmod,
514 	.clk		= "mcbsp3_ick",
515 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
516 };
517 
518 /* l4_core -> mcbsp4 */
519 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
520 	.master		= &omap2xxx_l4_core_hwmod,
521 	.slave		= &omap2430_mcbsp4_hwmod,
522 	.clk		= "mcbsp4_ick",
523 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
524 };
525 
526 /* l4_core -> mcbsp5 */
527 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
528 	.master		= &omap2xxx_l4_core_hwmod,
529 	.slave		= &omap2430_mcbsp5_hwmod,
530 	.clk		= "mcbsp5_ick",
531 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
532 };
533 
534 /* l4_core -> hdq1w */
535 static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = {
536 	.master		= &omap2xxx_l4_core_hwmod,
537 	.slave		= &omap2430_hdq1w_hwmod,
538 	.clk		= "hdq_ick",
539 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
540 	.flags		= OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
541 };
542 
543 static struct omap_hwmod_ocp_if omap2430_l3__gpmc = {
544 	.master		= &omap2xxx_l3_main_hwmod,
545 	.slave		= &omap2xxx_gpmc_hwmod,
546 	.clk		= "core_l3_ck",
547 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
548 };
549 
550 static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
551 	&omap2xxx_l3_main__l4_core,
552 	&omap2xxx_mpu__l3_main,
553 	&omap2xxx_dss__l3,
554 	&omap2430_usbhsotg__l3,
555 	&omap2430_l4_core__i2c1,
556 	&omap2430_l4_core__i2c2,
557 	&omap2xxx_l4_core__l4_wkup,
558 	&omap2_l4_core__uart1,
559 	&omap2_l4_core__uart2,
560 	&omap2_l4_core__uart3,
561 	&omap2430_l4_core__usbhsotg,
562 	&omap2430_l4_core__mmc1,
563 	&omap2430_l4_core__mmc2,
564 	&omap2xxx_l4_core__mcspi1,
565 	&omap2xxx_l4_core__mcspi2,
566 	&omap2430_l4_core__mcspi3,
567 	&omap2430_l3__iva,
568 	&omap2xxx_l4_core__timer3,
569 	&omap2xxx_l4_core__timer4,
570 	&omap2xxx_l4_core__timer5,
571 	&omap2xxx_l4_core__timer6,
572 	&omap2xxx_l4_core__timer7,
573 	&omap2xxx_l4_core__timer8,
574 	&omap2xxx_l4_core__timer9,
575 	&omap2xxx_l4_core__timer10,
576 	&omap2xxx_l4_core__timer11,
577 	&omap2xxx_l4_core__timer12,
578 	&omap2430_l4_wkup__wd_timer2,
579 	&omap2xxx_l4_core__dss,
580 	&omap2xxx_l4_core__dss_dispc,
581 	&omap2xxx_l4_core__dss_rfbi,
582 	&omap2xxx_l4_core__dss_venc,
583 	&omap2430_l4_wkup__gpio1,
584 	&omap2430_l4_wkup__gpio2,
585 	&omap2430_l4_wkup__gpio3,
586 	&omap2430_l4_wkup__gpio4,
587 	&omap2430_l4_core__gpio5,
588 	&omap2430_l4_core__mailbox,
589 	&omap2430_l4_core__mcbsp1,
590 	&omap2430_l4_core__mcbsp2,
591 	&omap2430_l4_core__mcbsp3,
592 	&omap2430_l4_core__mcbsp4,
593 	&omap2430_l4_core__mcbsp5,
594 	&omap2430_l4_core__hdq1w,
595 	&omap2xxx_l4_core__rng,
596 	&omap2xxx_l4_core__sham,
597 	&omap2xxx_l4_core__aes,
598 	&omap2430_l3__gpmc,
599 	NULL,
600 };
601 
602 int __init omap2430_hwmod_init(void)
603 {
604 	omap_hwmod_init();
605 	return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs);
606 }
607