1 /* 2 * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips 3 * 4 * Copyright (C) 2009-2011 Nokia Corporation 5 * Copyright (C) 2012 Texas Instruments, Inc. 6 * Paul Walmsley 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * XXX handle crossbar/shared link difference for L3? 13 * XXX these should be marked initdata for multi-OMAP kernels 14 */ 15 16 #include <linux/i2c-omap.h> 17 #include <linux/platform_data/asoc-ti-mcbsp.h> 18 #include <linux/platform_data/hsmmc-omap.h> 19 #include <linux/platform_data/spi-omap2-mcspi.h> 20 #include <linux/omap-dma.h> 21 #include <plat/dmtimer.h> 22 23 #include "omap_hwmod.h" 24 #include "l3_2xxx.h" 25 26 #include "soc.h" 27 #include "omap_hwmod_common_data.h" 28 #include "prm-regbits-24xx.h" 29 #include "cm-regbits-24xx.h" 30 #include "i2c.h" 31 #include "wd_timer.h" 32 33 /* 34 * OMAP2430 hardware module integration data 35 * 36 * All of the data in this section should be autogeneratable from the 37 * TI hardware database or other technical documentation. Data that 38 * is driver-specific or driver-kernel integration-specific belongs 39 * elsewhere. 40 */ 41 42 /* 43 * IP blocks 44 */ 45 46 /* IVA2 (IVA2) */ 47 static struct omap_hwmod_rst_info omap2430_iva_resets[] = { 48 { .name = "logic", .rst_shift = 0 }, 49 { .name = "mmu", .rst_shift = 1 }, 50 }; 51 52 static struct omap_hwmod omap2430_iva_hwmod = { 53 .name = "iva", 54 .class = &iva_hwmod_class, 55 .clkdm_name = "dsp_clkdm", 56 .rst_lines = omap2430_iva_resets, 57 .rst_lines_cnt = ARRAY_SIZE(omap2430_iva_resets), 58 .main_clk = "dsp_fck", 59 }; 60 61 /* I2C common */ 62 static struct omap_hwmod_class_sysconfig i2c_sysc = { 63 .rev_offs = 0x00, 64 .sysc_offs = 0x20, 65 .syss_offs = 0x10, 66 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | 67 SYSS_HAS_RESET_STATUS), 68 .sysc_fields = &omap_hwmod_sysc_type1, 69 }; 70 71 static struct omap_hwmod_class i2c_class = { 72 .name = "i2c", 73 .sysc = &i2c_sysc, 74 .rev = OMAP_I2C_IP_VERSION_1, 75 .reset = &omap_i2c_reset, 76 }; 77 78 static struct omap_i2c_dev_attr i2c_dev_attr = { 79 .fifo_depth = 8, /* bytes */ 80 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2 | 81 OMAP_I2C_FLAG_FORCE_19200_INT_CLK, 82 }; 83 84 /* I2C1 */ 85 static struct omap_hwmod omap2430_i2c1_hwmod = { 86 .name = "i2c1", 87 .flags = HWMOD_16BIT_REG, 88 .main_clk = "i2chs1_fck", 89 .prcm = { 90 .omap2 = { 91 /* 92 * NOTE: The CM_FCLKEN* and CM_ICLKEN* for 93 * I2CHS IP's do not follow the usual pattern. 94 * prcm_reg_id alone cannot be used to program 95 * the iclk and fclk. Needs to be handled using 96 * additional flags when clk handling is moved 97 * to hwmod framework. 98 */ 99 .module_offs = CORE_MOD, 100 .idlest_reg_id = 1, 101 .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT, 102 }, 103 }, 104 .class = &i2c_class, 105 .dev_attr = &i2c_dev_attr, 106 }; 107 108 /* I2C2 */ 109 static struct omap_hwmod omap2430_i2c2_hwmod = { 110 .name = "i2c2", 111 .flags = HWMOD_16BIT_REG, 112 .main_clk = "i2chs2_fck", 113 .prcm = { 114 .omap2 = { 115 .module_offs = CORE_MOD, 116 .idlest_reg_id = 1, 117 .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT, 118 }, 119 }, 120 .class = &i2c_class, 121 .dev_attr = &i2c_dev_attr, 122 }; 123 124 /* gpio5 */ 125 static struct omap_hwmod omap2430_gpio5_hwmod = { 126 .name = "gpio5", 127 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 128 .main_clk = "gpio5_fck", 129 .prcm = { 130 .omap2 = { 131 .module_offs = CORE_MOD, 132 .idlest_reg_id = 2, 133 .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT, 134 }, 135 }, 136 .class = &omap2xxx_gpio_hwmod_class, 137 .dev_attr = &omap2xxx_gpio_dev_attr, 138 }; 139 140 /* dma attributes */ 141 static struct omap_dma_dev_attr dma_dev_attr = { 142 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | 143 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, 144 .lch_count = 32, 145 }; 146 147 static struct omap_hwmod omap2430_dma_system_hwmod = { 148 .name = "dma", 149 .class = &omap2xxx_dma_hwmod_class, 150 .main_clk = "core_l3_ck", 151 .dev_attr = &dma_dev_attr, 152 .flags = HWMOD_NO_IDLEST, 153 }; 154 155 /* mailbox */ 156 static struct omap_hwmod omap2430_mailbox_hwmod = { 157 .name = "mailbox", 158 .class = &omap2xxx_mailbox_hwmod_class, 159 .main_clk = "mailboxes_ick", 160 .prcm = { 161 .omap2 = { 162 .module_offs = CORE_MOD, 163 .idlest_reg_id = 1, 164 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, 165 }, 166 }, 167 }; 168 169 /* mcspi3 */ 170 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { 171 .num_chipselect = 2, 172 }; 173 174 static struct omap_hwmod omap2430_mcspi3_hwmod = { 175 .name = "mcspi3", 176 .main_clk = "mcspi3_fck", 177 .prcm = { 178 .omap2 = { 179 .module_offs = CORE_MOD, 180 .idlest_reg_id = 2, 181 .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT, 182 }, 183 }, 184 .class = &omap2xxx_mcspi_class, 185 .dev_attr = &omap_mcspi3_dev_attr, 186 }; 187 188 /* usbhsotg */ 189 static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = { 190 .rev_offs = 0x0400, 191 .sysc_offs = 0x0404, 192 .syss_offs = 0x0408, 193 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| 194 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 195 SYSC_HAS_AUTOIDLE), 196 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 197 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 198 .sysc_fields = &omap_hwmod_sysc_type1, 199 }; 200 201 static struct omap_hwmod_class usbotg_class = { 202 .name = "usbotg", 203 .sysc = &omap2430_usbhsotg_sysc, 204 }; 205 206 /* usb_otg_hs */ 207 static struct omap_hwmod omap2430_usbhsotg_hwmod = { 208 .name = "usb_otg_hs", 209 .main_clk = "usbhs_ick", 210 .prcm = { 211 .omap2 = { 212 .module_offs = CORE_MOD, 213 .idlest_reg_id = 1, 214 .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT, 215 }, 216 }, 217 .class = &usbotg_class, 218 /* 219 * Erratum ID: i479 idle_req / idle_ack mechanism potentially 220 * broken when autoidle is enabled 221 * workaround is to disable the autoidle bit at module level. 222 */ 223 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE 224 | HWMOD_SWSUP_MSTANDBY, 225 }; 226 227 /* 228 * 'mcbsp' class 229 * multi channel buffered serial port controller 230 */ 231 232 static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = { 233 .rev_offs = 0x007C, 234 .sysc_offs = 0x008C, 235 .sysc_flags = (SYSC_HAS_SOFTRESET), 236 .sysc_fields = &omap_hwmod_sysc_type1, 237 }; 238 239 static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = { 240 .name = "mcbsp", 241 .sysc = &omap2430_mcbsp_sysc, 242 .rev = MCBSP_CONFIG_TYPE2, 243 }; 244 245 static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = { 246 { .role = "pad_fck", .clk = "mcbsp_clks" }, 247 { .role = "prcm_fck", .clk = "func_96m_ck" }, 248 }; 249 250 /* mcbsp1 */ 251 static struct omap_hwmod omap2430_mcbsp1_hwmod = { 252 .name = "mcbsp1", 253 .class = &omap2430_mcbsp_hwmod_class, 254 .main_clk = "mcbsp1_fck", 255 .prcm = { 256 .omap2 = { 257 .module_offs = CORE_MOD, 258 .idlest_reg_id = 1, 259 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, 260 }, 261 }, 262 .opt_clks = mcbsp_opt_clks, 263 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), 264 }; 265 266 /* mcbsp2 */ 267 static struct omap_hwmod omap2430_mcbsp2_hwmod = { 268 .name = "mcbsp2", 269 .class = &omap2430_mcbsp_hwmod_class, 270 .main_clk = "mcbsp2_fck", 271 .prcm = { 272 .omap2 = { 273 .module_offs = CORE_MOD, 274 .idlest_reg_id = 1, 275 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, 276 }, 277 }, 278 .opt_clks = mcbsp_opt_clks, 279 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), 280 }; 281 282 /* mcbsp3 */ 283 static struct omap_hwmod omap2430_mcbsp3_hwmod = { 284 .name = "mcbsp3", 285 .class = &omap2430_mcbsp_hwmod_class, 286 .main_clk = "mcbsp3_fck", 287 .prcm = { 288 .omap2 = { 289 .module_offs = CORE_MOD, 290 .idlest_reg_id = 2, 291 .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT, 292 }, 293 }, 294 .opt_clks = mcbsp_opt_clks, 295 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), 296 }; 297 298 /* mcbsp4 */ 299 static struct omap_hwmod omap2430_mcbsp4_hwmod = { 300 .name = "mcbsp4", 301 .class = &omap2430_mcbsp_hwmod_class, 302 .main_clk = "mcbsp4_fck", 303 .prcm = { 304 .omap2 = { 305 .module_offs = CORE_MOD, 306 .idlest_reg_id = 2, 307 .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT, 308 }, 309 }, 310 .opt_clks = mcbsp_opt_clks, 311 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), 312 }; 313 314 /* mcbsp5 */ 315 static struct omap_hwmod omap2430_mcbsp5_hwmod = { 316 .name = "mcbsp5", 317 .class = &omap2430_mcbsp_hwmod_class, 318 .main_clk = "mcbsp5_fck", 319 .prcm = { 320 .omap2 = { 321 .module_offs = CORE_MOD, 322 .idlest_reg_id = 2, 323 .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT, 324 }, 325 }, 326 .opt_clks = mcbsp_opt_clks, 327 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), 328 }; 329 330 /* MMC/SD/SDIO common */ 331 static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = { 332 .rev_offs = 0x1fc, 333 .sysc_offs = 0x10, 334 .syss_offs = 0x14, 335 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 336 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 337 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 338 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 339 .sysc_fields = &omap_hwmod_sysc_type1, 340 }; 341 342 static struct omap_hwmod_class omap2430_mmc_class = { 343 .name = "mmc", 344 .sysc = &omap2430_mmc_sysc, 345 }; 346 347 /* MMC/SD/SDIO1 */ 348 static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = { 349 { .role = "dbck", .clk = "mmchsdb1_fck" }, 350 }; 351 352 static struct omap_hsmmc_dev_attr mmc1_dev_attr = { 353 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, 354 }; 355 356 static struct omap_hwmod omap2430_mmc1_hwmod = { 357 .name = "mmc1", 358 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 359 .opt_clks = omap2430_mmc1_opt_clks, 360 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks), 361 .main_clk = "mmchs1_fck", 362 .prcm = { 363 .omap2 = { 364 .module_offs = CORE_MOD, 365 .idlest_reg_id = 2, 366 .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT, 367 }, 368 }, 369 .dev_attr = &mmc1_dev_attr, 370 .class = &omap2430_mmc_class, 371 }; 372 373 /* MMC/SD/SDIO2 */ 374 static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = { 375 { .role = "dbck", .clk = "mmchsdb2_fck" }, 376 }; 377 378 static struct omap_hwmod omap2430_mmc2_hwmod = { 379 .name = "mmc2", 380 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 381 .opt_clks = omap2430_mmc2_opt_clks, 382 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks), 383 .main_clk = "mmchs2_fck", 384 .prcm = { 385 .omap2 = { 386 .module_offs = CORE_MOD, 387 .idlest_reg_id = 2, 388 .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT, 389 }, 390 }, 391 .class = &omap2430_mmc_class, 392 }; 393 394 /* HDQ1W/1-wire */ 395 static struct omap_hwmod omap2430_hdq1w_hwmod = { 396 .name = "hdq1w", 397 .main_clk = "hdq_fck", 398 .prcm = { 399 .omap2 = { 400 .module_offs = CORE_MOD, 401 .idlest_reg_id = 1, 402 .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT, 403 }, 404 }, 405 .class = &omap2_hdq1w_class, 406 }; 407 408 /* 409 * interfaces 410 */ 411 412 /* L3 -> L4_CORE interface */ 413 /* l3_core -> usbhsotg interface */ 414 static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = { 415 .master = &omap2430_usbhsotg_hwmod, 416 .slave = &omap2xxx_l3_main_hwmod, 417 .clk = "core_l3_ck", 418 .user = OCP_USER_MPU, 419 }; 420 421 /* L4 CORE -> I2C1 interface */ 422 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { 423 .master = &omap2xxx_l4_core_hwmod, 424 .slave = &omap2430_i2c1_hwmod, 425 .clk = "i2c1_ick", 426 .user = OCP_USER_MPU | OCP_USER_SDMA, 427 }; 428 429 /* L4 CORE -> I2C2 interface */ 430 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { 431 .master = &omap2xxx_l4_core_hwmod, 432 .slave = &omap2430_i2c2_hwmod, 433 .clk = "i2c2_ick", 434 .user = OCP_USER_MPU | OCP_USER_SDMA, 435 }; 436 437 /* l4_core ->usbhsotg interface */ 438 static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = { 439 .master = &omap2xxx_l4_core_hwmod, 440 .slave = &omap2430_usbhsotg_hwmod, 441 .clk = "usb_l4_ick", 442 .user = OCP_USER_MPU, 443 }; 444 445 /* L4 CORE -> MMC1 interface */ 446 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = { 447 .master = &omap2xxx_l4_core_hwmod, 448 .slave = &omap2430_mmc1_hwmod, 449 .clk = "mmchs1_ick", 450 .user = OCP_USER_MPU | OCP_USER_SDMA, 451 }; 452 453 /* L4 CORE -> MMC2 interface */ 454 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = { 455 .master = &omap2xxx_l4_core_hwmod, 456 .slave = &omap2430_mmc2_hwmod, 457 .clk = "mmchs2_ick", 458 .user = OCP_USER_MPU | OCP_USER_SDMA, 459 }; 460 461 /* l4 core -> mcspi3 interface */ 462 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = { 463 .master = &omap2xxx_l4_core_hwmod, 464 .slave = &omap2430_mcspi3_hwmod, 465 .clk = "mcspi3_ick", 466 .user = OCP_USER_MPU | OCP_USER_SDMA, 467 }; 468 469 /* IVA2 <- L3 interface */ 470 static struct omap_hwmod_ocp_if omap2430_l3__iva = { 471 .master = &omap2xxx_l3_main_hwmod, 472 .slave = &omap2430_iva_hwmod, 473 .clk = "core_l3_ck", 474 .user = OCP_USER_MPU | OCP_USER_SDMA, 475 }; 476 477 /* l4_wkup -> timer1 */ 478 static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = { 479 .master = &omap2xxx_l4_wkup_hwmod, 480 .slave = &omap2xxx_timer1_hwmod, 481 .clk = "gpt1_ick", 482 .user = OCP_USER_MPU | OCP_USER_SDMA, 483 }; 484 485 /* l4_wkup -> wd_timer2 */ 486 static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { 487 .master = &omap2xxx_l4_wkup_hwmod, 488 .slave = &omap2xxx_wd_timer2_hwmod, 489 .clk = "mpu_wdt_ick", 490 .user = OCP_USER_MPU | OCP_USER_SDMA, 491 }; 492 493 /* l4_wkup -> gpio1 */ 494 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { 495 .master = &omap2xxx_l4_wkup_hwmod, 496 .slave = &omap2xxx_gpio1_hwmod, 497 .clk = "gpios_ick", 498 .user = OCP_USER_MPU | OCP_USER_SDMA, 499 }; 500 501 /* l4_wkup -> gpio2 */ 502 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { 503 .master = &omap2xxx_l4_wkup_hwmod, 504 .slave = &omap2xxx_gpio2_hwmod, 505 .clk = "gpios_ick", 506 .user = OCP_USER_MPU | OCP_USER_SDMA, 507 }; 508 509 /* l4_wkup -> gpio3 */ 510 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { 511 .master = &omap2xxx_l4_wkup_hwmod, 512 .slave = &omap2xxx_gpio3_hwmod, 513 .clk = "gpios_ick", 514 .user = OCP_USER_MPU | OCP_USER_SDMA, 515 }; 516 517 /* l4_wkup -> gpio4 */ 518 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { 519 .master = &omap2xxx_l4_wkup_hwmod, 520 .slave = &omap2xxx_gpio4_hwmod, 521 .clk = "gpios_ick", 522 .user = OCP_USER_MPU | OCP_USER_SDMA, 523 }; 524 525 /* l4_core -> gpio5 */ 526 static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { 527 .master = &omap2xxx_l4_core_hwmod, 528 .slave = &omap2430_gpio5_hwmod, 529 .clk = "gpio5_ick", 530 .user = OCP_USER_MPU | OCP_USER_SDMA, 531 }; 532 533 /* dma_system -> L3 */ 534 static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { 535 .master = &omap2430_dma_system_hwmod, 536 .slave = &omap2xxx_l3_main_hwmod, 537 .clk = "core_l3_ck", 538 .user = OCP_USER_MPU | OCP_USER_SDMA, 539 }; 540 541 /* l4_core -> dma_system */ 542 static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { 543 .master = &omap2xxx_l4_core_hwmod, 544 .slave = &omap2430_dma_system_hwmod, 545 .clk = "sdma_ick", 546 .user = OCP_USER_MPU | OCP_USER_SDMA, 547 }; 548 549 /* l4_core -> mailbox */ 550 static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = { 551 .master = &omap2xxx_l4_core_hwmod, 552 .slave = &omap2430_mailbox_hwmod, 553 .user = OCP_USER_MPU | OCP_USER_SDMA, 554 }; 555 556 /* l4_core -> mcbsp1 */ 557 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = { 558 .master = &omap2xxx_l4_core_hwmod, 559 .slave = &omap2430_mcbsp1_hwmod, 560 .clk = "mcbsp1_ick", 561 .user = OCP_USER_MPU | OCP_USER_SDMA, 562 }; 563 564 /* l4_core -> mcbsp2 */ 565 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = { 566 .master = &omap2xxx_l4_core_hwmod, 567 .slave = &omap2430_mcbsp2_hwmod, 568 .clk = "mcbsp2_ick", 569 .user = OCP_USER_MPU | OCP_USER_SDMA, 570 }; 571 572 /* l4_core -> mcbsp3 */ 573 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = { 574 .master = &omap2xxx_l4_core_hwmod, 575 .slave = &omap2430_mcbsp3_hwmod, 576 .clk = "mcbsp3_ick", 577 .user = OCP_USER_MPU | OCP_USER_SDMA, 578 }; 579 580 /* l4_core -> mcbsp4 */ 581 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = { 582 .master = &omap2xxx_l4_core_hwmod, 583 .slave = &omap2430_mcbsp4_hwmod, 584 .clk = "mcbsp4_ick", 585 .user = OCP_USER_MPU | OCP_USER_SDMA, 586 }; 587 588 /* l4_core -> mcbsp5 */ 589 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = { 590 .master = &omap2xxx_l4_core_hwmod, 591 .slave = &omap2430_mcbsp5_hwmod, 592 .clk = "mcbsp5_ick", 593 .user = OCP_USER_MPU | OCP_USER_SDMA, 594 }; 595 596 /* l4_core -> hdq1w */ 597 static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = { 598 .master = &omap2xxx_l4_core_hwmod, 599 .slave = &omap2430_hdq1w_hwmod, 600 .clk = "hdq_ick", 601 .user = OCP_USER_MPU | OCP_USER_SDMA, 602 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, 603 }; 604 605 /* l4_wkup -> 32ksync_counter */ 606 static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = { 607 .master = &omap2xxx_l4_wkup_hwmod, 608 .slave = &omap2xxx_counter_32k_hwmod, 609 .clk = "sync_32k_ick", 610 .user = OCP_USER_MPU | OCP_USER_SDMA, 611 }; 612 613 static struct omap_hwmod_ocp_if omap2430_l3__gpmc = { 614 .master = &omap2xxx_l3_main_hwmod, 615 .slave = &omap2xxx_gpmc_hwmod, 616 .clk = "core_l3_ck", 617 .user = OCP_USER_MPU | OCP_USER_SDMA, 618 }; 619 620 static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = { 621 &omap2xxx_l3_main__l4_core, 622 &omap2xxx_mpu__l3_main, 623 &omap2xxx_dss__l3, 624 &omap2430_usbhsotg__l3, 625 &omap2430_l4_core__i2c1, 626 &omap2430_l4_core__i2c2, 627 &omap2xxx_l4_core__l4_wkup, 628 &omap2_l4_core__uart1, 629 &omap2_l4_core__uart2, 630 &omap2_l4_core__uart3, 631 &omap2430_l4_core__usbhsotg, 632 &omap2430_l4_core__mmc1, 633 &omap2430_l4_core__mmc2, 634 &omap2xxx_l4_core__mcspi1, 635 &omap2xxx_l4_core__mcspi2, 636 &omap2430_l4_core__mcspi3, 637 &omap2430_l3__iva, 638 &omap2430_l4_wkup__timer1, 639 &omap2xxx_l4_core__timer2, 640 &omap2xxx_l4_core__timer3, 641 &omap2xxx_l4_core__timer4, 642 &omap2xxx_l4_core__timer5, 643 &omap2xxx_l4_core__timer6, 644 &omap2xxx_l4_core__timer7, 645 &omap2xxx_l4_core__timer8, 646 &omap2xxx_l4_core__timer9, 647 &omap2xxx_l4_core__timer10, 648 &omap2xxx_l4_core__timer11, 649 &omap2xxx_l4_core__timer12, 650 &omap2430_l4_wkup__wd_timer2, 651 &omap2xxx_l4_core__dss, 652 &omap2xxx_l4_core__dss_dispc, 653 &omap2xxx_l4_core__dss_rfbi, 654 &omap2xxx_l4_core__dss_venc, 655 &omap2430_l4_wkup__gpio1, 656 &omap2430_l4_wkup__gpio2, 657 &omap2430_l4_wkup__gpio3, 658 &omap2430_l4_wkup__gpio4, 659 &omap2430_l4_core__gpio5, 660 &omap2430_dma_system__l3, 661 &omap2430_l4_core__dma_system, 662 &omap2430_l4_core__mailbox, 663 &omap2430_l4_core__mcbsp1, 664 &omap2430_l4_core__mcbsp2, 665 &omap2430_l4_core__mcbsp3, 666 &omap2430_l4_core__mcbsp4, 667 &omap2430_l4_core__mcbsp5, 668 &omap2430_l4_core__hdq1w, 669 &omap2xxx_l4_core__rng, 670 &omap2xxx_l4_core__sham, 671 &omap2xxx_l4_core__aes, 672 &omap2430_l4_wkup__counter_32k, 673 &omap2430_l3__gpmc, 674 NULL, 675 }; 676 677 int __init omap2430_hwmod_init(void) 678 { 679 omap_hwmod_init(); 680 return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs); 681 } 682