1 /*
2  * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
3  *
4  * Copyright (C) 2009-2011 Nokia Corporation
5  * Copyright (C) 2012 Texas Instruments, Inc.
6  * Paul Walmsley
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  *
12  * XXX handle crossbar/shared link difference for L3?
13  * XXX these should be marked initdata for multi-OMAP kernels
14  */
15 
16 #include <linux/platform_data/i2c-omap.h>
17 #include <linux/platform_data/hsmmc-omap.h>
18 #include <linux/omap-dma.h>
19 
20 #include "omap_hwmod.h"
21 #include "l3_2xxx.h"
22 
23 #include "soc.h"
24 #include "omap_hwmod_common_data.h"
25 #include "prm-regbits-24xx.h"
26 #include "cm-regbits-24xx.h"
27 #include "i2c.h"
28 #include "wd_timer.h"
29 
30 /*
31  * OMAP2430 hardware module integration data
32  *
33  * All of the data in this section should be autogeneratable from the
34  * TI hardware database or other technical documentation.  Data that
35  * is driver-specific or driver-kernel integration-specific belongs
36  * elsewhere.
37  */
38 
39 /*
40  * IP blocks
41  */
42 
43 /* IVA2 (IVA2) */
44 static struct omap_hwmod_rst_info omap2430_iva_resets[] = {
45 	{ .name = "logic", .rst_shift = 0 },
46 	{ .name = "mmu", .rst_shift = 1 },
47 };
48 
49 static struct omap_hwmod omap2430_iva_hwmod = {
50 	.name		= "iva",
51 	.class		= &iva_hwmod_class,
52 	.clkdm_name	= "dsp_clkdm",
53 	.rst_lines	= omap2430_iva_resets,
54 	.rst_lines_cnt	= ARRAY_SIZE(omap2430_iva_resets),
55 	.main_clk	= "dsp_fck",
56 };
57 
58 /* I2C common */
59 static struct omap_hwmod_class_sysconfig i2c_sysc = {
60 	.rev_offs	= 0x00,
61 	.sysc_offs	= 0x20,
62 	.syss_offs	= 0x10,
63 	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
64 			   SYSS_HAS_RESET_STATUS),
65 	.sysc_fields	= &omap_hwmod_sysc_type1,
66 };
67 
68 static struct omap_hwmod_class i2c_class = {
69 	.name		= "i2c",
70 	.sysc		= &i2c_sysc,
71 	.reset		= &omap_i2c_reset,
72 };
73 
74 /* I2C1 */
75 static struct omap_hwmod omap2430_i2c1_hwmod = {
76 	.name		= "i2c1",
77 	.flags		= HWMOD_16BIT_REG,
78 	.main_clk	= "i2chs1_fck",
79 	.prcm		= {
80 		.omap2 = {
81 			/*
82 			 * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
83 			 * I2CHS IP's do not follow the usual pattern.
84 			 * prcm_reg_id alone cannot be used to program
85 			 * the iclk and fclk. Needs to be handled using
86 			 * additional flags when clk handling is moved
87 			 * to hwmod framework.
88 			 */
89 			.module_offs = CORE_MOD,
90 			.idlest_reg_id = 1,
91 			.idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
92 		},
93 	},
94 	.class		= &i2c_class,
95 };
96 
97 /* I2C2 */
98 static struct omap_hwmod omap2430_i2c2_hwmod = {
99 	.name		= "i2c2",
100 	.flags		= HWMOD_16BIT_REG,
101 	.main_clk	= "i2chs2_fck",
102 	.prcm		= {
103 		.omap2 = {
104 			.module_offs = CORE_MOD,
105 			.idlest_reg_id = 1,
106 			.idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
107 		},
108 	},
109 	.class		= &i2c_class,
110 };
111 
112 /* gpio5 */
113 static struct omap_hwmod omap2430_gpio5_hwmod = {
114 	.name		= "gpio5",
115 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
116 	.main_clk	= "gpio5_fck",
117 	.prcm		= {
118 		.omap2 = {
119 			.module_offs = CORE_MOD,
120 			.idlest_reg_id = 2,
121 			.idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
122 		},
123 	},
124 	.class		= &omap2xxx_gpio_hwmod_class,
125 };
126 
127 /* dma attributes */
128 static struct omap_dma_dev_attr dma_dev_attr = {
129 	.dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
130 				IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
131 	.lch_count = 32,
132 };
133 
134 static struct omap_hwmod omap2430_dma_system_hwmod = {
135 	.name		= "dma",
136 	.class		= &omap2xxx_dma_hwmod_class,
137 	.main_clk	= "core_l3_ck",
138 	.dev_attr	= &dma_dev_attr,
139 	.flags		= HWMOD_NO_IDLEST,
140 };
141 
142 /* mailbox */
143 static struct omap_hwmod omap2430_mailbox_hwmod = {
144 	.name		= "mailbox",
145 	.class		= &omap2xxx_mailbox_hwmod_class,
146 	.main_clk	= "mailboxes_ick",
147 	.prcm		= {
148 		.omap2 = {
149 			.module_offs = CORE_MOD,
150 			.idlest_reg_id = 1,
151 			.idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
152 		},
153 	},
154 };
155 
156 /* mcspi3 */
157 static struct omap_hwmod omap2430_mcspi3_hwmod = {
158 	.name		= "mcspi3",
159 	.main_clk	= "mcspi3_fck",
160 	.prcm		= {
161 		.omap2 = {
162 			.module_offs = CORE_MOD,
163 			.idlest_reg_id = 2,
164 			.idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
165 		},
166 	},
167 	.class		= &omap2xxx_mcspi_class,
168 };
169 
170 /* usbhsotg */
171 static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
172 	.rev_offs	= 0x0400,
173 	.sysc_offs	= 0x0404,
174 	.syss_offs	= 0x0408,
175 	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
176 			  SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
177 			  SYSC_HAS_AUTOIDLE),
178 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
179 			  MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
180 	.sysc_fields	= &omap_hwmod_sysc_type1,
181 };
182 
183 static struct omap_hwmod_class usbotg_class = {
184 	.name = "usbotg",
185 	.sysc = &omap2430_usbhsotg_sysc,
186 };
187 
188 /* usb_otg_hs */
189 static struct omap_hwmod omap2430_usbhsotg_hwmod = {
190 	.name		= "usb_otg_hs",
191 	.main_clk	= "usbhs_ick",
192 	.prcm		= {
193 		.omap2 = {
194 			.module_offs = CORE_MOD,
195 			.idlest_reg_id = 1,
196 			.idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
197 		},
198 	},
199 	.class		= &usbotg_class,
200 	/*
201 	 * Erratum ID: i479  idle_req / idle_ack mechanism potentially
202 	 * broken when autoidle is enabled
203 	 * workaround is to disable the autoidle bit at module level.
204 	 */
205 	.flags		= HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
206 				| HWMOD_SWSUP_MSTANDBY,
207 };
208 
209 /*
210  * 'mcbsp' class
211  * multi channel buffered serial port controller
212  */
213 
214 static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
215 	.rev_offs	= 0x007C,
216 	.sysc_offs	= 0x008C,
217 	.sysc_flags	= (SYSC_HAS_SOFTRESET),
218 	.sysc_fields    = &omap_hwmod_sysc_type1,
219 };
220 
221 static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
222 	.name = "mcbsp",
223 	.sysc = &omap2430_mcbsp_sysc,
224 };
225 
226 static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
227 	{ .role = "pad_fck", .clk = "mcbsp_clks" },
228 	{ .role = "prcm_fck", .clk = "func_96m_ck" },
229 };
230 
231 /* mcbsp1 */
232 static struct omap_hwmod omap2430_mcbsp1_hwmod = {
233 	.name		= "mcbsp1",
234 	.class		= &omap2430_mcbsp_hwmod_class,
235 	.main_clk	= "mcbsp1_fck",
236 	.prcm		= {
237 		.omap2 = {
238 			.module_offs = CORE_MOD,
239 			.idlest_reg_id = 1,
240 			.idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
241 		},
242 	},
243 	.opt_clks	= mcbsp_opt_clks,
244 	.opt_clks_cnt	= ARRAY_SIZE(mcbsp_opt_clks),
245 };
246 
247 /* mcbsp2 */
248 static struct omap_hwmod omap2430_mcbsp2_hwmod = {
249 	.name		= "mcbsp2",
250 	.class		= &omap2430_mcbsp_hwmod_class,
251 	.main_clk	= "mcbsp2_fck",
252 	.prcm		= {
253 		.omap2 = {
254 			.module_offs = CORE_MOD,
255 			.idlest_reg_id = 1,
256 			.idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
257 		},
258 	},
259 	.opt_clks	= mcbsp_opt_clks,
260 	.opt_clks_cnt	= ARRAY_SIZE(mcbsp_opt_clks),
261 };
262 
263 /* mcbsp3 */
264 static struct omap_hwmod omap2430_mcbsp3_hwmod = {
265 	.name		= "mcbsp3",
266 	.class		= &omap2430_mcbsp_hwmod_class,
267 	.main_clk	= "mcbsp3_fck",
268 	.prcm		= {
269 		.omap2 = {
270 			.module_offs = CORE_MOD,
271 			.idlest_reg_id = 2,
272 			.idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
273 		},
274 	},
275 	.opt_clks	= mcbsp_opt_clks,
276 	.opt_clks_cnt	= ARRAY_SIZE(mcbsp_opt_clks),
277 };
278 
279 /* mcbsp4 */
280 static struct omap_hwmod omap2430_mcbsp4_hwmod = {
281 	.name		= "mcbsp4",
282 	.class		= &omap2430_mcbsp_hwmod_class,
283 	.main_clk	= "mcbsp4_fck",
284 	.prcm		= {
285 		.omap2 = {
286 			.module_offs = CORE_MOD,
287 			.idlest_reg_id = 2,
288 			.idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
289 		},
290 	},
291 	.opt_clks	= mcbsp_opt_clks,
292 	.opt_clks_cnt	= ARRAY_SIZE(mcbsp_opt_clks),
293 };
294 
295 /* mcbsp5 */
296 static struct omap_hwmod omap2430_mcbsp5_hwmod = {
297 	.name		= "mcbsp5",
298 	.class		= &omap2430_mcbsp_hwmod_class,
299 	.main_clk	= "mcbsp5_fck",
300 	.prcm		= {
301 		.omap2 = {
302 			.module_offs = CORE_MOD,
303 			.idlest_reg_id = 2,
304 			.idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
305 		},
306 	},
307 	.opt_clks	= mcbsp_opt_clks,
308 	.opt_clks_cnt	= ARRAY_SIZE(mcbsp_opt_clks),
309 };
310 
311 /* MMC/SD/SDIO common */
312 static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
313 	.rev_offs	= 0x1fc,
314 	.sysc_offs	= 0x10,
315 	.syss_offs	= 0x14,
316 	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
317 			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
318 			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
319 	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
320 	.sysc_fields    = &omap_hwmod_sysc_type1,
321 };
322 
323 static struct omap_hwmod_class omap2430_mmc_class = {
324 	.name = "mmc",
325 	.sysc = &omap2430_mmc_sysc,
326 };
327 
328 /* MMC/SD/SDIO1 */
329 static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
330 	{ .role = "dbck", .clk = "mmchsdb1_fck" },
331 };
332 
333 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
334 	.flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
335 };
336 
337 static struct omap_hwmod omap2430_mmc1_hwmod = {
338 	.name		= "mmc1",
339 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
340 	.opt_clks	= omap2430_mmc1_opt_clks,
341 	.opt_clks_cnt	= ARRAY_SIZE(omap2430_mmc1_opt_clks),
342 	.main_clk	= "mmchs1_fck",
343 	.prcm		= {
344 		.omap2 = {
345 			.module_offs = CORE_MOD,
346 			.idlest_reg_id = 2,
347 			.idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
348 		},
349 	},
350 	.dev_attr	= &mmc1_dev_attr,
351 	.class		= &omap2430_mmc_class,
352 };
353 
354 /* MMC/SD/SDIO2 */
355 static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
356 	{ .role = "dbck", .clk = "mmchsdb2_fck" },
357 };
358 
359 static struct omap_hwmod omap2430_mmc2_hwmod = {
360 	.name		= "mmc2",
361 	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
362 	.opt_clks	= omap2430_mmc2_opt_clks,
363 	.opt_clks_cnt	= ARRAY_SIZE(omap2430_mmc2_opt_clks),
364 	.main_clk	= "mmchs2_fck",
365 	.prcm		= {
366 		.omap2 = {
367 			.module_offs = CORE_MOD,
368 			.idlest_reg_id = 2,
369 			.idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
370 		},
371 	},
372 	.class		= &omap2430_mmc_class,
373 };
374 
375 /* HDQ1W/1-wire */
376 static struct omap_hwmod omap2430_hdq1w_hwmod = {
377 	.name		= "hdq1w",
378 	.main_clk	= "hdq_fck",
379 	.prcm		= {
380 		.omap2 = {
381 			.module_offs = CORE_MOD,
382 			.idlest_reg_id = 1,
383 			.idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
384 		},
385 	},
386 	.class		= &omap2_hdq1w_class,
387 };
388 
389 /*
390  * interfaces
391  */
392 
393 /* L3 -> L4_CORE interface */
394 /* l3_core -> usbhsotg  interface */
395 static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
396 	.master		= &omap2430_usbhsotg_hwmod,
397 	.slave		= &omap2xxx_l3_main_hwmod,
398 	.clk		= "core_l3_ck",
399 	.user		= OCP_USER_MPU,
400 };
401 
402 /* L4 CORE -> I2C1 interface */
403 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
404 	.master		= &omap2xxx_l4_core_hwmod,
405 	.slave		= &omap2430_i2c1_hwmod,
406 	.clk		= "i2c1_ick",
407 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
408 };
409 
410 /* L4 CORE -> I2C2 interface */
411 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
412 	.master		= &omap2xxx_l4_core_hwmod,
413 	.slave		= &omap2430_i2c2_hwmod,
414 	.clk		= "i2c2_ick",
415 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
416 };
417 
418 /*  l4_core ->usbhsotg  interface */
419 static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
420 	.master		= &omap2xxx_l4_core_hwmod,
421 	.slave		= &omap2430_usbhsotg_hwmod,
422 	.clk		= "usb_l4_ick",
423 	.user		= OCP_USER_MPU,
424 };
425 
426 /* L4 CORE -> MMC1 interface */
427 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
428 	.master		= &omap2xxx_l4_core_hwmod,
429 	.slave		= &omap2430_mmc1_hwmod,
430 	.clk		= "mmchs1_ick",
431 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
432 };
433 
434 /* L4 CORE -> MMC2 interface */
435 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
436 	.master		= &omap2xxx_l4_core_hwmod,
437 	.slave		= &omap2430_mmc2_hwmod,
438 	.clk		= "mmchs2_ick",
439 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
440 };
441 
442 /* l4 core -> mcspi3 interface */
443 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
444 	.master		= &omap2xxx_l4_core_hwmod,
445 	.slave		= &omap2430_mcspi3_hwmod,
446 	.clk		= "mcspi3_ick",
447 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
448 };
449 
450 /* IVA2 <- L3 interface */
451 static struct omap_hwmod_ocp_if omap2430_l3__iva = {
452 	.master		= &omap2xxx_l3_main_hwmod,
453 	.slave		= &omap2430_iva_hwmod,
454 	.clk		= "core_l3_ck",
455 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
456 };
457 
458 /* l4_wkup -> timer1 */
459 static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
460 	.master		= &omap2xxx_l4_wkup_hwmod,
461 	.slave		= &omap2xxx_timer1_hwmod,
462 	.clk		= "gpt1_ick",
463 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
464 };
465 
466 /* l4_wkup -> wd_timer2 */
467 static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
468 	.master		= &omap2xxx_l4_wkup_hwmod,
469 	.slave		= &omap2xxx_wd_timer2_hwmod,
470 	.clk		= "mpu_wdt_ick",
471 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
472 };
473 
474 /* l4_wkup -> gpio1 */
475 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
476 	.master		= &omap2xxx_l4_wkup_hwmod,
477 	.slave		= &omap2xxx_gpio1_hwmod,
478 	.clk		= "gpios_ick",
479 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
480 };
481 
482 /* l4_wkup -> gpio2 */
483 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
484 	.master		= &omap2xxx_l4_wkup_hwmod,
485 	.slave		= &omap2xxx_gpio2_hwmod,
486 	.clk		= "gpios_ick",
487 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
488 };
489 
490 /* l4_wkup -> gpio3 */
491 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
492 	.master		= &omap2xxx_l4_wkup_hwmod,
493 	.slave		= &omap2xxx_gpio3_hwmod,
494 	.clk		= "gpios_ick",
495 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
496 };
497 
498 /* l4_wkup -> gpio4 */
499 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
500 	.master		= &omap2xxx_l4_wkup_hwmod,
501 	.slave		= &omap2xxx_gpio4_hwmod,
502 	.clk		= "gpios_ick",
503 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
504 };
505 
506 /* l4_core -> gpio5 */
507 static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
508 	.master		= &omap2xxx_l4_core_hwmod,
509 	.slave		= &omap2430_gpio5_hwmod,
510 	.clk		= "gpio5_ick",
511 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
512 };
513 
514 /* dma_system -> L3 */
515 static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
516 	.master		= &omap2430_dma_system_hwmod,
517 	.slave		= &omap2xxx_l3_main_hwmod,
518 	.clk		= "core_l3_ck",
519 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
520 };
521 
522 /* l4_core -> dma_system */
523 static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
524 	.master		= &omap2xxx_l4_core_hwmod,
525 	.slave		= &omap2430_dma_system_hwmod,
526 	.clk		= "sdma_ick",
527 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
528 };
529 
530 /* l4_core -> mailbox */
531 static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
532 	.master		= &omap2xxx_l4_core_hwmod,
533 	.slave		= &omap2430_mailbox_hwmod,
534 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
535 };
536 
537 /* l4_core -> mcbsp1 */
538 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
539 	.master		= &omap2xxx_l4_core_hwmod,
540 	.slave		= &omap2430_mcbsp1_hwmod,
541 	.clk		= "mcbsp1_ick",
542 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
543 };
544 
545 /* l4_core -> mcbsp2 */
546 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
547 	.master		= &omap2xxx_l4_core_hwmod,
548 	.slave		= &omap2430_mcbsp2_hwmod,
549 	.clk		= "mcbsp2_ick",
550 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
551 };
552 
553 /* l4_core -> mcbsp3 */
554 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
555 	.master		= &omap2xxx_l4_core_hwmod,
556 	.slave		= &omap2430_mcbsp3_hwmod,
557 	.clk		= "mcbsp3_ick",
558 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
559 };
560 
561 /* l4_core -> mcbsp4 */
562 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
563 	.master		= &omap2xxx_l4_core_hwmod,
564 	.slave		= &omap2430_mcbsp4_hwmod,
565 	.clk		= "mcbsp4_ick",
566 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
567 };
568 
569 /* l4_core -> mcbsp5 */
570 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
571 	.master		= &omap2xxx_l4_core_hwmod,
572 	.slave		= &omap2430_mcbsp5_hwmod,
573 	.clk		= "mcbsp5_ick",
574 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
575 };
576 
577 /* l4_core -> hdq1w */
578 static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = {
579 	.master		= &omap2xxx_l4_core_hwmod,
580 	.slave		= &omap2430_hdq1w_hwmod,
581 	.clk		= "hdq_ick",
582 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
583 	.flags		= OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
584 };
585 
586 /* l4_wkup -> 32ksync_counter */
587 static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
588 	.master		= &omap2xxx_l4_wkup_hwmod,
589 	.slave		= &omap2xxx_counter_32k_hwmod,
590 	.clk		= "sync_32k_ick",
591 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
592 };
593 
594 static struct omap_hwmod_ocp_if omap2430_l3__gpmc = {
595 	.master		= &omap2xxx_l3_main_hwmod,
596 	.slave		= &omap2xxx_gpmc_hwmod,
597 	.clk		= "core_l3_ck",
598 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
599 };
600 
601 static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
602 	&omap2xxx_l3_main__l4_core,
603 	&omap2xxx_mpu__l3_main,
604 	&omap2xxx_dss__l3,
605 	&omap2430_usbhsotg__l3,
606 	&omap2430_l4_core__i2c1,
607 	&omap2430_l4_core__i2c2,
608 	&omap2xxx_l4_core__l4_wkup,
609 	&omap2_l4_core__uart1,
610 	&omap2_l4_core__uart2,
611 	&omap2_l4_core__uart3,
612 	&omap2430_l4_core__usbhsotg,
613 	&omap2430_l4_core__mmc1,
614 	&omap2430_l4_core__mmc2,
615 	&omap2xxx_l4_core__mcspi1,
616 	&omap2xxx_l4_core__mcspi2,
617 	&omap2430_l4_core__mcspi3,
618 	&omap2430_l3__iva,
619 	&omap2430_l4_wkup__timer1,
620 	&omap2xxx_l4_core__timer2,
621 	&omap2xxx_l4_core__timer3,
622 	&omap2xxx_l4_core__timer4,
623 	&omap2xxx_l4_core__timer5,
624 	&omap2xxx_l4_core__timer6,
625 	&omap2xxx_l4_core__timer7,
626 	&omap2xxx_l4_core__timer8,
627 	&omap2xxx_l4_core__timer9,
628 	&omap2xxx_l4_core__timer10,
629 	&omap2xxx_l4_core__timer11,
630 	&omap2xxx_l4_core__timer12,
631 	&omap2430_l4_wkup__wd_timer2,
632 	&omap2xxx_l4_core__dss,
633 	&omap2xxx_l4_core__dss_dispc,
634 	&omap2xxx_l4_core__dss_rfbi,
635 	&omap2xxx_l4_core__dss_venc,
636 	&omap2430_l4_wkup__gpio1,
637 	&omap2430_l4_wkup__gpio2,
638 	&omap2430_l4_wkup__gpio3,
639 	&omap2430_l4_wkup__gpio4,
640 	&omap2430_l4_core__gpio5,
641 	&omap2430_dma_system__l3,
642 	&omap2430_l4_core__dma_system,
643 	&omap2430_l4_core__mailbox,
644 	&omap2430_l4_core__mcbsp1,
645 	&omap2430_l4_core__mcbsp2,
646 	&omap2430_l4_core__mcbsp3,
647 	&omap2430_l4_core__mcbsp4,
648 	&omap2430_l4_core__mcbsp5,
649 	&omap2430_l4_core__hdq1w,
650 	&omap2xxx_l4_core__rng,
651 	&omap2xxx_l4_core__sham,
652 	&omap2xxx_l4_core__aes,
653 	&omap2430_l4_wkup__counter_32k,
654 	&omap2430_l3__gpmc,
655 	NULL,
656 };
657 
658 int __init omap2430_hwmod_init(void)
659 {
660 	omap_hwmod_init();
661 	return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs);
662 }
663