1 /* 2 * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips 3 * 4 * Copyright (C) 2009-2011 Nokia Corporation 5 * Copyright (C) 2012 Texas Instruments, Inc. 6 * Paul Walmsley 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * XXX handle crossbar/shared link difference for L3? 13 * XXX these should be marked initdata for multi-OMAP kernels 14 */ 15 16 #include <linux/i2c-omap.h> 17 #include <linux/platform_data/asoc-ti-mcbsp.h> 18 #include <linux/platform_data/spi-omap2-mcspi.h> 19 #include <linux/omap-dma.h> 20 #include <plat/dmtimer.h> 21 22 #include "omap_hwmod.h" 23 #include "mmc.h" 24 #include "l3_2xxx.h" 25 26 #include "soc.h" 27 #include "omap_hwmod_common_data.h" 28 #include "prm-regbits-24xx.h" 29 #include "cm-regbits-24xx.h" 30 #include "i2c.h" 31 #include "wd_timer.h" 32 33 /* 34 * OMAP2430 hardware module integration data 35 * 36 * All of the data in this section should be autogeneratable from the 37 * TI hardware database or other technical documentation. Data that 38 * is driver-specific or driver-kernel integration-specific belongs 39 * elsewhere. 40 */ 41 42 /* 43 * IP blocks 44 */ 45 46 /* IVA2 (IVA2) */ 47 static struct omap_hwmod_rst_info omap2430_iva_resets[] = { 48 { .name = "logic", .rst_shift = 0 }, 49 { .name = "mmu", .rst_shift = 1 }, 50 }; 51 52 static struct omap_hwmod omap2430_iva_hwmod = { 53 .name = "iva", 54 .class = &iva_hwmod_class, 55 .clkdm_name = "dsp_clkdm", 56 .rst_lines = omap2430_iva_resets, 57 .rst_lines_cnt = ARRAY_SIZE(omap2430_iva_resets), 58 .main_clk = "dsp_fck", 59 }; 60 61 /* I2C common */ 62 static struct omap_hwmod_class_sysconfig i2c_sysc = { 63 .rev_offs = 0x00, 64 .sysc_offs = 0x20, 65 .syss_offs = 0x10, 66 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | 67 SYSS_HAS_RESET_STATUS), 68 .sysc_fields = &omap_hwmod_sysc_type1, 69 }; 70 71 static struct omap_hwmod_class i2c_class = { 72 .name = "i2c", 73 .sysc = &i2c_sysc, 74 .rev = OMAP_I2C_IP_VERSION_1, 75 .reset = &omap_i2c_reset, 76 }; 77 78 static struct omap_i2c_dev_attr i2c_dev_attr = { 79 .fifo_depth = 8, /* bytes */ 80 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2 | 81 OMAP_I2C_FLAG_FORCE_19200_INT_CLK, 82 }; 83 84 /* I2C1 */ 85 static struct omap_hwmod omap2430_i2c1_hwmod = { 86 .name = "i2c1", 87 .flags = HWMOD_16BIT_REG, 88 .mpu_irqs = omap2_i2c1_mpu_irqs, 89 .sdma_reqs = omap2_i2c1_sdma_reqs, 90 .main_clk = "i2chs1_fck", 91 .prcm = { 92 .omap2 = { 93 /* 94 * NOTE: The CM_FCLKEN* and CM_ICLKEN* for 95 * I2CHS IP's do not follow the usual pattern. 96 * prcm_reg_id alone cannot be used to program 97 * the iclk and fclk. Needs to be handled using 98 * additional flags when clk handling is moved 99 * to hwmod framework. 100 */ 101 .module_offs = CORE_MOD, 102 .prcm_reg_id = 1, 103 .module_bit = OMAP2430_EN_I2CHS1_SHIFT, 104 .idlest_reg_id = 1, 105 .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT, 106 }, 107 }, 108 .class = &i2c_class, 109 .dev_attr = &i2c_dev_attr, 110 }; 111 112 /* I2C2 */ 113 static struct omap_hwmod omap2430_i2c2_hwmod = { 114 .name = "i2c2", 115 .flags = HWMOD_16BIT_REG, 116 .mpu_irqs = omap2_i2c2_mpu_irqs, 117 .sdma_reqs = omap2_i2c2_sdma_reqs, 118 .main_clk = "i2chs2_fck", 119 .prcm = { 120 .omap2 = { 121 .module_offs = CORE_MOD, 122 .prcm_reg_id = 1, 123 .module_bit = OMAP2430_EN_I2CHS2_SHIFT, 124 .idlest_reg_id = 1, 125 .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT, 126 }, 127 }, 128 .class = &i2c_class, 129 .dev_attr = &i2c_dev_attr, 130 }; 131 132 /* gpio5 */ 133 static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { 134 { .irq = 33 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK5 */ 135 { .irq = -1 }, 136 }; 137 138 static struct omap_hwmod omap2430_gpio5_hwmod = { 139 .name = "gpio5", 140 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 141 .mpu_irqs = omap243x_gpio5_irqs, 142 .main_clk = "gpio5_fck", 143 .prcm = { 144 .omap2 = { 145 .prcm_reg_id = 2, 146 .module_bit = OMAP2430_EN_GPIO5_SHIFT, 147 .module_offs = CORE_MOD, 148 .idlest_reg_id = 2, 149 .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT, 150 }, 151 }, 152 .class = &omap2xxx_gpio_hwmod_class, 153 .dev_attr = &omap2xxx_gpio_dev_attr, 154 }; 155 156 /* dma attributes */ 157 static struct omap_dma_dev_attr dma_dev_attr = { 158 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | 159 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, 160 .lch_count = 32, 161 }; 162 163 static struct omap_hwmod omap2430_dma_system_hwmod = { 164 .name = "dma", 165 .class = &omap2xxx_dma_hwmod_class, 166 .mpu_irqs = omap2_dma_system_irqs, 167 .main_clk = "core_l3_ck", 168 .dev_attr = &dma_dev_attr, 169 .flags = HWMOD_NO_IDLEST, 170 }; 171 172 /* mailbox */ 173 static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = { 174 { .irq = 26 + OMAP_INTC_START, }, 175 { .irq = -1 }, 176 }; 177 178 static struct omap_hwmod omap2430_mailbox_hwmod = { 179 .name = "mailbox", 180 .class = &omap2xxx_mailbox_hwmod_class, 181 .mpu_irqs = omap2430_mailbox_irqs, 182 .main_clk = "mailboxes_ick", 183 .prcm = { 184 .omap2 = { 185 .prcm_reg_id = 1, 186 .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, 187 .module_offs = CORE_MOD, 188 .idlest_reg_id = 1, 189 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, 190 }, 191 }, 192 }; 193 194 /* mcspi3 */ 195 static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = { 196 { .irq = 91 + OMAP_INTC_START, }, 197 { .irq = -1 }, 198 }; 199 200 static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = { 201 { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */ 202 { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */ 203 { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */ 204 { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */ 205 { .dma_req = -1 } 206 }; 207 208 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { 209 .num_chipselect = 2, 210 }; 211 212 static struct omap_hwmod omap2430_mcspi3_hwmod = { 213 .name = "mcspi3", 214 .mpu_irqs = omap2430_mcspi3_mpu_irqs, 215 .sdma_reqs = omap2430_mcspi3_sdma_reqs, 216 .main_clk = "mcspi3_fck", 217 .prcm = { 218 .omap2 = { 219 .module_offs = CORE_MOD, 220 .prcm_reg_id = 2, 221 .module_bit = OMAP2430_EN_MCSPI3_SHIFT, 222 .idlest_reg_id = 2, 223 .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT, 224 }, 225 }, 226 .class = &omap2xxx_mcspi_class, 227 .dev_attr = &omap_mcspi3_dev_attr, 228 }; 229 230 /* usbhsotg */ 231 static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = { 232 .rev_offs = 0x0400, 233 .sysc_offs = 0x0404, 234 .syss_offs = 0x0408, 235 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| 236 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 237 SYSC_HAS_AUTOIDLE), 238 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 239 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 240 .sysc_fields = &omap_hwmod_sysc_type1, 241 }; 242 243 static struct omap_hwmod_class usbotg_class = { 244 .name = "usbotg", 245 .sysc = &omap2430_usbhsotg_sysc, 246 }; 247 248 /* usb_otg_hs */ 249 static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = { 250 251 { .name = "mc", .irq = 92 + OMAP_INTC_START, }, 252 { .name = "dma", .irq = 93 + OMAP_INTC_START, }, 253 { .irq = -1 }, 254 }; 255 256 static struct omap_hwmod omap2430_usbhsotg_hwmod = { 257 .name = "usb_otg_hs", 258 .mpu_irqs = omap2430_usbhsotg_mpu_irqs, 259 .main_clk = "usbhs_ick", 260 .prcm = { 261 .omap2 = { 262 .prcm_reg_id = 1, 263 .module_bit = OMAP2430_EN_USBHS_MASK, 264 .module_offs = CORE_MOD, 265 .idlest_reg_id = 1, 266 .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT, 267 }, 268 }, 269 .class = &usbotg_class, 270 /* 271 * Erratum ID: i479 idle_req / idle_ack mechanism potentially 272 * broken when autoidle is enabled 273 * workaround is to disable the autoidle bit at module level. 274 */ 275 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE 276 | HWMOD_SWSUP_MSTANDBY, 277 }; 278 279 /* 280 * 'mcbsp' class 281 * multi channel buffered serial port controller 282 */ 283 284 static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = { 285 .rev_offs = 0x007C, 286 .sysc_offs = 0x008C, 287 .sysc_flags = (SYSC_HAS_SOFTRESET), 288 .sysc_fields = &omap_hwmod_sysc_type1, 289 }; 290 291 static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = { 292 .name = "mcbsp", 293 .sysc = &omap2430_mcbsp_sysc, 294 .rev = MCBSP_CONFIG_TYPE2, 295 }; 296 297 static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = { 298 { .role = "pad_fck", .clk = "mcbsp_clks" }, 299 { .role = "prcm_fck", .clk = "func_96m_ck" }, 300 }; 301 302 /* mcbsp1 */ 303 static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = { 304 { .name = "tx", .irq = 59 + OMAP_INTC_START, }, 305 { .name = "rx", .irq = 60 + OMAP_INTC_START, }, 306 { .name = "ovr", .irq = 61 + OMAP_INTC_START, }, 307 { .name = "common", .irq = 64 + OMAP_INTC_START, }, 308 { .irq = -1 }, 309 }; 310 311 static struct omap_hwmod omap2430_mcbsp1_hwmod = { 312 .name = "mcbsp1", 313 .class = &omap2430_mcbsp_hwmod_class, 314 .mpu_irqs = omap2430_mcbsp1_irqs, 315 .sdma_reqs = omap2_mcbsp1_sdma_reqs, 316 .main_clk = "mcbsp1_fck", 317 .prcm = { 318 .omap2 = { 319 .prcm_reg_id = 1, 320 .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, 321 .module_offs = CORE_MOD, 322 .idlest_reg_id = 1, 323 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, 324 }, 325 }, 326 .opt_clks = mcbsp_opt_clks, 327 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), 328 }; 329 330 /* mcbsp2 */ 331 static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = { 332 { .name = "tx", .irq = 62 + OMAP_INTC_START, }, 333 { .name = "rx", .irq = 63 + OMAP_INTC_START, }, 334 { .name = "common", .irq = 16 + OMAP_INTC_START, }, 335 { .irq = -1 }, 336 }; 337 338 static struct omap_hwmod omap2430_mcbsp2_hwmod = { 339 .name = "mcbsp2", 340 .class = &omap2430_mcbsp_hwmod_class, 341 .mpu_irqs = omap2430_mcbsp2_irqs, 342 .sdma_reqs = omap2_mcbsp2_sdma_reqs, 343 .main_clk = "mcbsp2_fck", 344 .prcm = { 345 .omap2 = { 346 .prcm_reg_id = 1, 347 .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, 348 .module_offs = CORE_MOD, 349 .idlest_reg_id = 1, 350 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, 351 }, 352 }, 353 .opt_clks = mcbsp_opt_clks, 354 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), 355 }; 356 357 /* mcbsp3 */ 358 static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = { 359 { .name = "tx", .irq = 89 + OMAP_INTC_START, }, 360 { .name = "rx", .irq = 90 + OMAP_INTC_START, }, 361 { .name = "common", .irq = 17 + OMAP_INTC_START, }, 362 { .irq = -1 }, 363 }; 364 365 static struct omap_hwmod omap2430_mcbsp3_hwmod = { 366 .name = "mcbsp3", 367 .class = &omap2430_mcbsp_hwmod_class, 368 .mpu_irqs = omap2430_mcbsp3_irqs, 369 .sdma_reqs = omap2_mcbsp3_sdma_reqs, 370 .main_clk = "mcbsp3_fck", 371 .prcm = { 372 .omap2 = { 373 .prcm_reg_id = 1, 374 .module_bit = OMAP2430_EN_MCBSP3_SHIFT, 375 .module_offs = CORE_MOD, 376 .idlest_reg_id = 2, 377 .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT, 378 }, 379 }, 380 .opt_clks = mcbsp_opt_clks, 381 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), 382 }; 383 384 /* mcbsp4 */ 385 static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = { 386 { .name = "tx", .irq = 54 + OMAP_INTC_START, }, 387 { .name = "rx", .irq = 55 + OMAP_INTC_START, }, 388 { .name = "common", .irq = 18 + OMAP_INTC_START, }, 389 { .irq = -1 }, 390 }; 391 392 static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = { 393 { .name = "rx", .dma_req = 20 }, 394 { .name = "tx", .dma_req = 19 }, 395 { .dma_req = -1 } 396 }; 397 398 static struct omap_hwmod omap2430_mcbsp4_hwmod = { 399 .name = "mcbsp4", 400 .class = &omap2430_mcbsp_hwmod_class, 401 .mpu_irqs = omap2430_mcbsp4_irqs, 402 .sdma_reqs = omap2430_mcbsp4_sdma_chs, 403 .main_clk = "mcbsp4_fck", 404 .prcm = { 405 .omap2 = { 406 .prcm_reg_id = 1, 407 .module_bit = OMAP2430_EN_MCBSP4_SHIFT, 408 .module_offs = CORE_MOD, 409 .idlest_reg_id = 2, 410 .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT, 411 }, 412 }, 413 .opt_clks = mcbsp_opt_clks, 414 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), 415 }; 416 417 /* mcbsp5 */ 418 static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = { 419 { .name = "tx", .irq = 81 + OMAP_INTC_START, }, 420 { .name = "rx", .irq = 82 + OMAP_INTC_START, }, 421 { .name = "common", .irq = 19 + OMAP_INTC_START, }, 422 { .irq = -1 }, 423 }; 424 425 static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = { 426 { .name = "rx", .dma_req = 22 }, 427 { .name = "tx", .dma_req = 21 }, 428 { .dma_req = -1 } 429 }; 430 431 static struct omap_hwmod omap2430_mcbsp5_hwmod = { 432 .name = "mcbsp5", 433 .class = &omap2430_mcbsp_hwmod_class, 434 .mpu_irqs = omap2430_mcbsp5_irqs, 435 .sdma_reqs = omap2430_mcbsp5_sdma_chs, 436 .main_clk = "mcbsp5_fck", 437 .prcm = { 438 .omap2 = { 439 .prcm_reg_id = 1, 440 .module_bit = OMAP2430_EN_MCBSP5_SHIFT, 441 .module_offs = CORE_MOD, 442 .idlest_reg_id = 2, 443 .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT, 444 }, 445 }, 446 .opt_clks = mcbsp_opt_clks, 447 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), 448 }; 449 450 /* MMC/SD/SDIO common */ 451 static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = { 452 .rev_offs = 0x1fc, 453 .sysc_offs = 0x10, 454 .syss_offs = 0x14, 455 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 456 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 457 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 458 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 459 .sysc_fields = &omap_hwmod_sysc_type1, 460 }; 461 462 static struct omap_hwmod_class omap2430_mmc_class = { 463 .name = "mmc", 464 .sysc = &omap2430_mmc_sysc, 465 }; 466 467 /* MMC/SD/SDIO1 */ 468 static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = { 469 { .irq = 83 + OMAP_INTC_START, }, 470 { .irq = -1 }, 471 }; 472 473 static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = { 474 { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */ 475 { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */ 476 { .dma_req = -1 } 477 }; 478 479 static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = { 480 { .role = "dbck", .clk = "mmchsdb1_fck" }, 481 }; 482 483 static struct omap_mmc_dev_attr mmc1_dev_attr = { 484 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, 485 }; 486 487 static struct omap_hwmod omap2430_mmc1_hwmod = { 488 .name = "mmc1", 489 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 490 .mpu_irqs = omap2430_mmc1_mpu_irqs, 491 .sdma_reqs = omap2430_mmc1_sdma_reqs, 492 .opt_clks = omap2430_mmc1_opt_clks, 493 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks), 494 .main_clk = "mmchs1_fck", 495 .prcm = { 496 .omap2 = { 497 .module_offs = CORE_MOD, 498 .prcm_reg_id = 2, 499 .module_bit = OMAP2430_EN_MMCHS1_SHIFT, 500 .idlest_reg_id = 2, 501 .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT, 502 }, 503 }, 504 .dev_attr = &mmc1_dev_attr, 505 .class = &omap2430_mmc_class, 506 }; 507 508 /* MMC/SD/SDIO2 */ 509 static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = { 510 { .irq = 86 + OMAP_INTC_START, }, 511 { .irq = -1 }, 512 }; 513 514 static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = { 515 { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */ 516 { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */ 517 { .dma_req = -1 } 518 }; 519 520 static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = { 521 { .role = "dbck", .clk = "mmchsdb2_fck" }, 522 }; 523 524 static struct omap_hwmod omap2430_mmc2_hwmod = { 525 .name = "mmc2", 526 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 527 .mpu_irqs = omap2430_mmc2_mpu_irqs, 528 .sdma_reqs = omap2430_mmc2_sdma_reqs, 529 .opt_clks = omap2430_mmc2_opt_clks, 530 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks), 531 .main_clk = "mmchs2_fck", 532 .prcm = { 533 .omap2 = { 534 .module_offs = CORE_MOD, 535 .prcm_reg_id = 2, 536 .module_bit = OMAP2430_EN_MMCHS2_SHIFT, 537 .idlest_reg_id = 2, 538 .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT, 539 }, 540 }, 541 .class = &omap2430_mmc_class, 542 }; 543 544 /* HDQ1W/1-wire */ 545 static struct omap_hwmod omap2430_hdq1w_hwmod = { 546 .name = "hdq1w", 547 .mpu_irqs = omap2_hdq1w_mpu_irqs, 548 .main_clk = "hdq_fck", 549 .prcm = { 550 .omap2 = { 551 .module_offs = CORE_MOD, 552 .prcm_reg_id = 1, 553 .module_bit = OMAP24XX_EN_HDQ_SHIFT, 554 .idlest_reg_id = 1, 555 .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT, 556 }, 557 }, 558 .class = &omap2_hdq1w_class, 559 }; 560 561 /* 562 * interfaces 563 */ 564 565 /* L3 -> L4_CORE interface */ 566 /* l3_core -> usbhsotg interface */ 567 static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = { 568 .master = &omap2430_usbhsotg_hwmod, 569 .slave = &omap2xxx_l3_main_hwmod, 570 .clk = "core_l3_ck", 571 .user = OCP_USER_MPU, 572 }; 573 574 /* L4 CORE -> I2C1 interface */ 575 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { 576 .master = &omap2xxx_l4_core_hwmod, 577 .slave = &omap2430_i2c1_hwmod, 578 .clk = "i2c1_ick", 579 .addr = omap2_i2c1_addr_space, 580 .user = OCP_USER_MPU | OCP_USER_SDMA, 581 }; 582 583 /* L4 CORE -> I2C2 interface */ 584 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { 585 .master = &omap2xxx_l4_core_hwmod, 586 .slave = &omap2430_i2c2_hwmod, 587 .clk = "i2c2_ick", 588 .addr = omap2_i2c2_addr_space, 589 .user = OCP_USER_MPU | OCP_USER_SDMA, 590 }; 591 592 static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = { 593 { 594 .pa_start = OMAP243X_HS_BASE, 595 .pa_end = OMAP243X_HS_BASE + SZ_4K - 1, 596 .flags = ADDR_TYPE_RT 597 }, 598 { } 599 }; 600 601 /* l4_core ->usbhsotg interface */ 602 static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = { 603 .master = &omap2xxx_l4_core_hwmod, 604 .slave = &omap2430_usbhsotg_hwmod, 605 .clk = "usb_l4_ick", 606 .addr = omap2430_usbhsotg_addrs, 607 .user = OCP_USER_MPU, 608 }; 609 610 /* L4 CORE -> MMC1 interface */ 611 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = { 612 .master = &omap2xxx_l4_core_hwmod, 613 .slave = &omap2430_mmc1_hwmod, 614 .clk = "mmchs1_ick", 615 .addr = omap2430_mmc1_addr_space, 616 .user = OCP_USER_MPU | OCP_USER_SDMA, 617 }; 618 619 /* L4 CORE -> MMC2 interface */ 620 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = { 621 .master = &omap2xxx_l4_core_hwmod, 622 .slave = &omap2430_mmc2_hwmod, 623 .clk = "mmchs2_ick", 624 .addr = omap2430_mmc2_addr_space, 625 .user = OCP_USER_MPU | OCP_USER_SDMA, 626 }; 627 628 /* l4 core -> mcspi3 interface */ 629 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = { 630 .master = &omap2xxx_l4_core_hwmod, 631 .slave = &omap2430_mcspi3_hwmod, 632 .clk = "mcspi3_ick", 633 .addr = omap2430_mcspi3_addr_space, 634 .user = OCP_USER_MPU | OCP_USER_SDMA, 635 }; 636 637 /* IVA2 <- L3 interface */ 638 static struct omap_hwmod_ocp_if omap2430_l3__iva = { 639 .master = &omap2xxx_l3_main_hwmod, 640 .slave = &omap2430_iva_hwmod, 641 .clk = "core_l3_ck", 642 .user = OCP_USER_MPU | OCP_USER_SDMA, 643 }; 644 645 static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = { 646 { 647 .pa_start = 0x49018000, 648 .pa_end = 0x49018000 + SZ_1K - 1, 649 .flags = ADDR_TYPE_RT 650 }, 651 { } 652 }; 653 654 /* l4_wkup -> timer1 */ 655 static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = { 656 .master = &omap2xxx_l4_wkup_hwmod, 657 .slave = &omap2xxx_timer1_hwmod, 658 .clk = "gpt1_ick", 659 .addr = omap2430_timer1_addrs, 660 .user = OCP_USER_MPU | OCP_USER_SDMA, 661 }; 662 663 /* l4_wkup -> wd_timer2 */ 664 static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { 665 { 666 .pa_start = 0x49016000, 667 .pa_end = 0x4901607f, 668 .flags = ADDR_TYPE_RT 669 }, 670 { } 671 }; 672 673 static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { 674 .master = &omap2xxx_l4_wkup_hwmod, 675 .slave = &omap2xxx_wd_timer2_hwmod, 676 .clk = "mpu_wdt_ick", 677 .addr = omap2430_wd_timer2_addrs, 678 .user = OCP_USER_MPU | OCP_USER_SDMA, 679 }; 680 681 /* l4_wkup -> gpio1 */ 682 static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = { 683 { 684 .pa_start = 0x4900C000, 685 .pa_end = 0x4900C1ff, 686 .flags = ADDR_TYPE_RT 687 }, 688 { } 689 }; 690 691 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { 692 .master = &omap2xxx_l4_wkup_hwmod, 693 .slave = &omap2xxx_gpio1_hwmod, 694 .clk = "gpios_ick", 695 .addr = omap2430_gpio1_addr_space, 696 .user = OCP_USER_MPU | OCP_USER_SDMA, 697 }; 698 699 /* l4_wkup -> gpio2 */ 700 static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = { 701 { 702 .pa_start = 0x4900E000, 703 .pa_end = 0x4900E1ff, 704 .flags = ADDR_TYPE_RT 705 }, 706 { } 707 }; 708 709 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { 710 .master = &omap2xxx_l4_wkup_hwmod, 711 .slave = &omap2xxx_gpio2_hwmod, 712 .clk = "gpios_ick", 713 .addr = omap2430_gpio2_addr_space, 714 .user = OCP_USER_MPU | OCP_USER_SDMA, 715 }; 716 717 /* l4_wkup -> gpio3 */ 718 static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = { 719 { 720 .pa_start = 0x49010000, 721 .pa_end = 0x490101ff, 722 .flags = ADDR_TYPE_RT 723 }, 724 { } 725 }; 726 727 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { 728 .master = &omap2xxx_l4_wkup_hwmod, 729 .slave = &omap2xxx_gpio3_hwmod, 730 .clk = "gpios_ick", 731 .addr = omap2430_gpio3_addr_space, 732 .user = OCP_USER_MPU | OCP_USER_SDMA, 733 }; 734 735 /* l4_wkup -> gpio4 */ 736 static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = { 737 { 738 .pa_start = 0x49012000, 739 .pa_end = 0x490121ff, 740 .flags = ADDR_TYPE_RT 741 }, 742 { } 743 }; 744 745 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { 746 .master = &omap2xxx_l4_wkup_hwmod, 747 .slave = &omap2xxx_gpio4_hwmod, 748 .clk = "gpios_ick", 749 .addr = omap2430_gpio4_addr_space, 750 .user = OCP_USER_MPU | OCP_USER_SDMA, 751 }; 752 753 /* l4_core -> gpio5 */ 754 static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = { 755 { 756 .pa_start = 0x480B6000, 757 .pa_end = 0x480B61ff, 758 .flags = ADDR_TYPE_RT 759 }, 760 { } 761 }; 762 763 static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { 764 .master = &omap2xxx_l4_core_hwmod, 765 .slave = &omap2430_gpio5_hwmod, 766 .clk = "gpio5_ick", 767 .addr = omap2430_gpio5_addr_space, 768 .user = OCP_USER_MPU | OCP_USER_SDMA, 769 }; 770 771 /* dma_system -> L3 */ 772 static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { 773 .master = &omap2430_dma_system_hwmod, 774 .slave = &omap2xxx_l3_main_hwmod, 775 .clk = "core_l3_ck", 776 .user = OCP_USER_MPU | OCP_USER_SDMA, 777 }; 778 779 /* l4_core -> dma_system */ 780 static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { 781 .master = &omap2xxx_l4_core_hwmod, 782 .slave = &omap2430_dma_system_hwmod, 783 .clk = "sdma_ick", 784 .addr = omap2_dma_system_addrs, 785 .user = OCP_USER_MPU | OCP_USER_SDMA, 786 }; 787 788 /* l4_core -> mailbox */ 789 static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = { 790 .master = &omap2xxx_l4_core_hwmod, 791 .slave = &omap2430_mailbox_hwmod, 792 .addr = omap2_mailbox_addrs, 793 .user = OCP_USER_MPU | OCP_USER_SDMA, 794 }; 795 796 /* l4_core -> mcbsp1 */ 797 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = { 798 .master = &omap2xxx_l4_core_hwmod, 799 .slave = &omap2430_mcbsp1_hwmod, 800 .clk = "mcbsp1_ick", 801 .addr = omap2_mcbsp1_addrs, 802 .user = OCP_USER_MPU | OCP_USER_SDMA, 803 }; 804 805 /* l4_core -> mcbsp2 */ 806 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = { 807 .master = &omap2xxx_l4_core_hwmod, 808 .slave = &omap2430_mcbsp2_hwmod, 809 .clk = "mcbsp2_ick", 810 .addr = omap2xxx_mcbsp2_addrs, 811 .user = OCP_USER_MPU | OCP_USER_SDMA, 812 }; 813 814 static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = { 815 { 816 .name = "mpu", 817 .pa_start = 0x4808C000, 818 .pa_end = 0x4808C0ff, 819 .flags = ADDR_TYPE_RT 820 }, 821 { } 822 }; 823 824 /* l4_core -> mcbsp3 */ 825 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = { 826 .master = &omap2xxx_l4_core_hwmod, 827 .slave = &omap2430_mcbsp3_hwmod, 828 .clk = "mcbsp3_ick", 829 .addr = omap2430_mcbsp3_addrs, 830 .user = OCP_USER_MPU | OCP_USER_SDMA, 831 }; 832 833 static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = { 834 { 835 .name = "mpu", 836 .pa_start = 0x4808E000, 837 .pa_end = 0x4808E0ff, 838 .flags = ADDR_TYPE_RT 839 }, 840 { } 841 }; 842 843 /* l4_core -> mcbsp4 */ 844 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = { 845 .master = &omap2xxx_l4_core_hwmod, 846 .slave = &omap2430_mcbsp4_hwmod, 847 .clk = "mcbsp4_ick", 848 .addr = omap2430_mcbsp4_addrs, 849 .user = OCP_USER_MPU | OCP_USER_SDMA, 850 }; 851 852 static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = { 853 { 854 .name = "mpu", 855 .pa_start = 0x48096000, 856 .pa_end = 0x480960ff, 857 .flags = ADDR_TYPE_RT 858 }, 859 { } 860 }; 861 862 /* l4_core -> mcbsp5 */ 863 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = { 864 .master = &omap2xxx_l4_core_hwmod, 865 .slave = &omap2430_mcbsp5_hwmod, 866 .clk = "mcbsp5_ick", 867 .addr = omap2430_mcbsp5_addrs, 868 .user = OCP_USER_MPU | OCP_USER_SDMA, 869 }; 870 871 /* l4_core -> hdq1w */ 872 static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = { 873 .master = &omap2xxx_l4_core_hwmod, 874 .slave = &omap2430_hdq1w_hwmod, 875 .clk = "hdq_ick", 876 .addr = omap2_hdq1w_addr_space, 877 .user = OCP_USER_MPU | OCP_USER_SDMA, 878 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, 879 }; 880 881 /* l4_wkup -> 32ksync_counter */ 882 static struct omap_hwmod_addr_space omap2430_counter_32k_addrs[] = { 883 { 884 .pa_start = 0x49020000, 885 .pa_end = 0x4902001f, 886 .flags = ADDR_TYPE_RT 887 }, 888 { } 889 }; 890 891 static struct omap_hwmod_addr_space omap2430_gpmc_addrs[] = { 892 { 893 .pa_start = 0x6e000000, 894 .pa_end = 0x6e000fff, 895 .flags = ADDR_TYPE_RT 896 }, 897 { } 898 }; 899 900 static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = { 901 .master = &omap2xxx_l4_wkup_hwmod, 902 .slave = &omap2xxx_counter_32k_hwmod, 903 .clk = "sync_32k_ick", 904 .addr = omap2430_counter_32k_addrs, 905 .user = OCP_USER_MPU | OCP_USER_SDMA, 906 }; 907 908 static struct omap_hwmod_ocp_if omap2430_l3__gpmc = { 909 .master = &omap2xxx_l3_main_hwmod, 910 .slave = &omap2xxx_gpmc_hwmod, 911 .clk = "core_l3_ck", 912 .addr = omap2430_gpmc_addrs, 913 .user = OCP_USER_MPU | OCP_USER_SDMA, 914 }; 915 916 static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = { 917 &omap2xxx_l3_main__l4_core, 918 &omap2xxx_mpu__l3_main, 919 &omap2xxx_dss__l3, 920 &omap2430_usbhsotg__l3, 921 &omap2430_l4_core__i2c1, 922 &omap2430_l4_core__i2c2, 923 &omap2xxx_l4_core__l4_wkup, 924 &omap2_l4_core__uart1, 925 &omap2_l4_core__uart2, 926 &omap2_l4_core__uart3, 927 &omap2430_l4_core__usbhsotg, 928 &omap2430_l4_core__mmc1, 929 &omap2430_l4_core__mmc2, 930 &omap2xxx_l4_core__mcspi1, 931 &omap2xxx_l4_core__mcspi2, 932 &omap2430_l4_core__mcspi3, 933 &omap2430_l3__iva, 934 &omap2430_l4_wkup__timer1, 935 &omap2xxx_l4_core__timer2, 936 &omap2xxx_l4_core__timer3, 937 &omap2xxx_l4_core__timer4, 938 &omap2xxx_l4_core__timer5, 939 &omap2xxx_l4_core__timer6, 940 &omap2xxx_l4_core__timer7, 941 &omap2xxx_l4_core__timer8, 942 &omap2xxx_l4_core__timer9, 943 &omap2xxx_l4_core__timer10, 944 &omap2xxx_l4_core__timer11, 945 &omap2xxx_l4_core__timer12, 946 &omap2430_l4_wkup__wd_timer2, 947 &omap2xxx_l4_core__dss, 948 &omap2xxx_l4_core__dss_dispc, 949 &omap2xxx_l4_core__dss_rfbi, 950 &omap2xxx_l4_core__dss_venc, 951 &omap2430_l4_wkup__gpio1, 952 &omap2430_l4_wkup__gpio2, 953 &omap2430_l4_wkup__gpio3, 954 &omap2430_l4_wkup__gpio4, 955 &omap2430_l4_core__gpio5, 956 &omap2430_dma_system__l3, 957 &omap2430_l4_core__dma_system, 958 &omap2430_l4_core__mailbox, 959 &omap2430_l4_core__mcbsp1, 960 &omap2430_l4_core__mcbsp2, 961 &omap2430_l4_core__mcbsp3, 962 &omap2430_l4_core__mcbsp4, 963 &omap2430_l4_core__mcbsp5, 964 &omap2430_l4_core__hdq1w, 965 &omap2xxx_l4_core__rng, 966 &omap2430_l4_wkup__counter_32k, 967 &omap2430_l3__gpmc, 968 NULL, 969 }; 970 971 int __init omap2430_hwmod_init(void) 972 { 973 omap_hwmod_init(); 974 return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs); 975 } 976