1 /* 2 * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips 3 * 4 * Copyright (C) 2009-2011 Nokia Corporation 5 * Copyright (C) 2012 Texas Instruments, Inc. 6 * Paul Walmsley 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * XXX handle crossbar/shared link difference for L3? 13 * XXX these should be marked initdata for multi-OMAP kernels 14 */ 15 16 #include <linux/i2c-omap.h> 17 #include <linux/platform_data/asoc-ti-mcbsp.h> 18 #include <linux/platform_data/hsmmc-omap.h> 19 #include <linux/platform_data/spi-omap2-mcspi.h> 20 #include <linux/omap-dma.h> 21 #include <plat/dmtimer.h> 22 23 #include "omap_hwmod.h" 24 #include "l3_2xxx.h" 25 26 #include "soc.h" 27 #include "omap_hwmod_common_data.h" 28 #include "prm-regbits-24xx.h" 29 #include "cm-regbits-24xx.h" 30 #include "i2c.h" 31 #include "wd_timer.h" 32 33 /* 34 * OMAP2430 hardware module integration data 35 * 36 * All of the data in this section should be autogeneratable from the 37 * TI hardware database or other technical documentation. Data that 38 * is driver-specific or driver-kernel integration-specific belongs 39 * elsewhere. 40 */ 41 42 /* 43 * IP blocks 44 */ 45 46 /* IVA2 (IVA2) */ 47 static struct omap_hwmod_rst_info omap2430_iva_resets[] = { 48 { .name = "logic", .rst_shift = 0 }, 49 { .name = "mmu", .rst_shift = 1 }, 50 }; 51 52 static struct omap_hwmod omap2430_iva_hwmod = { 53 .name = "iva", 54 .class = &iva_hwmod_class, 55 .clkdm_name = "dsp_clkdm", 56 .rst_lines = omap2430_iva_resets, 57 .rst_lines_cnt = ARRAY_SIZE(omap2430_iva_resets), 58 .main_clk = "dsp_fck", 59 }; 60 61 /* I2C common */ 62 static struct omap_hwmod_class_sysconfig i2c_sysc = { 63 .rev_offs = 0x00, 64 .sysc_offs = 0x20, 65 .syss_offs = 0x10, 66 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | 67 SYSS_HAS_RESET_STATUS), 68 .sysc_fields = &omap_hwmod_sysc_type1, 69 }; 70 71 static struct omap_hwmod_class i2c_class = { 72 .name = "i2c", 73 .sysc = &i2c_sysc, 74 .rev = OMAP_I2C_IP_VERSION_1, 75 .reset = &omap_i2c_reset, 76 }; 77 78 static struct omap_i2c_dev_attr i2c_dev_attr = { 79 .fifo_depth = 8, /* bytes */ 80 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2 | 81 OMAP_I2C_FLAG_FORCE_19200_INT_CLK, 82 }; 83 84 /* I2C1 */ 85 static struct omap_hwmod omap2430_i2c1_hwmod = { 86 .name = "i2c1", 87 .flags = HWMOD_16BIT_REG, 88 .main_clk = "i2chs1_fck", 89 .prcm = { 90 .omap2 = { 91 /* 92 * NOTE: The CM_FCLKEN* and CM_ICLKEN* for 93 * I2CHS IP's do not follow the usual pattern. 94 * prcm_reg_id alone cannot be used to program 95 * the iclk and fclk. Needs to be handled using 96 * additional flags when clk handling is moved 97 * to hwmod framework. 98 */ 99 .module_offs = CORE_MOD, 100 .prcm_reg_id = 1, 101 .module_bit = OMAP2430_EN_I2CHS1_SHIFT, 102 .idlest_reg_id = 1, 103 .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT, 104 }, 105 }, 106 .class = &i2c_class, 107 .dev_attr = &i2c_dev_attr, 108 }; 109 110 /* I2C2 */ 111 static struct omap_hwmod omap2430_i2c2_hwmod = { 112 .name = "i2c2", 113 .flags = HWMOD_16BIT_REG, 114 .main_clk = "i2chs2_fck", 115 .prcm = { 116 .omap2 = { 117 .module_offs = CORE_MOD, 118 .prcm_reg_id = 1, 119 .module_bit = OMAP2430_EN_I2CHS2_SHIFT, 120 .idlest_reg_id = 1, 121 .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT, 122 }, 123 }, 124 .class = &i2c_class, 125 .dev_attr = &i2c_dev_attr, 126 }; 127 128 /* gpio5 */ 129 static struct omap_hwmod omap2430_gpio5_hwmod = { 130 .name = "gpio5", 131 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 132 .main_clk = "gpio5_fck", 133 .prcm = { 134 .omap2 = { 135 .prcm_reg_id = 2, 136 .module_bit = OMAP2430_EN_GPIO5_SHIFT, 137 .module_offs = CORE_MOD, 138 .idlest_reg_id = 2, 139 .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT, 140 }, 141 }, 142 .class = &omap2xxx_gpio_hwmod_class, 143 .dev_attr = &omap2xxx_gpio_dev_attr, 144 }; 145 146 /* dma attributes */ 147 static struct omap_dma_dev_attr dma_dev_attr = { 148 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | 149 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, 150 .lch_count = 32, 151 }; 152 153 static struct omap_hwmod omap2430_dma_system_hwmod = { 154 .name = "dma", 155 .class = &omap2xxx_dma_hwmod_class, 156 .main_clk = "core_l3_ck", 157 .dev_attr = &dma_dev_attr, 158 .flags = HWMOD_NO_IDLEST, 159 }; 160 161 /* mailbox */ 162 static struct omap_hwmod omap2430_mailbox_hwmod = { 163 .name = "mailbox", 164 .class = &omap2xxx_mailbox_hwmod_class, 165 .main_clk = "mailboxes_ick", 166 .prcm = { 167 .omap2 = { 168 .prcm_reg_id = 1, 169 .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, 170 .module_offs = CORE_MOD, 171 .idlest_reg_id = 1, 172 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, 173 }, 174 }, 175 }; 176 177 /* mcspi3 */ 178 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { 179 .num_chipselect = 2, 180 }; 181 182 static struct omap_hwmod omap2430_mcspi3_hwmod = { 183 .name = "mcspi3", 184 .main_clk = "mcspi3_fck", 185 .prcm = { 186 .omap2 = { 187 .module_offs = CORE_MOD, 188 .prcm_reg_id = 2, 189 .module_bit = OMAP2430_EN_MCSPI3_SHIFT, 190 .idlest_reg_id = 2, 191 .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT, 192 }, 193 }, 194 .class = &omap2xxx_mcspi_class, 195 .dev_attr = &omap_mcspi3_dev_attr, 196 }; 197 198 /* usbhsotg */ 199 static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = { 200 .rev_offs = 0x0400, 201 .sysc_offs = 0x0404, 202 .syss_offs = 0x0408, 203 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| 204 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 205 SYSC_HAS_AUTOIDLE), 206 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 207 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 208 .sysc_fields = &omap_hwmod_sysc_type1, 209 }; 210 211 static struct omap_hwmod_class usbotg_class = { 212 .name = "usbotg", 213 .sysc = &omap2430_usbhsotg_sysc, 214 }; 215 216 /* usb_otg_hs */ 217 static struct omap_hwmod omap2430_usbhsotg_hwmod = { 218 .name = "usb_otg_hs", 219 .main_clk = "usbhs_ick", 220 .prcm = { 221 .omap2 = { 222 .prcm_reg_id = 1, 223 .module_bit = OMAP2430_EN_USBHS_MASK, 224 .module_offs = CORE_MOD, 225 .idlest_reg_id = 1, 226 .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT, 227 }, 228 }, 229 .class = &usbotg_class, 230 /* 231 * Erratum ID: i479 idle_req / idle_ack mechanism potentially 232 * broken when autoidle is enabled 233 * workaround is to disable the autoidle bit at module level. 234 */ 235 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE 236 | HWMOD_SWSUP_MSTANDBY, 237 }; 238 239 /* 240 * 'mcbsp' class 241 * multi channel buffered serial port controller 242 */ 243 244 static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = { 245 .rev_offs = 0x007C, 246 .sysc_offs = 0x008C, 247 .sysc_flags = (SYSC_HAS_SOFTRESET), 248 .sysc_fields = &omap_hwmod_sysc_type1, 249 }; 250 251 static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = { 252 .name = "mcbsp", 253 .sysc = &omap2430_mcbsp_sysc, 254 .rev = MCBSP_CONFIG_TYPE2, 255 }; 256 257 static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = { 258 { .role = "pad_fck", .clk = "mcbsp_clks" }, 259 { .role = "prcm_fck", .clk = "func_96m_ck" }, 260 }; 261 262 /* mcbsp1 */ 263 static struct omap_hwmod omap2430_mcbsp1_hwmod = { 264 .name = "mcbsp1", 265 .class = &omap2430_mcbsp_hwmod_class, 266 .main_clk = "mcbsp1_fck", 267 .prcm = { 268 .omap2 = { 269 .prcm_reg_id = 1, 270 .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, 271 .module_offs = CORE_MOD, 272 .idlest_reg_id = 1, 273 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, 274 }, 275 }, 276 .opt_clks = mcbsp_opt_clks, 277 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), 278 }; 279 280 /* mcbsp2 */ 281 static struct omap_hwmod omap2430_mcbsp2_hwmod = { 282 .name = "mcbsp2", 283 .class = &omap2430_mcbsp_hwmod_class, 284 .main_clk = "mcbsp2_fck", 285 .prcm = { 286 .omap2 = { 287 .prcm_reg_id = 1, 288 .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, 289 .module_offs = CORE_MOD, 290 .idlest_reg_id = 1, 291 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, 292 }, 293 }, 294 .opt_clks = mcbsp_opt_clks, 295 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), 296 }; 297 298 /* mcbsp3 */ 299 static struct omap_hwmod omap2430_mcbsp3_hwmod = { 300 .name = "mcbsp3", 301 .class = &omap2430_mcbsp_hwmod_class, 302 .main_clk = "mcbsp3_fck", 303 .prcm = { 304 .omap2 = { 305 .prcm_reg_id = 1, 306 .module_bit = OMAP2430_EN_MCBSP3_SHIFT, 307 .module_offs = CORE_MOD, 308 .idlest_reg_id = 2, 309 .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT, 310 }, 311 }, 312 .opt_clks = mcbsp_opt_clks, 313 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), 314 }; 315 316 /* mcbsp4 */ 317 static struct omap_hwmod omap2430_mcbsp4_hwmod = { 318 .name = "mcbsp4", 319 .class = &omap2430_mcbsp_hwmod_class, 320 .main_clk = "mcbsp4_fck", 321 .prcm = { 322 .omap2 = { 323 .prcm_reg_id = 1, 324 .module_bit = OMAP2430_EN_MCBSP4_SHIFT, 325 .module_offs = CORE_MOD, 326 .idlest_reg_id = 2, 327 .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT, 328 }, 329 }, 330 .opt_clks = mcbsp_opt_clks, 331 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), 332 }; 333 334 /* mcbsp5 */ 335 static struct omap_hwmod omap2430_mcbsp5_hwmod = { 336 .name = "mcbsp5", 337 .class = &omap2430_mcbsp_hwmod_class, 338 .main_clk = "mcbsp5_fck", 339 .prcm = { 340 .omap2 = { 341 .prcm_reg_id = 1, 342 .module_bit = OMAP2430_EN_MCBSP5_SHIFT, 343 .module_offs = CORE_MOD, 344 .idlest_reg_id = 2, 345 .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT, 346 }, 347 }, 348 .opt_clks = mcbsp_opt_clks, 349 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), 350 }; 351 352 /* MMC/SD/SDIO common */ 353 static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = { 354 .rev_offs = 0x1fc, 355 .sysc_offs = 0x10, 356 .syss_offs = 0x14, 357 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 358 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 359 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 360 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 361 .sysc_fields = &omap_hwmod_sysc_type1, 362 }; 363 364 static struct omap_hwmod_class omap2430_mmc_class = { 365 .name = "mmc", 366 .sysc = &omap2430_mmc_sysc, 367 }; 368 369 /* MMC/SD/SDIO1 */ 370 static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = { 371 { .role = "dbck", .clk = "mmchsdb1_fck" }, 372 }; 373 374 static struct omap_hsmmc_dev_attr mmc1_dev_attr = { 375 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, 376 }; 377 378 static struct omap_hwmod omap2430_mmc1_hwmod = { 379 .name = "mmc1", 380 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 381 .opt_clks = omap2430_mmc1_opt_clks, 382 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks), 383 .main_clk = "mmchs1_fck", 384 .prcm = { 385 .omap2 = { 386 .module_offs = CORE_MOD, 387 .prcm_reg_id = 2, 388 .module_bit = OMAP2430_EN_MMCHS1_SHIFT, 389 .idlest_reg_id = 2, 390 .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT, 391 }, 392 }, 393 .dev_attr = &mmc1_dev_attr, 394 .class = &omap2430_mmc_class, 395 }; 396 397 /* MMC/SD/SDIO2 */ 398 static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = { 399 { .role = "dbck", .clk = "mmchsdb2_fck" }, 400 }; 401 402 static struct omap_hwmod omap2430_mmc2_hwmod = { 403 .name = "mmc2", 404 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 405 .opt_clks = omap2430_mmc2_opt_clks, 406 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks), 407 .main_clk = "mmchs2_fck", 408 .prcm = { 409 .omap2 = { 410 .module_offs = CORE_MOD, 411 .prcm_reg_id = 2, 412 .module_bit = OMAP2430_EN_MMCHS2_SHIFT, 413 .idlest_reg_id = 2, 414 .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT, 415 }, 416 }, 417 .class = &omap2430_mmc_class, 418 }; 419 420 /* HDQ1W/1-wire */ 421 static struct omap_hwmod omap2430_hdq1w_hwmod = { 422 .name = "hdq1w", 423 .main_clk = "hdq_fck", 424 .prcm = { 425 .omap2 = { 426 .module_offs = CORE_MOD, 427 .prcm_reg_id = 1, 428 .module_bit = OMAP24XX_EN_HDQ_SHIFT, 429 .idlest_reg_id = 1, 430 .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT, 431 }, 432 }, 433 .class = &omap2_hdq1w_class, 434 }; 435 436 /* 437 * interfaces 438 */ 439 440 /* L3 -> L4_CORE interface */ 441 /* l3_core -> usbhsotg interface */ 442 static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = { 443 .master = &omap2430_usbhsotg_hwmod, 444 .slave = &omap2xxx_l3_main_hwmod, 445 .clk = "core_l3_ck", 446 .user = OCP_USER_MPU, 447 }; 448 449 /* L4 CORE -> I2C1 interface */ 450 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { 451 .master = &omap2xxx_l4_core_hwmod, 452 .slave = &omap2430_i2c1_hwmod, 453 .clk = "i2c1_ick", 454 .user = OCP_USER_MPU | OCP_USER_SDMA, 455 }; 456 457 /* L4 CORE -> I2C2 interface */ 458 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { 459 .master = &omap2xxx_l4_core_hwmod, 460 .slave = &omap2430_i2c2_hwmod, 461 .clk = "i2c2_ick", 462 .user = OCP_USER_MPU | OCP_USER_SDMA, 463 }; 464 465 /* l4_core ->usbhsotg interface */ 466 static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = { 467 .master = &omap2xxx_l4_core_hwmod, 468 .slave = &omap2430_usbhsotg_hwmod, 469 .clk = "usb_l4_ick", 470 .user = OCP_USER_MPU, 471 }; 472 473 /* L4 CORE -> MMC1 interface */ 474 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = { 475 .master = &omap2xxx_l4_core_hwmod, 476 .slave = &omap2430_mmc1_hwmod, 477 .clk = "mmchs1_ick", 478 .user = OCP_USER_MPU | OCP_USER_SDMA, 479 }; 480 481 /* L4 CORE -> MMC2 interface */ 482 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = { 483 .master = &omap2xxx_l4_core_hwmod, 484 .slave = &omap2430_mmc2_hwmod, 485 .clk = "mmchs2_ick", 486 .user = OCP_USER_MPU | OCP_USER_SDMA, 487 }; 488 489 /* l4 core -> mcspi3 interface */ 490 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = { 491 .master = &omap2xxx_l4_core_hwmod, 492 .slave = &omap2430_mcspi3_hwmod, 493 .clk = "mcspi3_ick", 494 .user = OCP_USER_MPU | OCP_USER_SDMA, 495 }; 496 497 /* IVA2 <- L3 interface */ 498 static struct omap_hwmod_ocp_if omap2430_l3__iva = { 499 .master = &omap2xxx_l3_main_hwmod, 500 .slave = &omap2430_iva_hwmod, 501 .clk = "core_l3_ck", 502 .user = OCP_USER_MPU | OCP_USER_SDMA, 503 }; 504 505 /* l4_wkup -> timer1 */ 506 static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = { 507 .master = &omap2xxx_l4_wkup_hwmod, 508 .slave = &omap2xxx_timer1_hwmod, 509 .clk = "gpt1_ick", 510 .user = OCP_USER_MPU | OCP_USER_SDMA, 511 }; 512 513 /* l4_wkup -> wd_timer2 */ 514 static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { 515 .master = &omap2xxx_l4_wkup_hwmod, 516 .slave = &omap2xxx_wd_timer2_hwmod, 517 .clk = "mpu_wdt_ick", 518 .user = OCP_USER_MPU | OCP_USER_SDMA, 519 }; 520 521 /* l4_wkup -> gpio1 */ 522 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { 523 .master = &omap2xxx_l4_wkup_hwmod, 524 .slave = &omap2xxx_gpio1_hwmod, 525 .clk = "gpios_ick", 526 .user = OCP_USER_MPU | OCP_USER_SDMA, 527 }; 528 529 /* l4_wkup -> gpio2 */ 530 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { 531 .master = &omap2xxx_l4_wkup_hwmod, 532 .slave = &omap2xxx_gpio2_hwmod, 533 .clk = "gpios_ick", 534 .user = OCP_USER_MPU | OCP_USER_SDMA, 535 }; 536 537 /* l4_wkup -> gpio3 */ 538 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { 539 .master = &omap2xxx_l4_wkup_hwmod, 540 .slave = &omap2xxx_gpio3_hwmod, 541 .clk = "gpios_ick", 542 .user = OCP_USER_MPU | OCP_USER_SDMA, 543 }; 544 545 /* l4_wkup -> gpio4 */ 546 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { 547 .master = &omap2xxx_l4_wkup_hwmod, 548 .slave = &omap2xxx_gpio4_hwmod, 549 .clk = "gpios_ick", 550 .user = OCP_USER_MPU | OCP_USER_SDMA, 551 }; 552 553 /* l4_core -> gpio5 */ 554 static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { 555 .master = &omap2xxx_l4_core_hwmod, 556 .slave = &omap2430_gpio5_hwmod, 557 .clk = "gpio5_ick", 558 .user = OCP_USER_MPU | OCP_USER_SDMA, 559 }; 560 561 /* dma_system -> L3 */ 562 static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { 563 .master = &omap2430_dma_system_hwmod, 564 .slave = &omap2xxx_l3_main_hwmod, 565 .clk = "core_l3_ck", 566 .user = OCP_USER_MPU | OCP_USER_SDMA, 567 }; 568 569 /* l4_core -> dma_system */ 570 static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { 571 .master = &omap2xxx_l4_core_hwmod, 572 .slave = &omap2430_dma_system_hwmod, 573 .clk = "sdma_ick", 574 .user = OCP_USER_MPU | OCP_USER_SDMA, 575 }; 576 577 /* l4_core -> mailbox */ 578 static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = { 579 .master = &omap2xxx_l4_core_hwmod, 580 .slave = &omap2430_mailbox_hwmod, 581 .user = OCP_USER_MPU | OCP_USER_SDMA, 582 }; 583 584 /* l4_core -> mcbsp1 */ 585 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = { 586 .master = &omap2xxx_l4_core_hwmod, 587 .slave = &omap2430_mcbsp1_hwmod, 588 .clk = "mcbsp1_ick", 589 .user = OCP_USER_MPU | OCP_USER_SDMA, 590 }; 591 592 /* l4_core -> mcbsp2 */ 593 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = { 594 .master = &omap2xxx_l4_core_hwmod, 595 .slave = &omap2430_mcbsp2_hwmod, 596 .clk = "mcbsp2_ick", 597 .user = OCP_USER_MPU | OCP_USER_SDMA, 598 }; 599 600 /* l4_core -> mcbsp3 */ 601 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = { 602 .master = &omap2xxx_l4_core_hwmod, 603 .slave = &omap2430_mcbsp3_hwmod, 604 .clk = "mcbsp3_ick", 605 .user = OCP_USER_MPU | OCP_USER_SDMA, 606 }; 607 608 /* l4_core -> mcbsp4 */ 609 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = { 610 .master = &omap2xxx_l4_core_hwmod, 611 .slave = &omap2430_mcbsp4_hwmod, 612 .clk = "mcbsp4_ick", 613 .user = OCP_USER_MPU | OCP_USER_SDMA, 614 }; 615 616 /* l4_core -> mcbsp5 */ 617 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = { 618 .master = &omap2xxx_l4_core_hwmod, 619 .slave = &omap2430_mcbsp5_hwmod, 620 .clk = "mcbsp5_ick", 621 .user = OCP_USER_MPU | OCP_USER_SDMA, 622 }; 623 624 /* l4_core -> hdq1w */ 625 static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = { 626 .master = &omap2xxx_l4_core_hwmod, 627 .slave = &omap2430_hdq1w_hwmod, 628 .clk = "hdq_ick", 629 .user = OCP_USER_MPU | OCP_USER_SDMA, 630 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, 631 }; 632 633 /* l4_wkup -> 32ksync_counter */ 634 static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = { 635 .master = &omap2xxx_l4_wkup_hwmod, 636 .slave = &omap2xxx_counter_32k_hwmod, 637 .clk = "sync_32k_ick", 638 .user = OCP_USER_MPU | OCP_USER_SDMA, 639 }; 640 641 static struct omap_hwmod_ocp_if omap2430_l3__gpmc = { 642 .master = &omap2xxx_l3_main_hwmod, 643 .slave = &omap2xxx_gpmc_hwmod, 644 .clk = "core_l3_ck", 645 .user = OCP_USER_MPU | OCP_USER_SDMA, 646 }; 647 648 static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = { 649 &omap2xxx_l3_main__l4_core, 650 &omap2xxx_mpu__l3_main, 651 &omap2xxx_dss__l3, 652 &omap2430_usbhsotg__l3, 653 &omap2430_l4_core__i2c1, 654 &omap2430_l4_core__i2c2, 655 &omap2xxx_l4_core__l4_wkup, 656 &omap2_l4_core__uart1, 657 &omap2_l4_core__uart2, 658 &omap2_l4_core__uart3, 659 &omap2430_l4_core__usbhsotg, 660 &omap2430_l4_core__mmc1, 661 &omap2430_l4_core__mmc2, 662 &omap2xxx_l4_core__mcspi1, 663 &omap2xxx_l4_core__mcspi2, 664 &omap2430_l4_core__mcspi3, 665 &omap2430_l3__iva, 666 &omap2430_l4_wkup__timer1, 667 &omap2xxx_l4_core__timer2, 668 &omap2xxx_l4_core__timer3, 669 &omap2xxx_l4_core__timer4, 670 &omap2xxx_l4_core__timer5, 671 &omap2xxx_l4_core__timer6, 672 &omap2xxx_l4_core__timer7, 673 &omap2xxx_l4_core__timer8, 674 &omap2xxx_l4_core__timer9, 675 &omap2xxx_l4_core__timer10, 676 &omap2xxx_l4_core__timer11, 677 &omap2xxx_l4_core__timer12, 678 &omap2430_l4_wkup__wd_timer2, 679 &omap2xxx_l4_core__dss, 680 &omap2xxx_l4_core__dss_dispc, 681 &omap2xxx_l4_core__dss_rfbi, 682 &omap2xxx_l4_core__dss_venc, 683 &omap2430_l4_wkup__gpio1, 684 &omap2430_l4_wkup__gpio2, 685 &omap2430_l4_wkup__gpio3, 686 &omap2430_l4_wkup__gpio4, 687 &omap2430_l4_core__gpio5, 688 &omap2430_dma_system__l3, 689 &omap2430_l4_core__dma_system, 690 &omap2430_l4_core__mailbox, 691 &omap2430_l4_core__mcbsp1, 692 &omap2430_l4_core__mcbsp2, 693 &omap2430_l4_core__mcbsp3, 694 &omap2430_l4_core__mcbsp4, 695 &omap2430_l4_core__mcbsp5, 696 &omap2430_l4_core__hdq1w, 697 &omap2xxx_l4_core__rng, 698 &omap2xxx_l4_core__sham, 699 &omap2xxx_l4_core__aes, 700 &omap2430_l4_wkup__counter_32k, 701 &omap2430_l3__gpmc, 702 NULL, 703 }; 704 705 int __init omap2430_hwmod_init(void) 706 { 707 omap_hwmod_init(); 708 return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs); 709 } 710