17359154eSPaul Walmsley /* 27359154eSPaul Walmsley * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips 37359154eSPaul Walmsley * 47359154eSPaul Walmsley * Copyright (C) 2009-2010 Nokia Corporation 57359154eSPaul Walmsley * Paul Walmsley 67359154eSPaul Walmsley * 77359154eSPaul Walmsley * This program is free software; you can redistribute it and/or modify 87359154eSPaul Walmsley * it under the terms of the GNU General Public License version 2 as 97359154eSPaul Walmsley * published by the Free Software Foundation. 107359154eSPaul Walmsley * 117359154eSPaul Walmsley * XXX handle crossbar/shared link difference for L3? 127359154eSPaul Walmsley * XXX these should be marked initdata for multi-OMAP kernels 137359154eSPaul Walmsley */ 147359154eSPaul Walmsley #include <plat/omap_hwmod.h> 157359154eSPaul Walmsley #include <mach/irqs.h> 167359154eSPaul Walmsley #include <plat/cpu.h> 177359154eSPaul Walmsley #include <plat/dma.h> 18046465b7SKevin Hilman #include <plat/serial.h> 192004290fSPaul Walmsley #include <plat/i2c.h> 20aeac0e44SVaradarajan, Charulatha #include <plat/gpio.h> 217f904c78SCharulatha V #include <plat/mcspi.h> 22b6b58229SThara Gopinath #include <plat/dmtimer.h> 23de56dbb6SSenthilvadivu Guruswamy #include <plat/l3_2xxx.h> 247359154eSPaul Walmsley 2543b40992SPaul Walmsley #include "omap_hwmod_common_data.h" 2643b40992SPaul Walmsley 277359154eSPaul Walmsley #include "prm-regbits-24xx.h" 28165e2161SVaradarajan, Charulatha #include "cm-regbits-24xx.h" 29ff2516fbSPaul Walmsley #include "wd_timer.h" 307359154eSPaul Walmsley 317359154eSPaul Walmsley /* 327359154eSPaul Walmsley * OMAP2430 hardware module integration data 337359154eSPaul Walmsley * 347359154eSPaul Walmsley * ALl of the data in this section should be autogeneratable from the 357359154eSPaul Walmsley * TI hardware database or other technical documentation. Data that 367359154eSPaul Walmsley * is driver-specific or driver-kernel integration-specific belongs 377359154eSPaul Walmsley * elsewhere. 387359154eSPaul Walmsley */ 397359154eSPaul Walmsley 407359154eSPaul Walmsley static struct omap_hwmod omap2430_mpu_hwmod; 4108072acfSPaul Walmsley static struct omap_hwmod omap2430_iva_hwmod; 424a7cf90aSKevin Hilman static struct omap_hwmod omap2430_l3_main_hwmod; 437359154eSPaul Walmsley static struct omap_hwmod omap2430_l4_core_hwmod; 44de56dbb6SSenthilvadivu Guruswamy static struct omap_hwmod omap2430_dss_core_hwmod; 45de56dbb6SSenthilvadivu Guruswamy static struct omap_hwmod omap2430_dss_dispc_hwmod; 46de56dbb6SSenthilvadivu Guruswamy static struct omap_hwmod omap2430_dss_rfbi_hwmod; 47de56dbb6SSenthilvadivu Guruswamy static struct omap_hwmod omap2430_dss_venc_hwmod; 48165e2161SVaradarajan, Charulatha static struct omap_hwmod omap2430_wd_timer2_hwmod; 49aeac0e44SVaradarajan, Charulatha static struct omap_hwmod omap2430_gpio1_hwmod; 50aeac0e44SVaradarajan, Charulatha static struct omap_hwmod omap2430_gpio2_hwmod; 51aeac0e44SVaradarajan, Charulatha static struct omap_hwmod omap2430_gpio3_hwmod; 52aeac0e44SVaradarajan, Charulatha static struct omap_hwmod omap2430_gpio4_hwmod; 53aeac0e44SVaradarajan, Charulatha static struct omap_hwmod omap2430_gpio5_hwmod; 5482cbd1aeSG, Manjunath Kondaiah static struct omap_hwmod omap2430_dma_system_hwmod; 557f904c78SCharulatha V static struct omap_hwmod omap2430_mcspi1_hwmod; 567f904c78SCharulatha V static struct omap_hwmod omap2430_mcspi2_hwmod; 577f904c78SCharulatha V static struct omap_hwmod omap2430_mcspi3_hwmod; 587359154eSPaul Walmsley 597359154eSPaul Walmsley /* L3 -> L4_CORE interface */ 604a7cf90aSKevin Hilman static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { 614a7cf90aSKevin Hilman .master = &omap2430_l3_main_hwmod, 627359154eSPaul Walmsley .slave = &omap2430_l4_core_hwmod, 637359154eSPaul Walmsley .user = OCP_USER_MPU | OCP_USER_SDMA, 647359154eSPaul Walmsley }; 657359154eSPaul Walmsley 667359154eSPaul Walmsley /* MPU -> L3 interface */ 674a7cf90aSKevin Hilman static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = { 687359154eSPaul Walmsley .master = &omap2430_mpu_hwmod, 694a7cf90aSKevin Hilman .slave = &omap2430_l3_main_hwmod, 707359154eSPaul Walmsley .user = OCP_USER_MPU, 717359154eSPaul Walmsley }; 727359154eSPaul Walmsley 737359154eSPaul Walmsley /* Slave interfaces on the L3 interconnect */ 744a7cf90aSKevin Hilman static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = { 754a7cf90aSKevin Hilman &omap2430_mpu__l3_main, 767359154eSPaul Walmsley }; 777359154eSPaul Walmsley 78de56dbb6SSenthilvadivu Guruswamy /* DSS -> l3 */ 79de56dbb6SSenthilvadivu Guruswamy static struct omap_hwmod_ocp_if omap2430_dss__l3 = { 80de56dbb6SSenthilvadivu Guruswamy .master = &omap2430_dss_core_hwmod, 81de56dbb6SSenthilvadivu Guruswamy .slave = &omap2430_l3_main_hwmod, 82de56dbb6SSenthilvadivu Guruswamy .fw = { 83de56dbb6SSenthilvadivu Guruswamy .omap2 = { 84de56dbb6SSenthilvadivu Guruswamy .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, 85de56dbb6SSenthilvadivu Guruswamy .flags = OMAP_FIREWALL_L3, 86de56dbb6SSenthilvadivu Guruswamy } 87de56dbb6SSenthilvadivu Guruswamy }, 88de56dbb6SSenthilvadivu Guruswamy .user = OCP_USER_MPU | OCP_USER_SDMA, 89de56dbb6SSenthilvadivu Guruswamy }; 90de56dbb6SSenthilvadivu Guruswamy 917359154eSPaul Walmsley /* Master interfaces on the L3 interconnect */ 924a7cf90aSKevin Hilman static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = { 934a7cf90aSKevin Hilman &omap2430_l3_main__l4_core, 947359154eSPaul Walmsley }; 957359154eSPaul Walmsley 967359154eSPaul Walmsley /* L3 */ 974a7cf90aSKevin Hilman static struct omap_hwmod omap2430_l3_main_hwmod = { 98fa98347eSBenoit Cousson .name = "l3_main", 9943b40992SPaul Walmsley .class = &l3_hwmod_class, 1004a7cf90aSKevin Hilman .masters = omap2430_l3_main_masters, 1014a7cf90aSKevin Hilman .masters_cnt = ARRAY_SIZE(omap2430_l3_main_masters), 1024a7cf90aSKevin Hilman .slaves = omap2430_l3_main_slaves, 1034a7cf90aSKevin Hilman .slaves_cnt = ARRAY_SIZE(omap2430_l3_main_slaves), 1042eb1875dSKevin Hilman .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1052eb1875dSKevin Hilman .flags = HWMOD_NO_IDLEST, 1067359154eSPaul Walmsley }; 1077359154eSPaul Walmsley 1087359154eSPaul Walmsley static struct omap_hwmod omap2430_l4_wkup_hwmod; 109046465b7SKevin Hilman static struct omap_hwmod omap2430_uart1_hwmod; 110046465b7SKevin Hilman static struct omap_hwmod omap2430_uart2_hwmod; 111046465b7SKevin Hilman static struct omap_hwmod omap2430_uart3_hwmod; 1122004290fSPaul Walmsley static struct omap_hwmod omap2430_i2c1_hwmod; 1132004290fSPaul Walmsley static struct omap_hwmod omap2430_i2c2_hwmod; 1142004290fSPaul Walmsley 11544d02acfSHema HK static struct omap_hwmod omap2430_usbhsotg_hwmod; 11644d02acfSHema HK 11744d02acfSHema HK /* l3_core -> usbhsotg interface */ 11844d02acfSHema HK static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = { 11944d02acfSHema HK .master = &omap2430_usbhsotg_hwmod, 12044d02acfSHema HK .slave = &omap2430_l3_main_hwmod, 12144d02acfSHema HK .clk = "core_l3_ck", 12244d02acfSHema HK .user = OCP_USER_MPU, 12344d02acfSHema HK }; 12444d02acfSHema HK 1252004290fSPaul Walmsley /* I2C IP block address space length (in bytes) */ 1262004290fSPaul Walmsley #define OMAP2_I2C_AS_LEN 128 1272004290fSPaul Walmsley 1282004290fSPaul Walmsley /* L4 CORE -> I2C1 interface */ 1292004290fSPaul Walmsley static struct omap_hwmod_addr_space omap2430_i2c1_addr_space[] = { 1302004290fSPaul Walmsley { 1312004290fSPaul Walmsley .pa_start = 0x48070000, 1322004290fSPaul Walmsley .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1, 1332004290fSPaul Walmsley .flags = ADDR_TYPE_RT, 1342004290fSPaul Walmsley }, 1352004290fSPaul Walmsley }; 1362004290fSPaul Walmsley 1372004290fSPaul Walmsley static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { 1382004290fSPaul Walmsley .master = &omap2430_l4_core_hwmod, 1392004290fSPaul Walmsley .slave = &omap2430_i2c1_hwmod, 1402004290fSPaul Walmsley .clk = "i2c1_ick", 1412004290fSPaul Walmsley .addr = omap2430_i2c1_addr_space, 1422004290fSPaul Walmsley .addr_cnt = ARRAY_SIZE(omap2430_i2c1_addr_space), 1432004290fSPaul Walmsley .user = OCP_USER_MPU | OCP_USER_SDMA, 1442004290fSPaul Walmsley }; 1452004290fSPaul Walmsley 1462004290fSPaul Walmsley /* L4 CORE -> I2C2 interface */ 1472004290fSPaul Walmsley static struct omap_hwmod_addr_space omap2430_i2c2_addr_space[] = { 1482004290fSPaul Walmsley { 1492004290fSPaul Walmsley .pa_start = 0x48072000, 1502004290fSPaul Walmsley .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1, 1512004290fSPaul Walmsley .flags = ADDR_TYPE_RT, 1522004290fSPaul Walmsley }, 1532004290fSPaul Walmsley }; 1542004290fSPaul Walmsley 1552004290fSPaul Walmsley static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { 1562004290fSPaul Walmsley .master = &omap2430_l4_core_hwmod, 1572004290fSPaul Walmsley .slave = &omap2430_i2c2_hwmod, 1582004290fSPaul Walmsley .clk = "i2c2_ick", 1592004290fSPaul Walmsley .addr = omap2430_i2c2_addr_space, 1602004290fSPaul Walmsley .addr_cnt = ARRAY_SIZE(omap2430_i2c2_addr_space), 1612004290fSPaul Walmsley .user = OCP_USER_MPU | OCP_USER_SDMA, 1622004290fSPaul Walmsley }; 1637359154eSPaul Walmsley 1647359154eSPaul Walmsley /* L4_CORE -> L4_WKUP interface */ 1657359154eSPaul Walmsley static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { 1667359154eSPaul Walmsley .master = &omap2430_l4_core_hwmod, 1677359154eSPaul Walmsley .slave = &omap2430_l4_wkup_hwmod, 1687359154eSPaul Walmsley .user = OCP_USER_MPU | OCP_USER_SDMA, 1697359154eSPaul Walmsley }; 1707359154eSPaul Walmsley 171046465b7SKevin Hilman /* L4 CORE -> UART1 interface */ 172046465b7SKevin Hilman static struct omap_hwmod_addr_space omap2430_uart1_addr_space[] = { 173046465b7SKevin Hilman { 174046465b7SKevin Hilman .pa_start = OMAP2_UART1_BASE, 175046465b7SKevin Hilman .pa_end = OMAP2_UART1_BASE + SZ_8K - 1, 176046465b7SKevin Hilman .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 177046465b7SKevin Hilman }, 178046465b7SKevin Hilman }; 179046465b7SKevin Hilman 180046465b7SKevin Hilman static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { 181046465b7SKevin Hilman .master = &omap2430_l4_core_hwmod, 182046465b7SKevin Hilman .slave = &omap2430_uart1_hwmod, 183046465b7SKevin Hilman .clk = "uart1_ick", 184046465b7SKevin Hilman .addr = omap2430_uart1_addr_space, 185046465b7SKevin Hilman .addr_cnt = ARRAY_SIZE(omap2430_uart1_addr_space), 186046465b7SKevin Hilman .user = OCP_USER_MPU | OCP_USER_SDMA, 187046465b7SKevin Hilman }; 188046465b7SKevin Hilman 189046465b7SKevin Hilman /* L4 CORE -> UART2 interface */ 190046465b7SKevin Hilman static struct omap_hwmod_addr_space omap2430_uart2_addr_space[] = { 191046465b7SKevin Hilman { 192046465b7SKevin Hilman .pa_start = OMAP2_UART2_BASE, 193046465b7SKevin Hilman .pa_end = OMAP2_UART2_BASE + SZ_1K - 1, 194046465b7SKevin Hilman .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 195046465b7SKevin Hilman }, 196046465b7SKevin Hilman }; 197046465b7SKevin Hilman 198046465b7SKevin Hilman static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { 199046465b7SKevin Hilman .master = &omap2430_l4_core_hwmod, 200046465b7SKevin Hilman .slave = &omap2430_uart2_hwmod, 201046465b7SKevin Hilman .clk = "uart2_ick", 202046465b7SKevin Hilman .addr = omap2430_uart2_addr_space, 203046465b7SKevin Hilman .addr_cnt = ARRAY_SIZE(omap2430_uart2_addr_space), 204046465b7SKevin Hilman .user = OCP_USER_MPU | OCP_USER_SDMA, 205046465b7SKevin Hilman }; 206046465b7SKevin Hilman 207046465b7SKevin Hilman /* L4 PER -> UART3 interface */ 208046465b7SKevin Hilman static struct omap_hwmod_addr_space omap2430_uart3_addr_space[] = { 209046465b7SKevin Hilman { 210046465b7SKevin Hilman .pa_start = OMAP2_UART3_BASE, 211046465b7SKevin Hilman .pa_end = OMAP2_UART3_BASE + SZ_1K - 1, 212046465b7SKevin Hilman .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 213046465b7SKevin Hilman }, 214046465b7SKevin Hilman }; 215046465b7SKevin Hilman 216046465b7SKevin Hilman static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { 217046465b7SKevin Hilman .master = &omap2430_l4_core_hwmod, 218046465b7SKevin Hilman .slave = &omap2430_uart3_hwmod, 219046465b7SKevin Hilman .clk = "uart3_ick", 220046465b7SKevin Hilman .addr = omap2430_uart3_addr_space, 221046465b7SKevin Hilman .addr_cnt = ARRAY_SIZE(omap2430_uart3_addr_space), 222046465b7SKevin Hilman .user = OCP_USER_MPU | OCP_USER_SDMA, 223046465b7SKevin Hilman }; 224046465b7SKevin Hilman 22544d02acfSHema HK /* 22644d02acfSHema HK * usbhsotg interface data 22744d02acfSHema HK */ 22844d02acfSHema HK static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = { 22944d02acfSHema HK { 23044d02acfSHema HK .pa_start = OMAP243X_HS_BASE, 23144d02acfSHema HK .pa_end = OMAP243X_HS_BASE + SZ_4K - 1, 23244d02acfSHema HK .flags = ADDR_TYPE_RT 23344d02acfSHema HK }, 23444d02acfSHema HK }; 23544d02acfSHema HK 23644d02acfSHema HK /* l4_core ->usbhsotg interface */ 23744d02acfSHema HK static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = { 23844d02acfSHema HK .master = &omap2430_l4_core_hwmod, 23944d02acfSHema HK .slave = &omap2430_usbhsotg_hwmod, 24044d02acfSHema HK .clk = "usb_l4_ick", 24144d02acfSHema HK .addr = omap2430_usbhsotg_addrs, 24244d02acfSHema HK .addr_cnt = ARRAY_SIZE(omap2430_usbhsotg_addrs), 24344d02acfSHema HK .user = OCP_USER_MPU, 24444d02acfSHema HK }; 24544d02acfSHema HK 24644d02acfSHema HK static struct omap_hwmod_ocp_if *omap2430_usbhsotg_masters[] = { 24744d02acfSHema HK &omap2430_usbhsotg__l3, 24844d02acfSHema HK }; 24944d02acfSHema HK 25044d02acfSHema HK static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = { 25144d02acfSHema HK &omap2430_l4_core__usbhsotg, 25244d02acfSHema HK }; 25344d02acfSHema HK 2547359154eSPaul Walmsley /* Slave interfaces on the L4_CORE interconnect */ 2557359154eSPaul Walmsley static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = { 2564a7cf90aSKevin Hilman &omap2430_l3_main__l4_core, 2577359154eSPaul Walmsley }; 2587359154eSPaul Walmsley 2597359154eSPaul Walmsley /* Master interfaces on the L4_CORE interconnect */ 2607359154eSPaul Walmsley static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = { 2617359154eSPaul Walmsley &omap2430_l4_core__l4_wkup, 2627359154eSPaul Walmsley }; 2637359154eSPaul Walmsley 2647359154eSPaul Walmsley /* L4 CORE */ 2657359154eSPaul Walmsley static struct omap_hwmod omap2430_l4_core_hwmod = { 266fa98347eSBenoit Cousson .name = "l4_core", 26743b40992SPaul Walmsley .class = &l4_hwmod_class, 2687359154eSPaul Walmsley .masters = omap2430_l4_core_masters, 2697359154eSPaul Walmsley .masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters), 2707359154eSPaul Walmsley .slaves = omap2430_l4_core_slaves, 2717359154eSPaul Walmsley .slaves_cnt = ARRAY_SIZE(omap2430_l4_core_slaves), 2722eb1875dSKevin Hilman .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 2732eb1875dSKevin Hilman .flags = HWMOD_NO_IDLEST, 2747359154eSPaul Walmsley }; 2757359154eSPaul Walmsley 2767359154eSPaul Walmsley /* Slave interfaces on the L4_WKUP interconnect */ 2777359154eSPaul Walmsley static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = { 2787359154eSPaul Walmsley &omap2430_l4_core__l4_wkup, 279046465b7SKevin Hilman &omap2_l4_core__uart1, 280046465b7SKevin Hilman &omap2_l4_core__uart2, 281046465b7SKevin Hilman &omap2_l4_core__uart3, 2827359154eSPaul Walmsley }; 2837359154eSPaul Walmsley 2847359154eSPaul Walmsley /* Master interfaces on the L4_WKUP interconnect */ 2857359154eSPaul Walmsley static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = { 2867359154eSPaul Walmsley }; 2877359154eSPaul Walmsley 2887f904c78SCharulatha V /* l4 core -> mcspi1 interface */ 2897f904c78SCharulatha V static struct omap_hwmod_addr_space omap2430_mcspi1_addr_space[] = { 2907f904c78SCharulatha V { 2917f904c78SCharulatha V .pa_start = 0x48098000, 2927f904c78SCharulatha V .pa_end = 0x480980ff, 2937f904c78SCharulatha V .flags = ADDR_TYPE_RT, 2947f904c78SCharulatha V }, 2957f904c78SCharulatha V }; 2967f904c78SCharulatha V 2977f904c78SCharulatha V static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = { 2987f904c78SCharulatha V .master = &omap2430_l4_core_hwmod, 2997f904c78SCharulatha V .slave = &omap2430_mcspi1_hwmod, 3007f904c78SCharulatha V .clk = "mcspi1_ick", 3017f904c78SCharulatha V .addr = omap2430_mcspi1_addr_space, 3027f904c78SCharulatha V .addr_cnt = ARRAY_SIZE(omap2430_mcspi1_addr_space), 3037f904c78SCharulatha V .user = OCP_USER_MPU | OCP_USER_SDMA, 3047f904c78SCharulatha V }; 3057f904c78SCharulatha V 3067f904c78SCharulatha V /* l4 core -> mcspi2 interface */ 3077f904c78SCharulatha V static struct omap_hwmod_addr_space omap2430_mcspi2_addr_space[] = { 3087f904c78SCharulatha V { 3097f904c78SCharulatha V .pa_start = 0x4809a000, 3107f904c78SCharulatha V .pa_end = 0x4809a0ff, 3117f904c78SCharulatha V .flags = ADDR_TYPE_RT, 3127f904c78SCharulatha V }, 3137f904c78SCharulatha V }; 3147f904c78SCharulatha V 3157f904c78SCharulatha V static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = { 3167f904c78SCharulatha V .master = &omap2430_l4_core_hwmod, 3177f904c78SCharulatha V .slave = &omap2430_mcspi2_hwmod, 3187f904c78SCharulatha V .clk = "mcspi2_ick", 3197f904c78SCharulatha V .addr = omap2430_mcspi2_addr_space, 3207f904c78SCharulatha V .addr_cnt = ARRAY_SIZE(omap2430_mcspi2_addr_space), 3217f904c78SCharulatha V .user = OCP_USER_MPU | OCP_USER_SDMA, 3227f904c78SCharulatha V }; 3237f904c78SCharulatha V 3247f904c78SCharulatha V /* l4 core -> mcspi3 interface */ 3257f904c78SCharulatha V static struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = { 3267f904c78SCharulatha V { 3277f904c78SCharulatha V .pa_start = 0x480b8000, 3287f904c78SCharulatha V .pa_end = 0x480b80ff, 3297f904c78SCharulatha V .flags = ADDR_TYPE_RT, 3307f904c78SCharulatha V }, 3317f904c78SCharulatha V }; 3327f904c78SCharulatha V 3337f904c78SCharulatha V static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = { 3347f904c78SCharulatha V .master = &omap2430_l4_core_hwmod, 3357f904c78SCharulatha V .slave = &omap2430_mcspi3_hwmod, 3367f904c78SCharulatha V .clk = "mcspi3_ick", 3377f904c78SCharulatha V .addr = omap2430_mcspi3_addr_space, 3387f904c78SCharulatha V .addr_cnt = ARRAY_SIZE(omap2430_mcspi3_addr_space), 3397f904c78SCharulatha V .user = OCP_USER_MPU | OCP_USER_SDMA, 3407f904c78SCharulatha V }; 3417f904c78SCharulatha V 3427359154eSPaul Walmsley /* L4 WKUP */ 3437359154eSPaul Walmsley static struct omap_hwmod omap2430_l4_wkup_hwmod = { 344fa98347eSBenoit Cousson .name = "l4_wkup", 34543b40992SPaul Walmsley .class = &l4_hwmod_class, 3467359154eSPaul Walmsley .masters = omap2430_l4_wkup_masters, 3477359154eSPaul Walmsley .masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters), 3487359154eSPaul Walmsley .slaves = omap2430_l4_wkup_slaves, 3497359154eSPaul Walmsley .slaves_cnt = ARRAY_SIZE(omap2430_l4_wkup_slaves), 3502eb1875dSKevin Hilman .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 3512eb1875dSKevin Hilman .flags = HWMOD_NO_IDLEST, 3527359154eSPaul Walmsley }; 3537359154eSPaul Walmsley 3547359154eSPaul Walmsley /* Master interfaces on the MPU device */ 3557359154eSPaul Walmsley static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = { 3564a7cf90aSKevin Hilman &omap2430_mpu__l3_main, 3577359154eSPaul Walmsley }; 3587359154eSPaul Walmsley 3597359154eSPaul Walmsley /* MPU */ 3607359154eSPaul Walmsley static struct omap_hwmod omap2430_mpu_hwmod = { 3615c2c0296SBenoit Cousson .name = "mpu", 36243b40992SPaul Walmsley .class = &mpu_hwmod_class, 3637359154eSPaul Walmsley .main_clk = "mpu_ck", 3647359154eSPaul Walmsley .masters = omap2430_mpu_masters, 3657359154eSPaul Walmsley .masters_cnt = ARRAY_SIZE(omap2430_mpu_masters), 3667359154eSPaul Walmsley .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 3677359154eSPaul Walmsley }; 3687359154eSPaul Walmsley 36908072acfSPaul Walmsley /* 37008072acfSPaul Walmsley * IVA2_1 interface data 37108072acfSPaul Walmsley */ 37208072acfSPaul Walmsley 37308072acfSPaul Walmsley /* IVA2 <- L3 interface */ 37408072acfSPaul Walmsley static struct omap_hwmod_ocp_if omap2430_l3__iva = { 37508072acfSPaul Walmsley .master = &omap2430_l3_main_hwmod, 37608072acfSPaul Walmsley .slave = &omap2430_iva_hwmod, 37708072acfSPaul Walmsley .clk = "dsp_fck", 37808072acfSPaul Walmsley .user = OCP_USER_MPU | OCP_USER_SDMA, 37908072acfSPaul Walmsley }; 38008072acfSPaul Walmsley 38108072acfSPaul Walmsley static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = { 38208072acfSPaul Walmsley &omap2430_l3__iva, 38308072acfSPaul Walmsley }; 38408072acfSPaul Walmsley 38508072acfSPaul Walmsley /* 38608072acfSPaul Walmsley * IVA2 (IVA2) 38708072acfSPaul Walmsley */ 38808072acfSPaul Walmsley 38908072acfSPaul Walmsley static struct omap_hwmod omap2430_iva_hwmod = { 39008072acfSPaul Walmsley .name = "iva", 39108072acfSPaul Walmsley .class = &iva_hwmod_class, 39208072acfSPaul Walmsley .masters = omap2430_iva_masters, 39308072acfSPaul Walmsley .masters_cnt = ARRAY_SIZE(omap2430_iva_masters), 39408072acfSPaul Walmsley .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 39508072acfSPaul Walmsley }; 39608072acfSPaul Walmsley 397b6b58229SThara Gopinath /* Timer Common */ 398b6b58229SThara Gopinath static struct omap_hwmod_class_sysconfig omap2430_timer_sysc = { 399b6b58229SThara Gopinath .rev_offs = 0x0000, 400b6b58229SThara Gopinath .sysc_offs = 0x0010, 401b6b58229SThara Gopinath .syss_offs = 0x0014, 402b6b58229SThara Gopinath .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | 403b6b58229SThara Gopinath SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 404b6b58229SThara Gopinath SYSC_HAS_AUTOIDLE), 405b6b58229SThara Gopinath .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 406b6b58229SThara Gopinath .sysc_fields = &omap_hwmod_sysc_type1, 407b6b58229SThara Gopinath }; 408b6b58229SThara Gopinath 409b6b58229SThara Gopinath static struct omap_hwmod_class omap2430_timer_hwmod_class = { 410b6b58229SThara Gopinath .name = "timer", 411b6b58229SThara Gopinath .sysc = &omap2430_timer_sysc, 412b6b58229SThara Gopinath .rev = OMAP_TIMER_IP_VERSION_1, 413b6b58229SThara Gopinath }; 414b6b58229SThara Gopinath 415b6b58229SThara Gopinath /* timer1 */ 416b6b58229SThara Gopinath static struct omap_hwmod omap2430_timer1_hwmod; 417b6b58229SThara Gopinath static struct omap_hwmod_irq_info omap2430_timer1_mpu_irqs[] = { 418b6b58229SThara Gopinath { .irq = 37, }, 419b6b58229SThara Gopinath }; 420b6b58229SThara Gopinath 421b6b58229SThara Gopinath static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = { 422b6b58229SThara Gopinath { 423b6b58229SThara Gopinath .pa_start = 0x49018000, 424b6b58229SThara Gopinath .pa_end = 0x49018000 + SZ_1K - 1, 425b6b58229SThara Gopinath .flags = ADDR_TYPE_RT 426b6b58229SThara Gopinath }, 427b6b58229SThara Gopinath }; 428b6b58229SThara Gopinath 429b6b58229SThara Gopinath /* l4_wkup -> timer1 */ 430b6b58229SThara Gopinath static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = { 431b6b58229SThara Gopinath .master = &omap2430_l4_wkup_hwmod, 432b6b58229SThara Gopinath .slave = &omap2430_timer1_hwmod, 433b6b58229SThara Gopinath .clk = "gpt1_ick", 434b6b58229SThara Gopinath .addr = omap2430_timer1_addrs, 435b6b58229SThara Gopinath .addr_cnt = ARRAY_SIZE(omap2430_timer1_addrs), 436b6b58229SThara Gopinath .user = OCP_USER_MPU | OCP_USER_SDMA, 437b6b58229SThara Gopinath }; 438b6b58229SThara Gopinath 439b6b58229SThara Gopinath /* timer1 slave port */ 440b6b58229SThara Gopinath static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = { 441b6b58229SThara Gopinath &omap2430_l4_wkup__timer1, 442b6b58229SThara Gopinath }; 443b6b58229SThara Gopinath 444b6b58229SThara Gopinath /* timer1 hwmod */ 445b6b58229SThara Gopinath static struct omap_hwmod omap2430_timer1_hwmod = { 446b6b58229SThara Gopinath .name = "timer1", 447b6b58229SThara Gopinath .mpu_irqs = omap2430_timer1_mpu_irqs, 448b6b58229SThara Gopinath .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer1_mpu_irqs), 449b6b58229SThara Gopinath .main_clk = "gpt1_fck", 450b6b58229SThara Gopinath .prcm = { 451b6b58229SThara Gopinath .omap2 = { 452b6b58229SThara Gopinath .prcm_reg_id = 1, 453b6b58229SThara Gopinath .module_bit = OMAP24XX_EN_GPT1_SHIFT, 454b6b58229SThara Gopinath .module_offs = WKUP_MOD, 455b6b58229SThara Gopinath .idlest_reg_id = 1, 456b6b58229SThara Gopinath .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, 457b6b58229SThara Gopinath }, 458b6b58229SThara Gopinath }, 459b6b58229SThara Gopinath .slaves = omap2430_timer1_slaves, 460b6b58229SThara Gopinath .slaves_cnt = ARRAY_SIZE(omap2430_timer1_slaves), 461b6b58229SThara Gopinath .class = &omap2430_timer_hwmod_class, 462b6b58229SThara Gopinath .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 463b6b58229SThara Gopinath }; 464b6b58229SThara Gopinath 465b6b58229SThara Gopinath /* timer2 */ 466b6b58229SThara Gopinath static struct omap_hwmod omap2430_timer2_hwmod; 467b6b58229SThara Gopinath static struct omap_hwmod_irq_info omap2430_timer2_mpu_irqs[] = { 468b6b58229SThara Gopinath { .irq = 38, }, 469b6b58229SThara Gopinath }; 470b6b58229SThara Gopinath 471b6b58229SThara Gopinath static struct omap_hwmod_addr_space omap2430_timer2_addrs[] = { 472b6b58229SThara Gopinath { 473b6b58229SThara Gopinath .pa_start = 0x4802a000, 474b6b58229SThara Gopinath .pa_end = 0x4802a000 + SZ_1K - 1, 475b6b58229SThara Gopinath .flags = ADDR_TYPE_RT 476b6b58229SThara Gopinath }, 477b6b58229SThara Gopinath }; 478b6b58229SThara Gopinath 479b6b58229SThara Gopinath /* l4_core -> timer2 */ 480b6b58229SThara Gopinath static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = { 481b6b58229SThara Gopinath .master = &omap2430_l4_core_hwmod, 482b6b58229SThara Gopinath .slave = &omap2430_timer2_hwmod, 483b6b58229SThara Gopinath .clk = "gpt2_ick", 484b6b58229SThara Gopinath .addr = omap2430_timer2_addrs, 485b6b58229SThara Gopinath .addr_cnt = ARRAY_SIZE(omap2430_timer2_addrs), 486b6b58229SThara Gopinath .user = OCP_USER_MPU | OCP_USER_SDMA, 487b6b58229SThara Gopinath }; 488b6b58229SThara Gopinath 489b6b58229SThara Gopinath /* timer2 slave port */ 490b6b58229SThara Gopinath static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = { 491b6b58229SThara Gopinath &omap2430_l4_core__timer2, 492b6b58229SThara Gopinath }; 493b6b58229SThara Gopinath 494b6b58229SThara Gopinath /* timer2 hwmod */ 495b6b58229SThara Gopinath static struct omap_hwmod omap2430_timer2_hwmod = { 496b6b58229SThara Gopinath .name = "timer2", 497b6b58229SThara Gopinath .mpu_irqs = omap2430_timer2_mpu_irqs, 498b6b58229SThara Gopinath .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer2_mpu_irqs), 499b6b58229SThara Gopinath .main_clk = "gpt2_fck", 500b6b58229SThara Gopinath .prcm = { 501b6b58229SThara Gopinath .omap2 = { 502b6b58229SThara Gopinath .prcm_reg_id = 1, 503b6b58229SThara Gopinath .module_bit = OMAP24XX_EN_GPT2_SHIFT, 504b6b58229SThara Gopinath .module_offs = CORE_MOD, 505b6b58229SThara Gopinath .idlest_reg_id = 1, 506b6b58229SThara Gopinath .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, 507b6b58229SThara Gopinath }, 508b6b58229SThara Gopinath }, 509b6b58229SThara Gopinath .slaves = omap2430_timer2_slaves, 510b6b58229SThara Gopinath .slaves_cnt = ARRAY_SIZE(omap2430_timer2_slaves), 511b6b58229SThara Gopinath .class = &omap2430_timer_hwmod_class, 512b6b58229SThara Gopinath .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 513b6b58229SThara Gopinath }; 514b6b58229SThara Gopinath 515b6b58229SThara Gopinath /* timer3 */ 516b6b58229SThara Gopinath static struct omap_hwmod omap2430_timer3_hwmod; 517b6b58229SThara Gopinath static struct omap_hwmod_irq_info omap2430_timer3_mpu_irqs[] = { 518b6b58229SThara Gopinath { .irq = 39, }, 519b6b58229SThara Gopinath }; 520b6b58229SThara Gopinath 521b6b58229SThara Gopinath static struct omap_hwmod_addr_space omap2430_timer3_addrs[] = { 522b6b58229SThara Gopinath { 523b6b58229SThara Gopinath .pa_start = 0x48078000, 524b6b58229SThara Gopinath .pa_end = 0x48078000 + SZ_1K - 1, 525b6b58229SThara Gopinath .flags = ADDR_TYPE_RT 526b6b58229SThara Gopinath }, 527b6b58229SThara Gopinath }; 528b6b58229SThara Gopinath 529b6b58229SThara Gopinath /* l4_core -> timer3 */ 530b6b58229SThara Gopinath static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = { 531b6b58229SThara Gopinath .master = &omap2430_l4_core_hwmod, 532b6b58229SThara Gopinath .slave = &omap2430_timer3_hwmod, 533b6b58229SThara Gopinath .clk = "gpt3_ick", 534b6b58229SThara Gopinath .addr = omap2430_timer3_addrs, 535b6b58229SThara Gopinath .addr_cnt = ARRAY_SIZE(omap2430_timer3_addrs), 536b6b58229SThara Gopinath .user = OCP_USER_MPU | OCP_USER_SDMA, 537b6b58229SThara Gopinath }; 538b6b58229SThara Gopinath 539b6b58229SThara Gopinath /* timer3 slave port */ 540b6b58229SThara Gopinath static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = { 541b6b58229SThara Gopinath &omap2430_l4_core__timer3, 542b6b58229SThara Gopinath }; 543b6b58229SThara Gopinath 544b6b58229SThara Gopinath /* timer3 hwmod */ 545b6b58229SThara Gopinath static struct omap_hwmod omap2430_timer3_hwmod = { 546b6b58229SThara Gopinath .name = "timer3", 547b6b58229SThara Gopinath .mpu_irqs = omap2430_timer3_mpu_irqs, 548b6b58229SThara Gopinath .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer3_mpu_irqs), 549b6b58229SThara Gopinath .main_clk = "gpt3_fck", 550b6b58229SThara Gopinath .prcm = { 551b6b58229SThara Gopinath .omap2 = { 552b6b58229SThara Gopinath .prcm_reg_id = 1, 553b6b58229SThara Gopinath .module_bit = OMAP24XX_EN_GPT3_SHIFT, 554b6b58229SThara Gopinath .module_offs = CORE_MOD, 555b6b58229SThara Gopinath .idlest_reg_id = 1, 556b6b58229SThara Gopinath .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, 557b6b58229SThara Gopinath }, 558b6b58229SThara Gopinath }, 559b6b58229SThara Gopinath .slaves = omap2430_timer3_slaves, 560b6b58229SThara Gopinath .slaves_cnt = ARRAY_SIZE(omap2430_timer3_slaves), 561b6b58229SThara Gopinath .class = &omap2430_timer_hwmod_class, 562b6b58229SThara Gopinath .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 563b6b58229SThara Gopinath }; 564b6b58229SThara Gopinath 565b6b58229SThara Gopinath /* timer4 */ 566b6b58229SThara Gopinath static struct omap_hwmod omap2430_timer4_hwmod; 567b6b58229SThara Gopinath static struct omap_hwmod_irq_info omap2430_timer4_mpu_irqs[] = { 568b6b58229SThara Gopinath { .irq = 40, }, 569b6b58229SThara Gopinath }; 570b6b58229SThara Gopinath 571b6b58229SThara Gopinath static struct omap_hwmod_addr_space omap2430_timer4_addrs[] = { 572b6b58229SThara Gopinath { 573b6b58229SThara Gopinath .pa_start = 0x4807a000, 574b6b58229SThara Gopinath .pa_end = 0x4807a000 + SZ_1K - 1, 575b6b58229SThara Gopinath .flags = ADDR_TYPE_RT 576b6b58229SThara Gopinath }, 577b6b58229SThara Gopinath }; 578b6b58229SThara Gopinath 579b6b58229SThara Gopinath /* l4_core -> timer4 */ 580b6b58229SThara Gopinath static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = { 581b6b58229SThara Gopinath .master = &omap2430_l4_core_hwmod, 582b6b58229SThara Gopinath .slave = &omap2430_timer4_hwmod, 583b6b58229SThara Gopinath .clk = "gpt4_ick", 584b6b58229SThara Gopinath .addr = omap2430_timer4_addrs, 585b6b58229SThara Gopinath .addr_cnt = ARRAY_SIZE(omap2430_timer4_addrs), 586b6b58229SThara Gopinath .user = OCP_USER_MPU | OCP_USER_SDMA, 587b6b58229SThara Gopinath }; 588b6b58229SThara Gopinath 589b6b58229SThara Gopinath /* timer4 slave port */ 590b6b58229SThara Gopinath static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = { 591b6b58229SThara Gopinath &omap2430_l4_core__timer4, 592b6b58229SThara Gopinath }; 593b6b58229SThara Gopinath 594b6b58229SThara Gopinath /* timer4 hwmod */ 595b6b58229SThara Gopinath static struct omap_hwmod omap2430_timer4_hwmod = { 596b6b58229SThara Gopinath .name = "timer4", 597b6b58229SThara Gopinath .mpu_irqs = omap2430_timer4_mpu_irqs, 598b6b58229SThara Gopinath .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer4_mpu_irqs), 599b6b58229SThara Gopinath .main_clk = "gpt4_fck", 600b6b58229SThara Gopinath .prcm = { 601b6b58229SThara Gopinath .omap2 = { 602b6b58229SThara Gopinath .prcm_reg_id = 1, 603b6b58229SThara Gopinath .module_bit = OMAP24XX_EN_GPT4_SHIFT, 604b6b58229SThara Gopinath .module_offs = CORE_MOD, 605b6b58229SThara Gopinath .idlest_reg_id = 1, 606b6b58229SThara Gopinath .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, 607b6b58229SThara Gopinath }, 608b6b58229SThara Gopinath }, 609b6b58229SThara Gopinath .slaves = omap2430_timer4_slaves, 610b6b58229SThara Gopinath .slaves_cnt = ARRAY_SIZE(omap2430_timer4_slaves), 611b6b58229SThara Gopinath .class = &omap2430_timer_hwmod_class, 612b6b58229SThara Gopinath .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 613b6b58229SThara Gopinath }; 614b6b58229SThara Gopinath 615b6b58229SThara Gopinath /* timer5 */ 616b6b58229SThara Gopinath static struct omap_hwmod omap2430_timer5_hwmod; 617b6b58229SThara Gopinath static struct omap_hwmod_irq_info omap2430_timer5_mpu_irqs[] = { 618b6b58229SThara Gopinath { .irq = 41, }, 619b6b58229SThara Gopinath }; 620b6b58229SThara Gopinath 621b6b58229SThara Gopinath static struct omap_hwmod_addr_space omap2430_timer5_addrs[] = { 622b6b58229SThara Gopinath { 623b6b58229SThara Gopinath .pa_start = 0x4807c000, 624b6b58229SThara Gopinath .pa_end = 0x4807c000 + SZ_1K - 1, 625b6b58229SThara Gopinath .flags = ADDR_TYPE_RT 626b6b58229SThara Gopinath }, 627b6b58229SThara Gopinath }; 628b6b58229SThara Gopinath 629b6b58229SThara Gopinath /* l4_core -> timer5 */ 630b6b58229SThara Gopinath static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = { 631b6b58229SThara Gopinath .master = &omap2430_l4_core_hwmod, 632b6b58229SThara Gopinath .slave = &omap2430_timer5_hwmod, 633b6b58229SThara Gopinath .clk = "gpt5_ick", 634b6b58229SThara Gopinath .addr = omap2430_timer5_addrs, 635b6b58229SThara Gopinath .addr_cnt = ARRAY_SIZE(omap2430_timer5_addrs), 636b6b58229SThara Gopinath .user = OCP_USER_MPU | OCP_USER_SDMA, 637b6b58229SThara Gopinath }; 638b6b58229SThara Gopinath 639b6b58229SThara Gopinath /* timer5 slave port */ 640b6b58229SThara Gopinath static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = { 641b6b58229SThara Gopinath &omap2430_l4_core__timer5, 642b6b58229SThara Gopinath }; 643b6b58229SThara Gopinath 644b6b58229SThara Gopinath /* timer5 hwmod */ 645b6b58229SThara Gopinath static struct omap_hwmod omap2430_timer5_hwmod = { 646b6b58229SThara Gopinath .name = "timer5", 647b6b58229SThara Gopinath .mpu_irqs = omap2430_timer5_mpu_irqs, 648b6b58229SThara Gopinath .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer5_mpu_irqs), 649b6b58229SThara Gopinath .main_clk = "gpt5_fck", 650b6b58229SThara Gopinath .prcm = { 651b6b58229SThara Gopinath .omap2 = { 652b6b58229SThara Gopinath .prcm_reg_id = 1, 653b6b58229SThara Gopinath .module_bit = OMAP24XX_EN_GPT5_SHIFT, 654b6b58229SThara Gopinath .module_offs = CORE_MOD, 655b6b58229SThara Gopinath .idlest_reg_id = 1, 656b6b58229SThara Gopinath .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, 657b6b58229SThara Gopinath }, 658b6b58229SThara Gopinath }, 659b6b58229SThara Gopinath .slaves = omap2430_timer5_slaves, 660b6b58229SThara Gopinath .slaves_cnt = ARRAY_SIZE(omap2430_timer5_slaves), 661b6b58229SThara Gopinath .class = &omap2430_timer_hwmod_class, 662b6b58229SThara Gopinath .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 663b6b58229SThara Gopinath }; 664b6b58229SThara Gopinath 665b6b58229SThara Gopinath /* timer6 */ 666b6b58229SThara Gopinath static struct omap_hwmod omap2430_timer6_hwmod; 667b6b58229SThara Gopinath static struct omap_hwmod_irq_info omap2430_timer6_mpu_irqs[] = { 668b6b58229SThara Gopinath { .irq = 42, }, 669b6b58229SThara Gopinath }; 670b6b58229SThara Gopinath 671b6b58229SThara Gopinath static struct omap_hwmod_addr_space omap2430_timer6_addrs[] = { 672b6b58229SThara Gopinath { 673b6b58229SThara Gopinath .pa_start = 0x4807e000, 674b6b58229SThara Gopinath .pa_end = 0x4807e000 + SZ_1K - 1, 675b6b58229SThara Gopinath .flags = ADDR_TYPE_RT 676b6b58229SThara Gopinath }, 677b6b58229SThara Gopinath }; 678b6b58229SThara Gopinath 679b6b58229SThara Gopinath /* l4_core -> timer6 */ 680b6b58229SThara Gopinath static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = { 681b6b58229SThara Gopinath .master = &omap2430_l4_core_hwmod, 682b6b58229SThara Gopinath .slave = &omap2430_timer6_hwmod, 683b6b58229SThara Gopinath .clk = "gpt6_ick", 684b6b58229SThara Gopinath .addr = omap2430_timer6_addrs, 685b6b58229SThara Gopinath .addr_cnt = ARRAY_SIZE(omap2430_timer6_addrs), 686b6b58229SThara Gopinath .user = OCP_USER_MPU | OCP_USER_SDMA, 687b6b58229SThara Gopinath }; 688b6b58229SThara Gopinath 689b6b58229SThara Gopinath /* timer6 slave port */ 690b6b58229SThara Gopinath static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = { 691b6b58229SThara Gopinath &omap2430_l4_core__timer6, 692b6b58229SThara Gopinath }; 693b6b58229SThara Gopinath 694b6b58229SThara Gopinath /* timer6 hwmod */ 695b6b58229SThara Gopinath static struct omap_hwmod omap2430_timer6_hwmod = { 696b6b58229SThara Gopinath .name = "timer6", 697b6b58229SThara Gopinath .mpu_irqs = omap2430_timer6_mpu_irqs, 698b6b58229SThara Gopinath .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer6_mpu_irqs), 699b6b58229SThara Gopinath .main_clk = "gpt6_fck", 700b6b58229SThara Gopinath .prcm = { 701b6b58229SThara Gopinath .omap2 = { 702b6b58229SThara Gopinath .prcm_reg_id = 1, 703b6b58229SThara Gopinath .module_bit = OMAP24XX_EN_GPT6_SHIFT, 704b6b58229SThara Gopinath .module_offs = CORE_MOD, 705b6b58229SThara Gopinath .idlest_reg_id = 1, 706b6b58229SThara Gopinath .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, 707b6b58229SThara Gopinath }, 708b6b58229SThara Gopinath }, 709b6b58229SThara Gopinath .slaves = omap2430_timer6_slaves, 710b6b58229SThara Gopinath .slaves_cnt = ARRAY_SIZE(omap2430_timer6_slaves), 711b6b58229SThara Gopinath .class = &omap2430_timer_hwmod_class, 712b6b58229SThara Gopinath .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 713b6b58229SThara Gopinath }; 714b6b58229SThara Gopinath 715b6b58229SThara Gopinath /* timer7 */ 716b6b58229SThara Gopinath static struct omap_hwmod omap2430_timer7_hwmod; 717b6b58229SThara Gopinath static struct omap_hwmod_irq_info omap2430_timer7_mpu_irqs[] = { 718b6b58229SThara Gopinath { .irq = 43, }, 719b6b58229SThara Gopinath }; 720b6b58229SThara Gopinath 721b6b58229SThara Gopinath static struct omap_hwmod_addr_space omap2430_timer7_addrs[] = { 722b6b58229SThara Gopinath { 723b6b58229SThara Gopinath .pa_start = 0x48080000, 724b6b58229SThara Gopinath .pa_end = 0x48080000 + SZ_1K - 1, 725b6b58229SThara Gopinath .flags = ADDR_TYPE_RT 726b6b58229SThara Gopinath }, 727b6b58229SThara Gopinath }; 728b6b58229SThara Gopinath 729b6b58229SThara Gopinath /* l4_core -> timer7 */ 730b6b58229SThara Gopinath static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = { 731b6b58229SThara Gopinath .master = &omap2430_l4_core_hwmod, 732b6b58229SThara Gopinath .slave = &omap2430_timer7_hwmod, 733b6b58229SThara Gopinath .clk = "gpt7_ick", 734b6b58229SThara Gopinath .addr = omap2430_timer7_addrs, 735b6b58229SThara Gopinath .addr_cnt = ARRAY_SIZE(omap2430_timer7_addrs), 736b6b58229SThara Gopinath .user = OCP_USER_MPU | OCP_USER_SDMA, 737b6b58229SThara Gopinath }; 738b6b58229SThara Gopinath 739b6b58229SThara Gopinath /* timer7 slave port */ 740b6b58229SThara Gopinath static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = { 741b6b58229SThara Gopinath &omap2430_l4_core__timer7, 742b6b58229SThara Gopinath }; 743b6b58229SThara Gopinath 744b6b58229SThara Gopinath /* timer7 hwmod */ 745b6b58229SThara Gopinath static struct omap_hwmod omap2430_timer7_hwmod = { 746b6b58229SThara Gopinath .name = "timer7", 747b6b58229SThara Gopinath .mpu_irqs = omap2430_timer7_mpu_irqs, 748b6b58229SThara Gopinath .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer7_mpu_irqs), 749b6b58229SThara Gopinath .main_clk = "gpt7_fck", 750b6b58229SThara Gopinath .prcm = { 751b6b58229SThara Gopinath .omap2 = { 752b6b58229SThara Gopinath .prcm_reg_id = 1, 753b6b58229SThara Gopinath .module_bit = OMAP24XX_EN_GPT7_SHIFT, 754b6b58229SThara Gopinath .module_offs = CORE_MOD, 755b6b58229SThara Gopinath .idlest_reg_id = 1, 756b6b58229SThara Gopinath .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, 757b6b58229SThara Gopinath }, 758b6b58229SThara Gopinath }, 759b6b58229SThara Gopinath .slaves = omap2430_timer7_slaves, 760b6b58229SThara Gopinath .slaves_cnt = ARRAY_SIZE(omap2430_timer7_slaves), 761b6b58229SThara Gopinath .class = &omap2430_timer_hwmod_class, 762b6b58229SThara Gopinath .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 763b6b58229SThara Gopinath }; 764b6b58229SThara Gopinath 765b6b58229SThara Gopinath /* timer8 */ 766b6b58229SThara Gopinath static struct omap_hwmod omap2430_timer8_hwmod; 767b6b58229SThara Gopinath static struct omap_hwmod_irq_info omap2430_timer8_mpu_irqs[] = { 768b6b58229SThara Gopinath { .irq = 44, }, 769b6b58229SThara Gopinath }; 770b6b58229SThara Gopinath 771b6b58229SThara Gopinath static struct omap_hwmod_addr_space omap2430_timer8_addrs[] = { 772b6b58229SThara Gopinath { 773b6b58229SThara Gopinath .pa_start = 0x48082000, 774b6b58229SThara Gopinath .pa_end = 0x48082000 + SZ_1K - 1, 775b6b58229SThara Gopinath .flags = ADDR_TYPE_RT 776b6b58229SThara Gopinath }, 777b6b58229SThara Gopinath }; 778b6b58229SThara Gopinath 779b6b58229SThara Gopinath /* l4_core -> timer8 */ 780b6b58229SThara Gopinath static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = { 781b6b58229SThara Gopinath .master = &omap2430_l4_core_hwmod, 782b6b58229SThara Gopinath .slave = &omap2430_timer8_hwmod, 783b6b58229SThara Gopinath .clk = "gpt8_ick", 784b6b58229SThara Gopinath .addr = omap2430_timer8_addrs, 785b6b58229SThara Gopinath .addr_cnt = ARRAY_SIZE(omap2430_timer8_addrs), 786b6b58229SThara Gopinath .user = OCP_USER_MPU | OCP_USER_SDMA, 787b6b58229SThara Gopinath }; 788b6b58229SThara Gopinath 789b6b58229SThara Gopinath /* timer8 slave port */ 790b6b58229SThara Gopinath static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = { 791b6b58229SThara Gopinath &omap2430_l4_core__timer8, 792b6b58229SThara Gopinath }; 793b6b58229SThara Gopinath 794b6b58229SThara Gopinath /* timer8 hwmod */ 795b6b58229SThara Gopinath static struct omap_hwmod omap2430_timer8_hwmod = { 796b6b58229SThara Gopinath .name = "timer8", 797b6b58229SThara Gopinath .mpu_irqs = omap2430_timer8_mpu_irqs, 798b6b58229SThara Gopinath .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer8_mpu_irqs), 799b6b58229SThara Gopinath .main_clk = "gpt8_fck", 800b6b58229SThara Gopinath .prcm = { 801b6b58229SThara Gopinath .omap2 = { 802b6b58229SThara Gopinath .prcm_reg_id = 1, 803b6b58229SThara Gopinath .module_bit = OMAP24XX_EN_GPT8_SHIFT, 804b6b58229SThara Gopinath .module_offs = CORE_MOD, 805b6b58229SThara Gopinath .idlest_reg_id = 1, 806b6b58229SThara Gopinath .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, 807b6b58229SThara Gopinath }, 808b6b58229SThara Gopinath }, 809b6b58229SThara Gopinath .slaves = omap2430_timer8_slaves, 810b6b58229SThara Gopinath .slaves_cnt = ARRAY_SIZE(omap2430_timer8_slaves), 811b6b58229SThara Gopinath .class = &omap2430_timer_hwmod_class, 812b6b58229SThara Gopinath .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 813b6b58229SThara Gopinath }; 814b6b58229SThara Gopinath 815b6b58229SThara Gopinath /* timer9 */ 816b6b58229SThara Gopinath static struct omap_hwmod omap2430_timer9_hwmod; 817b6b58229SThara Gopinath static struct omap_hwmod_irq_info omap2430_timer9_mpu_irqs[] = { 818b6b58229SThara Gopinath { .irq = 45, }, 819b6b58229SThara Gopinath }; 820b6b58229SThara Gopinath 821b6b58229SThara Gopinath static struct omap_hwmod_addr_space omap2430_timer9_addrs[] = { 822b6b58229SThara Gopinath { 823b6b58229SThara Gopinath .pa_start = 0x48084000, 824b6b58229SThara Gopinath .pa_end = 0x48084000 + SZ_1K - 1, 825b6b58229SThara Gopinath .flags = ADDR_TYPE_RT 826b6b58229SThara Gopinath }, 827b6b58229SThara Gopinath }; 828b6b58229SThara Gopinath 829b6b58229SThara Gopinath /* l4_core -> timer9 */ 830b6b58229SThara Gopinath static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = { 831b6b58229SThara Gopinath .master = &omap2430_l4_core_hwmod, 832b6b58229SThara Gopinath .slave = &omap2430_timer9_hwmod, 833b6b58229SThara Gopinath .clk = "gpt9_ick", 834b6b58229SThara Gopinath .addr = omap2430_timer9_addrs, 835b6b58229SThara Gopinath .addr_cnt = ARRAY_SIZE(omap2430_timer9_addrs), 836b6b58229SThara Gopinath .user = OCP_USER_MPU | OCP_USER_SDMA, 837b6b58229SThara Gopinath }; 838b6b58229SThara Gopinath 839b6b58229SThara Gopinath /* timer9 slave port */ 840b6b58229SThara Gopinath static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = { 841b6b58229SThara Gopinath &omap2430_l4_core__timer9, 842b6b58229SThara Gopinath }; 843b6b58229SThara Gopinath 844b6b58229SThara Gopinath /* timer9 hwmod */ 845b6b58229SThara Gopinath static struct omap_hwmod omap2430_timer9_hwmod = { 846b6b58229SThara Gopinath .name = "timer9", 847b6b58229SThara Gopinath .mpu_irqs = omap2430_timer9_mpu_irqs, 848b6b58229SThara Gopinath .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer9_mpu_irqs), 849b6b58229SThara Gopinath .main_clk = "gpt9_fck", 850b6b58229SThara Gopinath .prcm = { 851b6b58229SThara Gopinath .omap2 = { 852b6b58229SThara Gopinath .prcm_reg_id = 1, 853b6b58229SThara Gopinath .module_bit = OMAP24XX_EN_GPT9_SHIFT, 854b6b58229SThara Gopinath .module_offs = CORE_MOD, 855b6b58229SThara Gopinath .idlest_reg_id = 1, 856b6b58229SThara Gopinath .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, 857b6b58229SThara Gopinath }, 858b6b58229SThara Gopinath }, 859b6b58229SThara Gopinath .slaves = omap2430_timer9_slaves, 860b6b58229SThara Gopinath .slaves_cnt = ARRAY_SIZE(omap2430_timer9_slaves), 861b6b58229SThara Gopinath .class = &omap2430_timer_hwmod_class, 862b6b58229SThara Gopinath .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 863b6b58229SThara Gopinath }; 864b6b58229SThara Gopinath 865b6b58229SThara Gopinath /* timer10 */ 866b6b58229SThara Gopinath static struct omap_hwmod omap2430_timer10_hwmod; 867b6b58229SThara Gopinath static struct omap_hwmod_irq_info omap2430_timer10_mpu_irqs[] = { 868b6b58229SThara Gopinath { .irq = 46, }, 869b6b58229SThara Gopinath }; 870b6b58229SThara Gopinath 871b6b58229SThara Gopinath static struct omap_hwmod_addr_space omap2430_timer10_addrs[] = { 872b6b58229SThara Gopinath { 873b6b58229SThara Gopinath .pa_start = 0x48086000, 874b6b58229SThara Gopinath .pa_end = 0x48086000 + SZ_1K - 1, 875b6b58229SThara Gopinath .flags = ADDR_TYPE_RT 876b6b58229SThara Gopinath }, 877b6b58229SThara Gopinath }; 878b6b58229SThara Gopinath 879b6b58229SThara Gopinath /* l4_core -> timer10 */ 880b6b58229SThara Gopinath static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = { 881b6b58229SThara Gopinath .master = &omap2430_l4_core_hwmod, 882b6b58229SThara Gopinath .slave = &omap2430_timer10_hwmod, 883b6b58229SThara Gopinath .clk = "gpt10_ick", 884b6b58229SThara Gopinath .addr = omap2430_timer10_addrs, 885b6b58229SThara Gopinath .addr_cnt = ARRAY_SIZE(omap2430_timer10_addrs), 886b6b58229SThara Gopinath .user = OCP_USER_MPU | OCP_USER_SDMA, 887b6b58229SThara Gopinath }; 888b6b58229SThara Gopinath 889b6b58229SThara Gopinath /* timer10 slave port */ 890b6b58229SThara Gopinath static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = { 891b6b58229SThara Gopinath &omap2430_l4_core__timer10, 892b6b58229SThara Gopinath }; 893b6b58229SThara Gopinath 894b6b58229SThara Gopinath /* timer10 hwmod */ 895b6b58229SThara Gopinath static struct omap_hwmod omap2430_timer10_hwmod = { 896b6b58229SThara Gopinath .name = "timer10", 897b6b58229SThara Gopinath .mpu_irqs = omap2430_timer10_mpu_irqs, 898b6b58229SThara Gopinath .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer10_mpu_irqs), 899b6b58229SThara Gopinath .main_clk = "gpt10_fck", 900b6b58229SThara Gopinath .prcm = { 901b6b58229SThara Gopinath .omap2 = { 902b6b58229SThara Gopinath .prcm_reg_id = 1, 903b6b58229SThara Gopinath .module_bit = OMAP24XX_EN_GPT10_SHIFT, 904b6b58229SThara Gopinath .module_offs = CORE_MOD, 905b6b58229SThara Gopinath .idlest_reg_id = 1, 906b6b58229SThara Gopinath .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, 907b6b58229SThara Gopinath }, 908b6b58229SThara Gopinath }, 909b6b58229SThara Gopinath .slaves = omap2430_timer10_slaves, 910b6b58229SThara Gopinath .slaves_cnt = ARRAY_SIZE(omap2430_timer10_slaves), 911b6b58229SThara Gopinath .class = &omap2430_timer_hwmod_class, 912b6b58229SThara Gopinath .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 913b6b58229SThara Gopinath }; 914b6b58229SThara Gopinath 915b6b58229SThara Gopinath /* timer11 */ 916b6b58229SThara Gopinath static struct omap_hwmod omap2430_timer11_hwmod; 917b6b58229SThara Gopinath static struct omap_hwmod_irq_info omap2430_timer11_mpu_irqs[] = { 918b6b58229SThara Gopinath { .irq = 47, }, 919b6b58229SThara Gopinath }; 920b6b58229SThara Gopinath 921b6b58229SThara Gopinath static struct omap_hwmod_addr_space omap2430_timer11_addrs[] = { 922b6b58229SThara Gopinath { 923b6b58229SThara Gopinath .pa_start = 0x48088000, 924b6b58229SThara Gopinath .pa_end = 0x48088000 + SZ_1K - 1, 925b6b58229SThara Gopinath .flags = ADDR_TYPE_RT 926b6b58229SThara Gopinath }, 927b6b58229SThara Gopinath }; 928b6b58229SThara Gopinath 929b6b58229SThara Gopinath /* l4_core -> timer11 */ 930b6b58229SThara Gopinath static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = { 931b6b58229SThara Gopinath .master = &omap2430_l4_core_hwmod, 932b6b58229SThara Gopinath .slave = &omap2430_timer11_hwmod, 933b6b58229SThara Gopinath .clk = "gpt11_ick", 934b6b58229SThara Gopinath .addr = omap2430_timer11_addrs, 935b6b58229SThara Gopinath .addr_cnt = ARRAY_SIZE(omap2430_timer11_addrs), 936b6b58229SThara Gopinath .user = OCP_USER_MPU | OCP_USER_SDMA, 937b6b58229SThara Gopinath }; 938b6b58229SThara Gopinath 939b6b58229SThara Gopinath /* timer11 slave port */ 940b6b58229SThara Gopinath static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = { 941b6b58229SThara Gopinath &omap2430_l4_core__timer11, 942b6b58229SThara Gopinath }; 943b6b58229SThara Gopinath 944b6b58229SThara Gopinath /* timer11 hwmod */ 945b6b58229SThara Gopinath static struct omap_hwmod omap2430_timer11_hwmod = { 946b6b58229SThara Gopinath .name = "timer11", 947b6b58229SThara Gopinath .mpu_irqs = omap2430_timer11_mpu_irqs, 948b6b58229SThara Gopinath .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer11_mpu_irqs), 949b6b58229SThara Gopinath .main_clk = "gpt11_fck", 950b6b58229SThara Gopinath .prcm = { 951b6b58229SThara Gopinath .omap2 = { 952b6b58229SThara Gopinath .prcm_reg_id = 1, 953b6b58229SThara Gopinath .module_bit = OMAP24XX_EN_GPT11_SHIFT, 954b6b58229SThara Gopinath .module_offs = CORE_MOD, 955b6b58229SThara Gopinath .idlest_reg_id = 1, 956b6b58229SThara Gopinath .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, 957b6b58229SThara Gopinath }, 958b6b58229SThara Gopinath }, 959b6b58229SThara Gopinath .slaves = omap2430_timer11_slaves, 960b6b58229SThara Gopinath .slaves_cnt = ARRAY_SIZE(omap2430_timer11_slaves), 961b6b58229SThara Gopinath .class = &omap2430_timer_hwmod_class, 962b6b58229SThara Gopinath .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 963b6b58229SThara Gopinath }; 964b6b58229SThara Gopinath 965b6b58229SThara Gopinath /* timer12 */ 966b6b58229SThara Gopinath static struct omap_hwmod omap2430_timer12_hwmod; 967b6b58229SThara Gopinath static struct omap_hwmod_irq_info omap2430_timer12_mpu_irqs[] = { 968b6b58229SThara Gopinath { .irq = 48, }, 969b6b58229SThara Gopinath }; 970b6b58229SThara Gopinath 971b6b58229SThara Gopinath static struct omap_hwmod_addr_space omap2430_timer12_addrs[] = { 972b6b58229SThara Gopinath { 973b6b58229SThara Gopinath .pa_start = 0x4808a000, 974b6b58229SThara Gopinath .pa_end = 0x4808a000 + SZ_1K - 1, 975b6b58229SThara Gopinath .flags = ADDR_TYPE_RT 976b6b58229SThara Gopinath }, 977b6b58229SThara Gopinath }; 978b6b58229SThara Gopinath 979b6b58229SThara Gopinath /* l4_core -> timer12 */ 980b6b58229SThara Gopinath static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = { 981b6b58229SThara Gopinath .master = &omap2430_l4_core_hwmod, 982b6b58229SThara Gopinath .slave = &omap2430_timer12_hwmod, 983b6b58229SThara Gopinath .clk = "gpt12_ick", 984b6b58229SThara Gopinath .addr = omap2430_timer12_addrs, 985b6b58229SThara Gopinath .addr_cnt = ARRAY_SIZE(omap2430_timer12_addrs), 986b6b58229SThara Gopinath .user = OCP_USER_MPU | OCP_USER_SDMA, 987b6b58229SThara Gopinath }; 988b6b58229SThara Gopinath 989b6b58229SThara Gopinath /* timer12 slave port */ 990b6b58229SThara Gopinath static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = { 991b6b58229SThara Gopinath &omap2430_l4_core__timer12, 992b6b58229SThara Gopinath }; 993b6b58229SThara Gopinath 994b6b58229SThara Gopinath /* timer12 hwmod */ 995b6b58229SThara Gopinath static struct omap_hwmod omap2430_timer12_hwmod = { 996b6b58229SThara Gopinath .name = "timer12", 997b6b58229SThara Gopinath .mpu_irqs = omap2430_timer12_mpu_irqs, 998b6b58229SThara Gopinath .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer12_mpu_irqs), 999b6b58229SThara Gopinath .main_clk = "gpt12_fck", 1000b6b58229SThara Gopinath .prcm = { 1001b6b58229SThara Gopinath .omap2 = { 1002b6b58229SThara Gopinath .prcm_reg_id = 1, 1003b6b58229SThara Gopinath .module_bit = OMAP24XX_EN_GPT12_SHIFT, 1004b6b58229SThara Gopinath .module_offs = CORE_MOD, 1005b6b58229SThara Gopinath .idlest_reg_id = 1, 1006b6b58229SThara Gopinath .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, 1007b6b58229SThara Gopinath }, 1008b6b58229SThara Gopinath }, 1009b6b58229SThara Gopinath .slaves = omap2430_timer12_slaves, 1010b6b58229SThara Gopinath .slaves_cnt = ARRAY_SIZE(omap2430_timer12_slaves), 1011b6b58229SThara Gopinath .class = &omap2430_timer_hwmod_class, 1012b6b58229SThara Gopinath .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 1013b6b58229SThara Gopinath }; 1014b6b58229SThara Gopinath 1015165e2161SVaradarajan, Charulatha /* l4_wkup -> wd_timer2 */ 1016165e2161SVaradarajan, Charulatha static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { 1017165e2161SVaradarajan, Charulatha { 1018165e2161SVaradarajan, Charulatha .pa_start = 0x49016000, 1019165e2161SVaradarajan, Charulatha .pa_end = 0x4901607f, 1020165e2161SVaradarajan, Charulatha .flags = ADDR_TYPE_RT 1021165e2161SVaradarajan, Charulatha }, 1022165e2161SVaradarajan, Charulatha }; 1023165e2161SVaradarajan, Charulatha 1024165e2161SVaradarajan, Charulatha static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { 1025165e2161SVaradarajan, Charulatha .master = &omap2430_l4_wkup_hwmod, 1026165e2161SVaradarajan, Charulatha .slave = &omap2430_wd_timer2_hwmod, 1027165e2161SVaradarajan, Charulatha .clk = "mpu_wdt_ick", 1028165e2161SVaradarajan, Charulatha .addr = omap2430_wd_timer2_addrs, 1029165e2161SVaradarajan, Charulatha .addr_cnt = ARRAY_SIZE(omap2430_wd_timer2_addrs), 1030165e2161SVaradarajan, Charulatha .user = OCP_USER_MPU | OCP_USER_SDMA, 1031165e2161SVaradarajan, Charulatha }; 1032165e2161SVaradarajan, Charulatha 1033165e2161SVaradarajan, Charulatha /* 1034165e2161SVaradarajan, Charulatha * 'wd_timer' class 1035165e2161SVaradarajan, Charulatha * 32-bit watchdog upward counter that generates a pulse on the reset pin on 1036165e2161SVaradarajan, Charulatha * overflow condition 1037165e2161SVaradarajan, Charulatha */ 1038165e2161SVaradarajan, Charulatha 1039165e2161SVaradarajan, Charulatha static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = { 1040165e2161SVaradarajan, Charulatha .rev_offs = 0x0, 1041165e2161SVaradarajan, Charulatha .sysc_offs = 0x0010, 1042165e2161SVaradarajan, Charulatha .syss_offs = 0x0014, 1043165e2161SVaradarajan, Charulatha .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | 1044165e2161SVaradarajan, Charulatha SYSC_HAS_AUTOIDLE), 1045165e2161SVaradarajan, Charulatha .sysc_fields = &omap_hwmod_sysc_type1, 1046165e2161SVaradarajan, Charulatha }; 1047165e2161SVaradarajan, Charulatha 1048165e2161SVaradarajan, Charulatha static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = { 1049165e2161SVaradarajan, Charulatha .name = "wd_timer", 1050165e2161SVaradarajan, Charulatha .sysc = &omap2430_wd_timer_sysc, 1051ff2516fbSPaul Walmsley .pre_shutdown = &omap2_wd_timer_disable 1052165e2161SVaradarajan, Charulatha }; 1053165e2161SVaradarajan, Charulatha 1054165e2161SVaradarajan, Charulatha /* wd_timer2 */ 1055165e2161SVaradarajan, Charulatha static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = { 1056165e2161SVaradarajan, Charulatha &omap2430_l4_wkup__wd_timer2, 1057165e2161SVaradarajan, Charulatha }; 1058165e2161SVaradarajan, Charulatha 1059165e2161SVaradarajan, Charulatha static struct omap_hwmod omap2430_wd_timer2_hwmod = { 1060165e2161SVaradarajan, Charulatha .name = "wd_timer2", 1061165e2161SVaradarajan, Charulatha .class = &omap2430_wd_timer_hwmod_class, 1062165e2161SVaradarajan, Charulatha .main_clk = "mpu_wdt_fck", 1063165e2161SVaradarajan, Charulatha .prcm = { 1064165e2161SVaradarajan, Charulatha .omap2 = { 1065165e2161SVaradarajan, Charulatha .prcm_reg_id = 1, 1066165e2161SVaradarajan, Charulatha .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, 1067165e2161SVaradarajan, Charulatha .module_offs = WKUP_MOD, 1068165e2161SVaradarajan, Charulatha .idlest_reg_id = 1, 1069165e2161SVaradarajan, Charulatha .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, 1070165e2161SVaradarajan, Charulatha }, 1071165e2161SVaradarajan, Charulatha }, 1072165e2161SVaradarajan, Charulatha .slaves = omap2430_wd_timer2_slaves, 1073165e2161SVaradarajan, Charulatha .slaves_cnt = ARRAY_SIZE(omap2430_wd_timer2_slaves), 1074165e2161SVaradarajan, Charulatha .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1075165e2161SVaradarajan, Charulatha }; 1076165e2161SVaradarajan, Charulatha 1077046465b7SKevin Hilman /* UART */ 1078046465b7SKevin Hilman 1079046465b7SKevin Hilman static struct omap_hwmod_class_sysconfig uart_sysc = { 1080046465b7SKevin Hilman .rev_offs = 0x50, 1081046465b7SKevin Hilman .sysc_offs = 0x54, 1082046465b7SKevin Hilman .syss_offs = 0x58, 1083046465b7SKevin Hilman .sysc_flags = (SYSC_HAS_SIDLEMODE | 1084046465b7SKevin Hilman SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 1085046465b7SKevin Hilman SYSC_HAS_AUTOIDLE), 1086046465b7SKevin Hilman .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1087046465b7SKevin Hilman .sysc_fields = &omap_hwmod_sysc_type1, 1088046465b7SKevin Hilman }; 1089046465b7SKevin Hilman 1090046465b7SKevin Hilman static struct omap_hwmod_class uart_class = { 1091046465b7SKevin Hilman .name = "uart", 1092046465b7SKevin Hilman .sysc = &uart_sysc, 1093046465b7SKevin Hilman }; 1094046465b7SKevin Hilman 1095046465b7SKevin Hilman /* UART1 */ 1096046465b7SKevin Hilman 1097046465b7SKevin Hilman static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { 1098046465b7SKevin Hilman { .irq = INT_24XX_UART1_IRQ, }, 1099046465b7SKevin Hilman }; 1100046465b7SKevin Hilman 1101046465b7SKevin Hilman static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { 1102046465b7SKevin Hilman { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, 1103046465b7SKevin Hilman { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, 1104046465b7SKevin Hilman }; 1105046465b7SKevin Hilman 1106046465b7SKevin Hilman static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = { 1107046465b7SKevin Hilman &omap2_l4_core__uart1, 1108046465b7SKevin Hilman }; 1109046465b7SKevin Hilman 1110046465b7SKevin Hilman static struct omap_hwmod omap2430_uart1_hwmod = { 1111046465b7SKevin Hilman .name = "uart1", 1112046465b7SKevin Hilman .mpu_irqs = uart1_mpu_irqs, 1113046465b7SKevin Hilman .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), 1114046465b7SKevin Hilman .sdma_reqs = uart1_sdma_reqs, 1115046465b7SKevin Hilman .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), 1116046465b7SKevin Hilman .main_clk = "uart1_fck", 1117046465b7SKevin Hilman .prcm = { 1118046465b7SKevin Hilman .omap2 = { 1119046465b7SKevin Hilman .module_offs = CORE_MOD, 1120046465b7SKevin Hilman .prcm_reg_id = 1, 1121046465b7SKevin Hilman .module_bit = OMAP24XX_EN_UART1_SHIFT, 1122046465b7SKevin Hilman .idlest_reg_id = 1, 1123046465b7SKevin Hilman .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, 1124046465b7SKevin Hilman }, 1125046465b7SKevin Hilman }, 1126046465b7SKevin Hilman .slaves = omap2430_uart1_slaves, 1127046465b7SKevin Hilman .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves), 1128046465b7SKevin Hilman .class = &uart_class, 1129046465b7SKevin Hilman .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1130046465b7SKevin Hilman }; 1131046465b7SKevin Hilman 1132046465b7SKevin Hilman /* UART2 */ 1133046465b7SKevin Hilman 1134046465b7SKevin Hilman static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { 1135046465b7SKevin Hilman { .irq = INT_24XX_UART2_IRQ, }, 1136046465b7SKevin Hilman }; 1137046465b7SKevin Hilman 1138046465b7SKevin Hilman static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { 1139046465b7SKevin Hilman { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, 1140046465b7SKevin Hilman { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, 1141046465b7SKevin Hilman }; 1142046465b7SKevin Hilman 1143046465b7SKevin Hilman static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = { 1144046465b7SKevin Hilman &omap2_l4_core__uart2, 1145046465b7SKevin Hilman }; 1146046465b7SKevin Hilman 1147046465b7SKevin Hilman static struct omap_hwmod omap2430_uart2_hwmod = { 1148046465b7SKevin Hilman .name = "uart2", 1149046465b7SKevin Hilman .mpu_irqs = uart2_mpu_irqs, 1150046465b7SKevin Hilman .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), 1151046465b7SKevin Hilman .sdma_reqs = uart2_sdma_reqs, 1152046465b7SKevin Hilman .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), 1153046465b7SKevin Hilman .main_clk = "uart2_fck", 1154046465b7SKevin Hilman .prcm = { 1155046465b7SKevin Hilman .omap2 = { 1156046465b7SKevin Hilman .module_offs = CORE_MOD, 1157046465b7SKevin Hilman .prcm_reg_id = 1, 1158046465b7SKevin Hilman .module_bit = OMAP24XX_EN_UART2_SHIFT, 1159046465b7SKevin Hilman .idlest_reg_id = 1, 1160046465b7SKevin Hilman .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, 1161046465b7SKevin Hilman }, 1162046465b7SKevin Hilman }, 1163046465b7SKevin Hilman .slaves = omap2430_uart2_slaves, 1164046465b7SKevin Hilman .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves), 1165046465b7SKevin Hilman .class = &uart_class, 1166046465b7SKevin Hilman .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1167046465b7SKevin Hilman }; 1168046465b7SKevin Hilman 1169046465b7SKevin Hilman /* UART3 */ 1170046465b7SKevin Hilman 1171046465b7SKevin Hilman static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { 1172046465b7SKevin Hilman { .irq = INT_24XX_UART3_IRQ, }, 1173046465b7SKevin Hilman }; 1174046465b7SKevin Hilman 1175046465b7SKevin Hilman static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { 1176046465b7SKevin Hilman { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, 1177046465b7SKevin Hilman { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, 1178046465b7SKevin Hilman }; 1179046465b7SKevin Hilman 1180046465b7SKevin Hilman static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = { 1181046465b7SKevin Hilman &omap2_l4_core__uart3, 1182046465b7SKevin Hilman }; 1183046465b7SKevin Hilman 1184046465b7SKevin Hilman static struct omap_hwmod omap2430_uart3_hwmod = { 1185046465b7SKevin Hilman .name = "uart3", 1186046465b7SKevin Hilman .mpu_irqs = uart3_mpu_irqs, 1187046465b7SKevin Hilman .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), 1188046465b7SKevin Hilman .sdma_reqs = uart3_sdma_reqs, 1189046465b7SKevin Hilman .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), 1190046465b7SKevin Hilman .main_clk = "uart3_fck", 1191046465b7SKevin Hilman .prcm = { 1192046465b7SKevin Hilman .omap2 = { 1193046465b7SKevin Hilman .module_offs = CORE_MOD, 1194046465b7SKevin Hilman .prcm_reg_id = 2, 1195046465b7SKevin Hilman .module_bit = OMAP24XX_EN_UART3_SHIFT, 1196046465b7SKevin Hilman .idlest_reg_id = 2, 1197046465b7SKevin Hilman .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, 1198046465b7SKevin Hilman }, 1199046465b7SKevin Hilman }, 1200046465b7SKevin Hilman .slaves = omap2430_uart3_slaves, 1201046465b7SKevin Hilman .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves), 1202046465b7SKevin Hilman .class = &uart_class, 1203046465b7SKevin Hilman .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1204046465b7SKevin Hilman }; 1205046465b7SKevin Hilman 1206de56dbb6SSenthilvadivu Guruswamy /* 1207de56dbb6SSenthilvadivu Guruswamy * 'dss' class 1208de56dbb6SSenthilvadivu Guruswamy * display sub-system 1209de56dbb6SSenthilvadivu Guruswamy */ 1210de56dbb6SSenthilvadivu Guruswamy 1211de56dbb6SSenthilvadivu Guruswamy static struct omap_hwmod_class_sysconfig omap2430_dss_sysc = { 1212de56dbb6SSenthilvadivu Guruswamy .rev_offs = 0x0000, 1213de56dbb6SSenthilvadivu Guruswamy .sysc_offs = 0x0010, 1214de56dbb6SSenthilvadivu Guruswamy .syss_offs = 0x0014, 1215de56dbb6SSenthilvadivu Guruswamy .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), 1216de56dbb6SSenthilvadivu Guruswamy .sysc_fields = &omap_hwmod_sysc_type1, 1217de56dbb6SSenthilvadivu Guruswamy }; 1218de56dbb6SSenthilvadivu Guruswamy 1219de56dbb6SSenthilvadivu Guruswamy static struct omap_hwmod_class omap2430_dss_hwmod_class = { 1220de56dbb6SSenthilvadivu Guruswamy .name = "dss", 1221de56dbb6SSenthilvadivu Guruswamy .sysc = &omap2430_dss_sysc, 1222de56dbb6SSenthilvadivu Guruswamy }; 1223de56dbb6SSenthilvadivu Guruswamy 1224de56dbb6SSenthilvadivu Guruswamy /* dss */ 1225de56dbb6SSenthilvadivu Guruswamy static struct omap_hwmod_irq_info omap2430_dss_irqs[] = { 1226de56dbb6SSenthilvadivu Guruswamy { .irq = 25 }, 1227de56dbb6SSenthilvadivu Guruswamy }; 1228de56dbb6SSenthilvadivu Guruswamy static struct omap_hwmod_dma_info omap2430_dss_sdma_chs[] = { 1229de56dbb6SSenthilvadivu Guruswamy { .name = "dispc", .dma_req = 5 }, 1230de56dbb6SSenthilvadivu Guruswamy }; 1231de56dbb6SSenthilvadivu Guruswamy 1232de56dbb6SSenthilvadivu Guruswamy /* dss */ 1233de56dbb6SSenthilvadivu Guruswamy /* dss master ports */ 1234de56dbb6SSenthilvadivu Guruswamy static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = { 1235de56dbb6SSenthilvadivu Guruswamy &omap2430_dss__l3, 1236de56dbb6SSenthilvadivu Guruswamy }; 1237de56dbb6SSenthilvadivu Guruswamy 1238de56dbb6SSenthilvadivu Guruswamy static struct omap_hwmod_addr_space omap2430_dss_addrs[] = { 1239de56dbb6SSenthilvadivu Guruswamy { 1240de56dbb6SSenthilvadivu Guruswamy .pa_start = 0x48050000, 1241de56dbb6SSenthilvadivu Guruswamy .pa_end = 0x480503FF, 1242de56dbb6SSenthilvadivu Guruswamy .flags = ADDR_TYPE_RT 1243de56dbb6SSenthilvadivu Guruswamy }, 1244de56dbb6SSenthilvadivu Guruswamy }; 1245de56dbb6SSenthilvadivu Guruswamy 1246de56dbb6SSenthilvadivu Guruswamy /* l4_core -> dss */ 1247de56dbb6SSenthilvadivu Guruswamy static struct omap_hwmod_ocp_if omap2430_l4_core__dss = { 1248de56dbb6SSenthilvadivu Guruswamy .master = &omap2430_l4_core_hwmod, 1249de56dbb6SSenthilvadivu Guruswamy .slave = &omap2430_dss_core_hwmod, 1250de56dbb6SSenthilvadivu Guruswamy .clk = "dss_ick", 1251de56dbb6SSenthilvadivu Guruswamy .addr = omap2430_dss_addrs, 1252de56dbb6SSenthilvadivu Guruswamy .addr_cnt = ARRAY_SIZE(omap2430_dss_addrs), 1253de56dbb6SSenthilvadivu Guruswamy .user = OCP_USER_MPU | OCP_USER_SDMA, 1254de56dbb6SSenthilvadivu Guruswamy }; 1255de56dbb6SSenthilvadivu Guruswamy 1256de56dbb6SSenthilvadivu Guruswamy /* dss slave ports */ 1257de56dbb6SSenthilvadivu Guruswamy static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = { 1258de56dbb6SSenthilvadivu Guruswamy &omap2430_l4_core__dss, 1259de56dbb6SSenthilvadivu Guruswamy }; 1260de56dbb6SSenthilvadivu Guruswamy 1261de56dbb6SSenthilvadivu Guruswamy static struct omap_hwmod_opt_clk dss_opt_clks[] = { 1262de56dbb6SSenthilvadivu Guruswamy { .role = "tv_clk", .clk = "dss_54m_fck" }, 1263de56dbb6SSenthilvadivu Guruswamy { .role = "sys_clk", .clk = "dss2_fck" }, 1264de56dbb6SSenthilvadivu Guruswamy }; 1265de56dbb6SSenthilvadivu Guruswamy 1266de56dbb6SSenthilvadivu Guruswamy static struct omap_hwmod omap2430_dss_core_hwmod = { 1267de56dbb6SSenthilvadivu Guruswamy .name = "dss_core", 1268de56dbb6SSenthilvadivu Guruswamy .class = &omap2430_dss_hwmod_class, 1269de56dbb6SSenthilvadivu Guruswamy .main_clk = "dss1_fck", /* instead of dss_fck */ 1270de56dbb6SSenthilvadivu Guruswamy .mpu_irqs = omap2430_dss_irqs, 1271de56dbb6SSenthilvadivu Guruswamy .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dss_irqs), 1272de56dbb6SSenthilvadivu Guruswamy .sdma_reqs = omap2430_dss_sdma_chs, 1273de56dbb6SSenthilvadivu Guruswamy .sdma_reqs_cnt = ARRAY_SIZE(omap2430_dss_sdma_chs), 1274de56dbb6SSenthilvadivu Guruswamy .prcm = { 1275de56dbb6SSenthilvadivu Guruswamy .omap2 = { 1276de56dbb6SSenthilvadivu Guruswamy .prcm_reg_id = 1, 1277de56dbb6SSenthilvadivu Guruswamy .module_bit = OMAP24XX_EN_DSS1_SHIFT, 1278de56dbb6SSenthilvadivu Guruswamy .module_offs = CORE_MOD, 1279de56dbb6SSenthilvadivu Guruswamy .idlest_reg_id = 1, 1280de56dbb6SSenthilvadivu Guruswamy .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, 1281de56dbb6SSenthilvadivu Guruswamy }, 1282de56dbb6SSenthilvadivu Guruswamy }, 1283de56dbb6SSenthilvadivu Guruswamy .opt_clks = dss_opt_clks, 1284de56dbb6SSenthilvadivu Guruswamy .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), 1285de56dbb6SSenthilvadivu Guruswamy .slaves = omap2430_dss_slaves, 1286de56dbb6SSenthilvadivu Guruswamy .slaves_cnt = ARRAY_SIZE(omap2430_dss_slaves), 1287de56dbb6SSenthilvadivu Guruswamy .masters = omap2430_dss_masters, 1288de56dbb6SSenthilvadivu Guruswamy .masters_cnt = ARRAY_SIZE(omap2430_dss_masters), 1289de56dbb6SSenthilvadivu Guruswamy .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1290de56dbb6SSenthilvadivu Guruswamy .flags = HWMOD_NO_IDLEST, 1291de56dbb6SSenthilvadivu Guruswamy }; 1292de56dbb6SSenthilvadivu Guruswamy 1293de56dbb6SSenthilvadivu Guruswamy /* 1294de56dbb6SSenthilvadivu Guruswamy * 'dispc' class 1295de56dbb6SSenthilvadivu Guruswamy * display controller 1296de56dbb6SSenthilvadivu Guruswamy */ 1297de56dbb6SSenthilvadivu Guruswamy 1298de56dbb6SSenthilvadivu Guruswamy static struct omap_hwmod_class_sysconfig omap2430_dispc_sysc = { 1299de56dbb6SSenthilvadivu Guruswamy .rev_offs = 0x0000, 1300de56dbb6SSenthilvadivu Guruswamy .sysc_offs = 0x0010, 1301de56dbb6SSenthilvadivu Guruswamy .syss_offs = 0x0014, 1302de56dbb6SSenthilvadivu Guruswamy .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | 1303de56dbb6SSenthilvadivu Guruswamy SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), 1304de56dbb6SSenthilvadivu Guruswamy .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 1305de56dbb6SSenthilvadivu Guruswamy MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 1306de56dbb6SSenthilvadivu Guruswamy .sysc_fields = &omap_hwmod_sysc_type1, 1307de56dbb6SSenthilvadivu Guruswamy }; 1308de56dbb6SSenthilvadivu Guruswamy 1309de56dbb6SSenthilvadivu Guruswamy static struct omap_hwmod_class omap2430_dispc_hwmod_class = { 1310de56dbb6SSenthilvadivu Guruswamy .name = "dispc", 1311de56dbb6SSenthilvadivu Guruswamy .sysc = &omap2430_dispc_sysc, 1312de56dbb6SSenthilvadivu Guruswamy }; 1313de56dbb6SSenthilvadivu Guruswamy 1314de56dbb6SSenthilvadivu Guruswamy static struct omap_hwmod_addr_space omap2430_dss_dispc_addrs[] = { 1315de56dbb6SSenthilvadivu Guruswamy { 1316de56dbb6SSenthilvadivu Guruswamy .pa_start = 0x48050400, 1317de56dbb6SSenthilvadivu Guruswamy .pa_end = 0x480507FF, 1318de56dbb6SSenthilvadivu Guruswamy .flags = ADDR_TYPE_RT 1319de56dbb6SSenthilvadivu Guruswamy }, 1320de56dbb6SSenthilvadivu Guruswamy }; 1321de56dbb6SSenthilvadivu Guruswamy 1322de56dbb6SSenthilvadivu Guruswamy /* l4_core -> dss_dispc */ 1323de56dbb6SSenthilvadivu Guruswamy static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = { 1324de56dbb6SSenthilvadivu Guruswamy .master = &omap2430_l4_core_hwmod, 1325de56dbb6SSenthilvadivu Guruswamy .slave = &omap2430_dss_dispc_hwmod, 1326de56dbb6SSenthilvadivu Guruswamy .clk = "dss_ick", 1327de56dbb6SSenthilvadivu Guruswamy .addr = omap2430_dss_dispc_addrs, 1328de56dbb6SSenthilvadivu Guruswamy .addr_cnt = ARRAY_SIZE(omap2430_dss_dispc_addrs), 1329de56dbb6SSenthilvadivu Guruswamy .user = OCP_USER_MPU | OCP_USER_SDMA, 1330de56dbb6SSenthilvadivu Guruswamy }; 1331de56dbb6SSenthilvadivu Guruswamy 1332de56dbb6SSenthilvadivu Guruswamy /* dss_dispc slave ports */ 1333de56dbb6SSenthilvadivu Guruswamy static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = { 1334de56dbb6SSenthilvadivu Guruswamy &omap2430_l4_core__dss_dispc, 1335de56dbb6SSenthilvadivu Guruswamy }; 1336de56dbb6SSenthilvadivu Guruswamy 1337de56dbb6SSenthilvadivu Guruswamy static struct omap_hwmod omap2430_dss_dispc_hwmod = { 1338de56dbb6SSenthilvadivu Guruswamy .name = "dss_dispc", 1339de56dbb6SSenthilvadivu Guruswamy .class = &omap2430_dispc_hwmod_class, 1340de56dbb6SSenthilvadivu Guruswamy .main_clk = "dss1_fck", 1341de56dbb6SSenthilvadivu Guruswamy .prcm = { 1342de56dbb6SSenthilvadivu Guruswamy .omap2 = { 1343de56dbb6SSenthilvadivu Guruswamy .prcm_reg_id = 1, 1344de56dbb6SSenthilvadivu Guruswamy .module_bit = OMAP24XX_EN_DSS1_SHIFT, 1345de56dbb6SSenthilvadivu Guruswamy .module_offs = CORE_MOD, 1346de56dbb6SSenthilvadivu Guruswamy .idlest_reg_id = 1, 1347de56dbb6SSenthilvadivu Guruswamy .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, 1348de56dbb6SSenthilvadivu Guruswamy }, 1349de56dbb6SSenthilvadivu Guruswamy }, 1350de56dbb6SSenthilvadivu Guruswamy .slaves = omap2430_dss_dispc_slaves, 1351de56dbb6SSenthilvadivu Guruswamy .slaves_cnt = ARRAY_SIZE(omap2430_dss_dispc_slaves), 1352de56dbb6SSenthilvadivu Guruswamy .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1353de56dbb6SSenthilvadivu Guruswamy .flags = HWMOD_NO_IDLEST, 1354de56dbb6SSenthilvadivu Guruswamy }; 1355de56dbb6SSenthilvadivu Guruswamy 1356de56dbb6SSenthilvadivu Guruswamy /* 1357de56dbb6SSenthilvadivu Guruswamy * 'rfbi' class 1358de56dbb6SSenthilvadivu Guruswamy * remote frame buffer interface 1359de56dbb6SSenthilvadivu Guruswamy */ 1360de56dbb6SSenthilvadivu Guruswamy 1361de56dbb6SSenthilvadivu Guruswamy static struct omap_hwmod_class_sysconfig omap2430_rfbi_sysc = { 1362de56dbb6SSenthilvadivu Guruswamy .rev_offs = 0x0000, 1363de56dbb6SSenthilvadivu Guruswamy .sysc_offs = 0x0010, 1364de56dbb6SSenthilvadivu Guruswamy .syss_offs = 0x0014, 1365de56dbb6SSenthilvadivu Guruswamy .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 1366de56dbb6SSenthilvadivu Guruswamy SYSC_HAS_AUTOIDLE), 1367de56dbb6SSenthilvadivu Guruswamy .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1368de56dbb6SSenthilvadivu Guruswamy .sysc_fields = &omap_hwmod_sysc_type1, 1369de56dbb6SSenthilvadivu Guruswamy }; 1370de56dbb6SSenthilvadivu Guruswamy 1371de56dbb6SSenthilvadivu Guruswamy static struct omap_hwmod_class omap2430_rfbi_hwmod_class = { 1372de56dbb6SSenthilvadivu Guruswamy .name = "rfbi", 1373de56dbb6SSenthilvadivu Guruswamy .sysc = &omap2430_rfbi_sysc, 1374de56dbb6SSenthilvadivu Guruswamy }; 1375de56dbb6SSenthilvadivu Guruswamy 1376de56dbb6SSenthilvadivu Guruswamy static struct omap_hwmod_addr_space omap2430_dss_rfbi_addrs[] = { 1377de56dbb6SSenthilvadivu Guruswamy { 1378de56dbb6SSenthilvadivu Guruswamy .pa_start = 0x48050800, 1379de56dbb6SSenthilvadivu Guruswamy .pa_end = 0x48050BFF, 1380de56dbb6SSenthilvadivu Guruswamy .flags = ADDR_TYPE_RT 1381de56dbb6SSenthilvadivu Guruswamy }, 1382de56dbb6SSenthilvadivu Guruswamy }; 1383de56dbb6SSenthilvadivu Guruswamy 1384de56dbb6SSenthilvadivu Guruswamy /* l4_core -> dss_rfbi */ 1385de56dbb6SSenthilvadivu Guruswamy static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = { 1386de56dbb6SSenthilvadivu Guruswamy .master = &omap2430_l4_core_hwmod, 1387de56dbb6SSenthilvadivu Guruswamy .slave = &omap2430_dss_rfbi_hwmod, 1388de56dbb6SSenthilvadivu Guruswamy .clk = "dss_ick", 1389de56dbb6SSenthilvadivu Guruswamy .addr = omap2430_dss_rfbi_addrs, 1390de56dbb6SSenthilvadivu Guruswamy .addr_cnt = ARRAY_SIZE(omap2430_dss_rfbi_addrs), 1391de56dbb6SSenthilvadivu Guruswamy .user = OCP_USER_MPU | OCP_USER_SDMA, 1392de56dbb6SSenthilvadivu Guruswamy }; 1393de56dbb6SSenthilvadivu Guruswamy 1394de56dbb6SSenthilvadivu Guruswamy /* dss_rfbi slave ports */ 1395de56dbb6SSenthilvadivu Guruswamy static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = { 1396de56dbb6SSenthilvadivu Guruswamy &omap2430_l4_core__dss_rfbi, 1397de56dbb6SSenthilvadivu Guruswamy }; 1398de56dbb6SSenthilvadivu Guruswamy 1399de56dbb6SSenthilvadivu Guruswamy static struct omap_hwmod omap2430_dss_rfbi_hwmod = { 1400de56dbb6SSenthilvadivu Guruswamy .name = "dss_rfbi", 1401de56dbb6SSenthilvadivu Guruswamy .class = &omap2430_rfbi_hwmod_class, 1402de56dbb6SSenthilvadivu Guruswamy .main_clk = "dss1_fck", 1403de56dbb6SSenthilvadivu Guruswamy .prcm = { 1404de56dbb6SSenthilvadivu Guruswamy .omap2 = { 1405de56dbb6SSenthilvadivu Guruswamy .prcm_reg_id = 1, 1406de56dbb6SSenthilvadivu Guruswamy .module_bit = OMAP24XX_EN_DSS1_SHIFT, 1407de56dbb6SSenthilvadivu Guruswamy .module_offs = CORE_MOD, 1408de56dbb6SSenthilvadivu Guruswamy }, 1409de56dbb6SSenthilvadivu Guruswamy }, 1410de56dbb6SSenthilvadivu Guruswamy .slaves = omap2430_dss_rfbi_slaves, 1411de56dbb6SSenthilvadivu Guruswamy .slaves_cnt = ARRAY_SIZE(omap2430_dss_rfbi_slaves), 1412de56dbb6SSenthilvadivu Guruswamy .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1413de56dbb6SSenthilvadivu Guruswamy .flags = HWMOD_NO_IDLEST, 1414de56dbb6SSenthilvadivu Guruswamy }; 1415de56dbb6SSenthilvadivu Guruswamy 1416de56dbb6SSenthilvadivu Guruswamy /* 1417de56dbb6SSenthilvadivu Guruswamy * 'venc' class 1418de56dbb6SSenthilvadivu Guruswamy * video encoder 1419de56dbb6SSenthilvadivu Guruswamy */ 1420de56dbb6SSenthilvadivu Guruswamy 1421de56dbb6SSenthilvadivu Guruswamy static struct omap_hwmod_class omap2430_venc_hwmod_class = { 1422de56dbb6SSenthilvadivu Guruswamy .name = "venc", 1423de56dbb6SSenthilvadivu Guruswamy }; 1424de56dbb6SSenthilvadivu Guruswamy 1425de56dbb6SSenthilvadivu Guruswamy /* dss_venc */ 1426de56dbb6SSenthilvadivu Guruswamy static struct omap_hwmod_addr_space omap2430_dss_venc_addrs[] = { 1427de56dbb6SSenthilvadivu Guruswamy { 1428de56dbb6SSenthilvadivu Guruswamy .pa_start = 0x48050C00, 1429de56dbb6SSenthilvadivu Guruswamy .pa_end = 0x48050FFF, 1430de56dbb6SSenthilvadivu Guruswamy .flags = ADDR_TYPE_RT 1431de56dbb6SSenthilvadivu Guruswamy }, 1432de56dbb6SSenthilvadivu Guruswamy }; 1433de56dbb6SSenthilvadivu Guruswamy 1434de56dbb6SSenthilvadivu Guruswamy /* l4_core -> dss_venc */ 1435de56dbb6SSenthilvadivu Guruswamy static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = { 1436de56dbb6SSenthilvadivu Guruswamy .master = &omap2430_l4_core_hwmod, 1437de56dbb6SSenthilvadivu Guruswamy .slave = &omap2430_dss_venc_hwmod, 1438de56dbb6SSenthilvadivu Guruswamy .clk = "dss_54m_fck", 1439de56dbb6SSenthilvadivu Guruswamy .addr = omap2430_dss_venc_addrs, 1440de56dbb6SSenthilvadivu Guruswamy .addr_cnt = ARRAY_SIZE(omap2430_dss_venc_addrs), 1441de56dbb6SSenthilvadivu Guruswamy .user = OCP_USER_MPU | OCP_USER_SDMA, 1442de56dbb6SSenthilvadivu Guruswamy }; 1443de56dbb6SSenthilvadivu Guruswamy 1444de56dbb6SSenthilvadivu Guruswamy /* dss_venc slave ports */ 1445de56dbb6SSenthilvadivu Guruswamy static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = { 1446de56dbb6SSenthilvadivu Guruswamy &omap2430_l4_core__dss_venc, 1447de56dbb6SSenthilvadivu Guruswamy }; 1448de56dbb6SSenthilvadivu Guruswamy 1449de56dbb6SSenthilvadivu Guruswamy static struct omap_hwmod omap2430_dss_venc_hwmod = { 1450de56dbb6SSenthilvadivu Guruswamy .name = "dss_venc", 1451de56dbb6SSenthilvadivu Guruswamy .class = &omap2430_venc_hwmod_class, 1452de56dbb6SSenthilvadivu Guruswamy .main_clk = "dss1_fck", 1453de56dbb6SSenthilvadivu Guruswamy .prcm = { 1454de56dbb6SSenthilvadivu Guruswamy .omap2 = { 1455de56dbb6SSenthilvadivu Guruswamy .prcm_reg_id = 1, 1456de56dbb6SSenthilvadivu Guruswamy .module_bit = OMAP24XX_EN_DSS1_SHIFT, 1457de56dbb6SSenthilvadivu Guruswamy .module_offs = CORE_MOD, 1458de56dbb6SSenthilvadivu Guruswamy }, 1459de56dbb6SSenthilvadivu Guruswamy }, 1460de56dbb6SSenthilvadivu Guruswamy .slaves = omap2430_dss_venc_slaves, 1461de56dbb6SSenthilvadivu Guruswamy .slaves_cnt = ARRAY_SIZE(omap2430_dss_venc_slaves), 1462de56dbb6SSenthilvadivu Guruswamy .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1463de56dbb6SSenthilvadivu Guruswamy .flags = HWMOD_NO_IDLEST, 1464de56dbb6SSenthilvadivu Guruswamy }; 1465de56dbb6SSenthilvadivu Guruswamy 14662004290fSPaul Walmsley /* I2C common */ 14672004290fSPaul Walmsley static struct omap_hwmod_class_sysconfig i2c_sysc = { 14682004290fSPaul Walmsley .rev_offs = 0x00, 14692004290fSPaul Walmsley .sysc_offs = 0x20, 14702004290fSPaul Walmsley .syss_offs = 0x10, 14712004290fSPaul Walmsley .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), 14722004290fSPaul Walmsley .sysc_fields = &omap_hwmod_sysc_type1, 14732004290fSPaul Walmsley }; 14742004290fSPaul Walmsley 14752004290fSPaul Walmsley static struct omap_hwmod_class i2c_class = { 14762004290fSPaul Walmsley .name = "i2c", 14772004290fSPaul Walmsley .sysc = &i2c_sysc, 14782004290fSPaul Walmsley }; 14792004290fSPaul Walmsley 148050ebb777SBenoit Cousson static struct omap_i2c_dev_attr i2c_dev_attr = { 14812004290fSPaul Walmsley .fifo_depth = 8, /* bytes */ 14822004290fSPaul Walmsley }; 14832004290fSPaul Walmsley 148450ebb777SBenoit Cousson /* I2C1 */ 148550ebb777SBenoit Cousson 14862004290fSPaul Walmsley static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { 14872004290fSPaul Walmsley { .irq = INT_24XX_I2C1_IRQ, }, 14882004290fSPaul Walmsley }; 14892004290fSPaul Walmsley 14902004290fSPaul Walmsley static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = { 14912004290fSPaul Walmsley { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX }, 14922004290fSPaul Walmsley { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX }, 14932004290fSPaul Walmsley }; 14942004290fSPaul Walmsley 14952004290fSPaul Walmsley static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = { 14962004290fSPaul Walmsley &omap2430_l4_core__i2c1, 14972004290fSPaul Walmsley }; 14982004290fSPaul Walmsley 14992004290fSPaul Walmsley static struct omap_hwmod omap2430_i2c1_hwmod = { 15002004290fSPaul Walmsley .name = "i2c1", 15012004290fSPaul Walmsley .mpu_irqs = i2c1_mpu_irqs, 15022004290fSPaul Walmsley .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), 15032004290fSPaul Walmsley .sdma_reqs = i2c1_sdma_reqs, 15042004290fSPaul Walmsley .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs), 15052004290fSPaul Walmsley .main_clk = "i2chs1_fck", 15062004290fSPaul Walmsley .prcm = { 15072004290fSPaul Walmsley .omap2 = { 15082004290fSPaul Walmsley /* 15092004290fSPaul Walmsley * NOTE: The CM_FCLKEN* and CM_ICLKEN* for 15102004290fSPaul Walmsley * I2CHS IP's do not follow the usual pattern. 15112004290fSPaul Walmsley * prcm_reg_id alone cannot be used to program 15122004290fSPaul Walmsley * the iclk and fclk. Needs to be handled using 15132004290fSPaul Walmsley * additonal flags when clk handling is moved 15142004290fSPaul Walmsley * to hwmod framework. 15152004290fSPaul Walmsley */ 15162004290fSPaul Walmsley .module_offs = CORE_MOD, 15172004290fSPaul Walmsley .prcm_reg_id = 1, 15182004290fSPaul Walmsley .module_bit = OMAP2430_EN_I2CHS1_SHIFT, 15192004290fSPaul Walmsley .idlest_reg_id = 1, 15202004290fSPaul Walmsley .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT, 15212004290fSPaul Walmsley }, 15222004290fSPaul Walmsley }, 15232004290fSPaul Walmsley .slaves = omap2430_i2c1_slaves, 15242004290fSPaul Walmsley .slaves_cnt = ARRAY_SIZE(omap2430_i2c1_slaves), 15252004290fSPaul Walmsley .class = &i2c_class, 152650ebb777SBenoit Cousson .dev_attr = &i2c_dev_attr, 15272004290fSPaul Walmsley .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 15282004290fSPaul Walmsley }; 15292004290fSPaul Walmsley 15302004290fSPaul Walmsley /* I2C2 */ 15312004290fSPaul Walmsley 15322004290fSPaul Walmsley static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { 15332004290fSPaul Walmsley { .irq = INT_24XX_I2C2_IRQ, }, 15342004290fSPaul Walmsley }; 15352004290fSPaul Walmsley 15362004290fSPaul Walmsley static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = { 15372004290fSPaul Walmsley { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX }, 15382004290fSPaul Walmsley { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX }, 15392004290fSPaul Walmsley }; 15402004290fSPaul Walmsley 15412004290fSPaul Walmsley static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = { 15422004290fSPaul Walmsley &omap2430_l4_core__i2c2, 15432004290fSPaul Walmsley }; 15442004290fSPaul Walmsley 15452004290fSPaul Walmsley static struct omap_hwmod omap2430_i2c2_hwmod = { 15462004290fSPaul Walmsley .name = "i2c2", 15472004290fSPaul Walmsley .mpu_irqs = i2c2_mpu_irqs, 15482004290fSPaul Walmsley .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), 15492004290fSPaul Walmsley .sdma_reqs = i2c2_sdma_reqs, 15502004290fSPaul Walmsley .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs), 15512004290fSPaul Walmsley .main_clk = "i2chs2_fck", 15522004290fSPaul Walmsley .prcm = { 15532004290fSPaul Walmsley .omap2 = { 15542004290fSPaul Walmsley .module_offs = CORE_MOD, 15552004290fSPaul Walmsley .prcm_reg_id = 1, 15562004290fSPaul Walmsley .module_bit = OMAP2430_EN_I2CHS2_SHIFT, 15572004290fSPaul Walmsley .idlest_reg_id = 1, 15582004290fSPaul Walmsley .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT, 15592004290fSPaul Walmsley }, 15602004290fSPaul Walmsley }, 15612004290fSPaul Walmsley .slaves = omap2430_i2c2_slaves, 15622004290fSPaul Walmsley .slaves_cnt = ARRAY_SIZE(omap2430_i2c2_slaves), 15632004290fSPaul Walmsley .class = &i2c_class, 156450ebb777SBenoit Cousson .dev_attr = &i2c_dev_attr, 15652004290fSPaul Walmsley .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 15662004290fSPaul Walmsley }; 15672004290fSPaul Walmsley 1568aeac0e44SVaradarajan, Charulatha /* l4_wkup -> gpio1 */ 1569aeac0e44SVaradarajan, Charulatha static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = { 1570aeac0e44SVaradarajan, Charulatha { 1571aeac0e44SVaradarajan, Charulatha .pa_start = 0x4900C000, 1572aeac0e44SVaradarajan, Charulatha .pa_end = 0x4900C1ff, 1573aeac0e44SVaradarajan, Charulatha .flags = ADDR_TYPE_RT 1574aeac0e44SVaradarajan, Charulatha }, 1575aeac0e44SVaradarajan, Charulatha }; 1576aeac0e44SVaradarajan, Charulatha 1577aeac0e44SVaradarajan, Charulatha static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { 1578aeac0e44SVaradarajan, Charulatha .master = &omap2430_l4_wkup_hwmod, 1579aeac0e44SVaradarajan, Charulatha .slave = &omap2430_gpio1_hwmod, 1580aeac0e44SVaradarajan, Charulatha .clk = "gpios_ick", 1581aeac0e44SVaradarajan, Charulatha .addr = omap2430_gpio1_addr_space, 1582aeac0e44SVaradarajan, Charulatha .addr_cnt = ARRAY_SIZE(omap2430_gpio1_addr_space), 1583aeac0e44SVaradarajan, Charulatha .user = OCP_USER_MPU | OCP_USER_SDMA, 1584aeac0e44SVaradarajan, Charulatha }; 1585aeac0e44SVaradarajan, Charulatha 1586aeac0e44SVaradarajan, Charulatha /* l4_wkup -> gpio2 */ 1587aeac0e44SVaradarajan, Charulatha static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = { 1588aeac0e44SVaradarajan, Charulatha { 1589aeac0e44SVaradarajan, Charulatha .pa_start = 0x4900E000, 1590aeac0e44SVaradarajan, Charulatha .pa_end = 0x4900E1ff, 1591aeac0e44SVaradarajan, Charulatha .flags = ADDR_TYPE_RT 1592aeac0e44SVaradarajan, Charulatha }, 1593aeac0e44SVaradarajan, Charulatha }; 1594aeac0e44SVaradarajan, Charulatha 1595aeac0e44SVaradarajan, Charulatha static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { 1596aeac0e44SVaradarajan, Charulatha .master = &omap2430_l4_wkup_hwmod, 1597aeac0e44SVaradarajan, Charulatha .slave = &omap2430_gpio2_hwmod, 1598aeac0e44SVaradarajan, Charulatha .clk = "gpios_ick", 1599aeac0e44SVaradarajan, Charulatha .addr = omap2430_gpio2_addr_space, 1600aeac0e44SVaradarajan, Charulatha .addr_cnt = ARRAY_SIZE(omap2430_gpio2_addr_space), 1601aeac0e44SVaradarajan, Charulatha .user = OCP_USER_MPU | OCP_USER_SDMA, 1602aeac0e44SVaradarajan, Charulatha }; 1603aeac0e44SVaradarajan, Charulatha 1604aeac0e44SVaradarajan, Charulatha /* l4_wkup -> gpio3 */ 1605aeac0e44SVaradarajan, Charulatha static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = { 1606aeac0e44SVaradarajan, Charulatha { 1607aeac0e44SVaradarajan, Charulatha .pa_start = 0x49010000, 1608aeac0e44SVaradarajan, Charulatha .pa_end = 0x490101ff, 1609aeac0e44SVaradarajan, Charulatha .flags = ADDR_TYPE_RT 1610aeac0e44SVaradarajan, Charulatha }, 1611aeac0e44SVaradarajan, Charulatha }; 1612aeac0e44SVaradarajan, Charulatha 1613aeac0e44SVaradarajan, Charulatha static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { 1614aeac0e44SVaradarajan, Charulatha .master = &omap2430_l4_wkup_hwmod, 1615aeac0e44SVaradarajan, Charulatha .slave = &omap2430_gpio3_hwmod, 1616aeac0e44SVaradarajan, Charulatha .clk = "gpios_ick", 1617aeac0e44SVaradarajan, Charulatha .addr = omap2430_gpio3_addr_space, 1618aeac0e44SVaradarajan, Charulatha .addr_cnt = ARRAY_SIZE(omap2430_gpio3_addr_space), 1619aeac0e44SVaradarajan, Charulatha .user = OCP_USER_MPU | OCP_USER_SDMA, 1620aeac0e44SVaradarajan, Charulatha }; 1621aeac0e44SVaradarajan, Charulatha 1622aeac0e44SVaradarajan, Charulatha /* l4_wkup -> gpio4 */ 1623aeac0e44SVaradarajan, Charulatha static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = { 1624aeac0e44SVaradarajan, Charulatha { 1625aeac0e44SVaradarajan, Charulatha .pa_start = 0x49012000, 1626aeac0e44SVaradarajan, Charulatha .pa_end = 0x490121ff, 1627aeac0e44SVaradarajan, Charulatha .flags = ADDR_TYPE_RT 1628aeac0e44SVaradarajan, Charulatha }, 1629aeac0e44SVaradarajan, Charulatha }; 1630aeac0e44SVaradarajan, Charulatha 1631aeac0e44SVaradarajan, Charulatha static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { 1632aeac0e44SVaradarajan, Charulatha .master = &omap2430_l4_wkup_hwmod, 1633aeac0e44SVaradarajan, Charulatha .slave = &omap2430_gpio4_hwmod, 1634aeac0e44SVaradarajan, Charulatha .clk = "gpios_ick", 1635aeac0e44SVaradarajan, Charulatha .addr = omap2430_gpio4_addr_space, 1636aeac0e44SVaradarajan, Charulatha .addr_cnt = ARRAY_SIZE(omap2430_gpio4_addr_space), 1637aeac0e44SVaradarajan, Charulatha .user = OCP_USER_MPU | OCP_USER_SDMA, 1638aeac0e44SVaradarajan, Charulatha }; 1639aeac0e44SVaradarajan, Charulatha 1640aeac0e44SVaradarajan, Charulatha /* l4_core -> gpio5 */ 1641aeac0e44SVaradarajan, Charulatha static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = { 1642aeac0e44SVaradarajan, Charulatha { 1643aeac0e44SVaradarajan, Charulatha .pa_start = 0x480B6000, 1644aeac0e44SVaradarajan, Charulatha .pa_end = 0x480B61ff, 1645aeac0e44SVaradarajan, Charulatha .flags = ADDR_TYPE_RT 1646aeac0e44SVaradarajan, Charulatha }, 1647aeac0e44SVaradarajan, Charulatha }; 1648aeac0e44SVaradarajan, Charulatha 1649aeac0e44SVaradarajan, Charulatha static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { 1650aeac0e44SVaradarajan, Charulatha .master = &omap2430_l4_core_hwmod, 1651aeac0e44SVaradarajan, Charulatha .slave = &omap2430_gpio5_hwmod, 1652aeac0e44SVaradarajan, Charulatha .clk = "gpio5_ick", 1653aeac0e44SVaradarajan, Charulatha .addr = omap2430_gpio5_addr_space, 1654aeac0e44SVaradarajan, Charulatha .addr_cnt = ARRAY_SIZE(omap2430_gpio5_addr_space), 1655aeac0e44SVaradarajan, Charulatha .user = OCP_USER_MPU | OCP_USER_SDMA, 1656aeac0e44SVaradarajan, Charulatha }; 1657aeac0e44SVaradarajan, Charulatha 1658aeac0e44SVaradarajan, Charulatha /* gpio dev_attr */ 1659aeac0e44SVaradarajan, Charulatha static struct omap_gpio_dev_attr gpio_dev_attr = { 1660aeac0e44SVaradarajan, Charulatha .bank_width = 32, 1661aeac0e44SVaradarajan, Charulatha .dbck_flag = false, 1662aeac0e44SVaradarajan, Charulatha }; 1663aeac0e44SVaradarajan, Charulatha 1664aeac0e44SVaradarajan, Charulatha static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = { 1665aeac0e44SVaradarajan, Charulatha .rev_offs = 0x0000, 1666aeac0e44SVaradarajan, Charulatha .sysc_offs = 0x0010, 1667aeac0e44SVaradarajan, Charulatha .syss_offs = 0x0014, 1668aeac0e44SVaradarajan, Charulatha .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | 1669aeac0e44SVaradarajan, Charulatha SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), 1670aeac0e44SVaradarajan, Charulatha .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1671aeac0e44SVaradarajan, Charulatha .sysc_fields = &omap_hwmod_sysc_type1, 1672aeac0e44SVaradarajan, Charulatha }; 1673aeac0e44SVaradarajan, Charulatha 1674aeac0e44SVaradarajan, Charulatha /* 1675aeac0e44SVaradarajan, Charulatha * 'gpio' class 1676aeac0e44SVaradarajan, Charulatha * general purpose io module 1677aeac0e44SVaradarajan, Charulatha */ 1678aeac0e44SVaradarajan, Charulatha static struct omap_hwmod_class omap243x_gpio_hwmod_class = { 1679aeac0e44SVaradarajan, Charulatha .name = "gpio", 1680aeac0e44SVaradarajan, Charulatha .sysc = &omap243x_gpio_sysc, 1681aeac0e44SVaradarajan, Charulatha .rev = 0, 1682aeac0e44SVaradarajan, Charulatha }; 1683aeac0e44SVaradarajan, Charulatha 1684aeac0e44SVaradarajan, Charulatha /* gpio1 */ 1685aeac0e44SVaradarajan, Charulatha static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = { 1686aeac0e44SVaradarajan, Charulatha { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */ 1687aeac0e44SVaradarajan, Charulatha }; 1688aeac0e44SVaradarajan, Charulatha 1689aeac0e44SVaradarajan, Charulatha static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = { 1690aeac0e44SVaradarajan, Charulatha &omap2430_l4_wkup__gpio1, 1691aeac0e44SVaradarajan, Charulatha }; 1692aeac0e44SVaradarajan, Charulatha 1693aeac0e44SVaradarajan, Charulatha static struct omap_hwmod omap2430_gpio1_hwmod = { 1694aeac0e44SVaradarajan, Charulatha .name = "gpio1", 1695aeac0e44SVaradarajan, Charulatha .mpu_irqs = omap243x_gpio1_irqs, 1696aeac0e44SVaradarajan, Charulatha .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio1_irqs), 1697aeac0e44SVaradarajan, Charulatha .main_clk = "gpios_fck", 1698aeac0e44SVaradarajan, Charulatha .prcm = { 1699aeac0e44SVaradarajan, Charulatha .omap2 = { 1700aeac0e44SVaradarajan, Charulatha .prcm_reg_id = 1, 1701aeac0e44SVaradarajan, Charulatha .module_bit = OMAP24XX_EN_GPIOS_SHIFT, 1702aeac0e44SVaradarajan, Charulatha .module_offs = WKUP_MOD, 1703aeac0e44SVaradarajan, Charulatha .idlest_reg_id = 1, 1704aeac0e44SVaradarajan, Charulatha .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT, 1705aeac0e44SVaradarajan, Charulatha }, 1706aeac0e44SVaradarajan, Charulatha }, 1707aeac0e44SVaradarajan, Charulatha .slaves = omap2430_gpio1_slaves, 1708aeac0e44SVaradarajan, Charulatha .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves), 1709aeac0e44SVaradarajan, Charulatha .class = &omap243x_gpio_hwmod_class, 1710aeac0e44SVaradarajan, Charulatha .dev_attr = &gpio_dev_attr, 1711aeac0e44SVaradarajan, Charulatha .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1712aeac0e44SVaradarajan, Charulatha }; 1713aeac0e44SVaradarajan, Charulatha 1714aeac0e44SVaradarajan, Charulatha /* gpio2 */ 1715aeac0e44SVaradarajan, Charulatha static struct omap_hwmod_irq_info omap243x_gpio2_irqs[] = { 1716aeac0e44SVaradarajan, Charulatha { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */ 1717aeac0e44SVaradarajan, Charulatha }; 1718aeac0e44SVaradarajan, Charulatha 1719aeac0e44SVaradarajan, Charulatha static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = { 1720aeac0e44SVaradarajan, Charulatha &omap2430_l4_wkup__gpio2, 1721aeac0e44SVaradarajan, Charulatha }; 1722aeac0e44SVaradarajan, Charulatha 1723aeac0e44SVaradarajan, Charulatha static struct omap_hwmod omap2430_gpio2_hwmod = { 1724aeac0e44SVaradarajan, Charulatha .name = "gpio2", 1725aeac0e44SVaradarajan, Charulatha .mpu_irqs = omap243x_gpio2_irqs, 1726aeac0e44SVaradarajan, Charulatha .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio2_irqs), 1727aeac0e44SVaradarajan, Charulatha .main_clk = "gpios_fck", 1728aeac0e44SVaradarajan, Charulatha .prcm = { 1729aeac0e44SVaradarajan, Charulatha .omap2 = { 1730aeac0e44SVaradarajan, Charulatha .prcm_reg_id = 1, 1731aeac0e44SVaradarajan, Charulatha .module_bit = OMAP24XX_EN_GPIOS_SHIFT, 1732aeac0e44SVaradarajan, Charulatha .module_offs = WKUP_MOD, 1733aeac0e44SVaradarajan, Charulatha .idlest_reg_id = 1, 1734aeac0e44SVaradarajan, Charulatha .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, 1735aeac0e44SVaradarajan, Charulatha }, 1736aeac0e44SVaradarajan, Charulatha }, 1737aeac0e44SVaradarajan, Charulatha .slaves = omap2430_gpio2_slaves, 1738aeac0e44SVaradarajan, Charulatha .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves), 1739aeac0e44SVaradarajan, Charulatha .class = &omap243x_gpio_hwmod_class, 1740aeac0e44SVaradarajan, Charulatha .dev_attr = &gpio_dev_attr, 1741aeac0e44SVaradarajan, Charulatha .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1742aeac0e44SVaradarajan, Charulatha }; 1743aeac0e44SVaradarajan, Charulatha 1744aeac0e44SVaradarajan, Charulatha /* gpio3 */ 1745aeac0e44SVaradarajan, Charulatha static struct omap_hwmod_irq_info omap243x_gpio3_irqs[] = { 1746aeac0e44SVaradarajan, Charulatha { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */ 1747aeac0e44SVaradarajan, Charulatha }; 1748aeac0e44SVaradarajan, Charulatha 1749aeac0e44SVaradarajan, Charulatha static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = { 1750aeac0e44SVaradarajan, Charulatha &omap2430_l4_wkup__gpio3, 1751aeac0e44SVaradarajan, Charulatha }; 1752aeac0e44SVaradarajan, Charulatha 1753aeac0e44SVaradarajan, Charulatha static struct omap_hwmod omap2430_gpio3_hwmod = { 1754aeac0e44SVaradarajan, Charulatha .name = "gpio3", 1755aeac0e44SVaradarajan, Charulatha .mpu_irqs = omap243x_gpio3_irqs, 1756aeac0e44SVaradarajan, Charulatha .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio3_irqs), 1757aeac0e44SVaradarajan, Charulatha .main_clk = "gpios_fck", 1758aeac0e44SVaradarajan, Charulatha .prcm = { 1759aeac0e44SVaradarajan, Charulatha .omap2 = { 1760aeac0e44SVaradarajan, Charulatha .prcm_reg_id = 1, 1761aeac0e44SVaradarajan, Charulatha .module_bit = OMAP24XX_EN_GPIOS_SHIFT, 1762aeac0e44SVaradarajan, Charulatha .module_offs = WKUP_MOD, 1763aeac0e44SVaradarajan, Charulatha .idlest_reg_id = 1, 1764aeac0e44SVaradarajan, Charulatha .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, 1765aeac0e44SVaradarajan, Charulatha }, 1766aeac0e44SVaradarajan, Charulatha }, 1767aeac0e44SVaradarajan, Charulatha .slaves = omap2430_gpio3_slaves, 1768aeac0e44SVaradarajan, Charulatha .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves), 1769aeac0e44SVaradarajan, Charulatha .class = &omap243x_gpio_hwmod_class, 1770aeac0e44SVaradarajan, Charulatha .dev_attr = &gpio_dev_attr, 1771aeac0e44SVaradarajan, Charulatha .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1772aeac0e44SVaradarajan, Charulatha }; 1773aeac0e44SVaradarajan, Charulatha 1774aeac0e44SVaradarajan, Charulatha /* gpio4 */ 1775aeac0e44SVaradarajan, Charulatha static struct omap_hwmod_irq_info omap243x_gpio4_irqs[] = { 1776aeac0e44SVaradarajan, Charulatha { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */ 1777aeac0e44SVaradarajan, Charulatha }; 1778aeac0e44SVaradarajan, Charulatha 1779aeac0e44SVaradarajan, Charulatha static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = { 1780aeac0e44SVaradarajan, Charulatha &omap2430_l4_wkup__gpio4, 1781aeac0e44SVaradarajan, Charulatha }; 1782aeac0e44SVaradarajan, Charulatha 1783aeac0e44SVaradarajan, Charulatha static struct omap_hwmod omap2430_gpio4_hwmod = { 1784aeac0e44SVaradarajan, Charulatha .name = "gpio4", 1785aeac0e44SVaradarajan, Charulatha .mpu_irqs = omap243x_gpio4_irqs, 1786aeac0e44SVaradarajan, Charulatha .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio4_irqs), 1787aeac0e44SVaradarajan, Charulatha .main_clk = "gpios_fck", 1788aeac0e44SVaradarajan, Charulatha .prcm = { 1789aeac0e44SVaradarajan, Charulatha .omap2 = { 1790aeac0e44SVaradarajan, Charulatha .prcm_reg_id = 1, 1791aeac0e44SVaradarajan, Charulatha .module_bit = OMAP24XX_EN_GPIOS_SHIFT, 1792aeac0e44SVaradarajan, Charulatha .module_offs = WKUP_MOD, 1793aeac0e44SVaradarajan, Charulatha .idlest_reg_id = 1, 1794aeac0e44SVaradarajan, Charulatha .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, 1795aeac0e44SVaradarajan, Charulatha }, 1796aeac0e44SVaradarajan, Charulatha }, 1797aeac0e44SVaradarajan, Charulatha .slaves = omap2430_gpio4_slaves, 1798aeac0e44SVaradarajan, Charulatha .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves), 1799aeac0e44SVaradarajan, Charulatha .class = &omap243x_gpio_hwmod_class, 1800aeac0e44SVaradarajan, Charulatha .dev_attr = &gpio_dev_attr, 1801aeac0e44SVaradarajan, Charulatha .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1802aeac0e44SVaradarajan, Charulatha }; 1803aeac0e44SVaradarajan, Charulatha 1804aeac0e44SVaradarajan, Charulatha /* gpio5 */ 1805aeac0e44SVaradarajan, Charulatha static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { 1806aeac0e44SVaradarajan, Charulatha { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */ 1807aeac0e44SVaradarajan, Charulatha }; 1808aeac0e44SVaradarajan, Charulatha 1809aeac0e44SVaradarajan, Charulatha static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = { 1810aeac0e44SVaradarajan, Charulatha &omap2430_l4_core__gpio5, 1811aeac0e44SVaradarajan, Charulatha }; 1812aeac0e44SVaradarajan, Charulatha 1813aeac0e44SVaradarajan, Charulatha static struct omap_hwmod omap2430_gpio5_hwmod = { 1814aeac0e44SVaradarajan, Charulatha .name = "gpio5", 1815aeac0e44SVaradarajan, Charulatha .mpu_irqs = omap243x_gpio5_irqs, 1816aeac0e44SVaradarajan, Charulatha .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio5_irqs), 1817aeac0e44SVaradarajan, Charulatha .main_clk = "gpio5_fck", 1818aeac0e44SVaradarajan, Charulatha .prcm = { 1819aeac0e44SVaradarajan, Charulatha .omap2 = { 1820aeac0e44SVaradarajan, Charulatha .prcm_reg_id = 2, 1821aeac0e44SVaradarajan, Charulatha .module_bit = OMAP2430_EN_GPIO5_SHIFT, 1822aeac0e44SVaradarajan, Charulatha .module_offs = CORE_MOD, 1823aeac0e44SVaradarajan, Charulatha .idlest_reg_id = 2, 1824aeac0e44SVaradarajan, Charulatha .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT, 1825aeac0e44SVaradarajan, Charulatha }, 1826aeac0e44SVaradarajan, Charulatha }, 1827aeac0e44SVaradarajan, Charulatha .slaves = omap2430_gpio5_slaves, 1828aeac0e44SVaradarajan, Charulatha .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves), 1829aeac0e44SVaradarajan, Charulatha .class = &omap243x_gpio_hwmod_class, 1830aeac0e44SVaradarajan, Charulatha .dev_attr = &gpio_dev_attr, 1831aeac0e44SVaradarajan, Charulatha .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1832aeac0e44SVaradarajan, Charulatha }; 1833aeac0e44SVaradarajan, Charulatha 183482cbd1aeSG, Manjunath Kondaiah /* dma_system */ 183582cbd1aeSG, Manjunath Kondaiah static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = { 183682cbd1aeSG, Manjunath Kondaiah .rev_offs = 0x0000, 183782cbd1aeSG, Manjunath Kondaiah .sysc_offs = 0x002c, 183882cbd1aeSG, Manjunath Kondaiah .syss_offs = 0x0028, 183982cbd1aeSG, Manjunath Kondaiah .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE | 184082cbd1aeSG, Manjunath Kondaiah SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE | 184182cbd1aeSG, Manjunath Kondaiah SYSC_HAS_AUTOIDLE), 184282cbd1aeSG, Manjunath Kondaiah .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 184382cbd1aeSG, Manjunath Kondaiah .sysc_fields = &omap_hwmod_sysc_type1, 184482cbd1aeSG, Manjunath Kondaiah }; 184582cbd1aeSG, Manjunath Kondaiah 184682cbd1aeSG, Manjunath Kondaiah static struct omap_hwmod_class omap2430_dma_hwmod_class = { 184782cbd1aeSG, Manjunath Kondaiah .name = "dma", 184882cbd1aeSG, Manjunath Kondaiah .sysc = &omap2430_dma_sysc, 184982cbd1aeSG, Manjunath Kondaiah }; 185082cbd1aeSG, Manjunath Kondaiah 185182cbd1aeSG, Manjunath Kondaiah /* dma attributes */ 185282cbd1aeSG, Manjunath Kondaiah static struct omap_dma_dev_attr dma_dev_attr = { 185382cbd1aeSG, Manjunath Kondaiah .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | 185482cbd1aeSG, Manjunath Kondaiah IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, 185582cbd1aeSG, Manjunath Kondaiah .lch_count = 32, 185682cbd1aeSG, Manjunath Kondaiah }; 185782cbd1aeSG, Manjunath Kondaiah 185882cbd1aeSG, Manjunath Kondaiah static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = { 185982cbd1aeSG, Manjunath Kondaiah { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */ 186082cbd1aeSG, Manjunath Kondaiah { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */ 186182cbd1aeSG, Manjunath Kondaiah { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */ 186282cbd1aeSG, Manjunath Kondaiah { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */ 186382cbd1aeSG, Manjunath Kondaiah }; 186482cbd1aeSG, Manjunath Kondaiah 186582cbd1aeSG, Manjunath Kondaiah static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = { 186682cbd1aeSG, Manjunath Kondaiah { 186782cbd1aeSG, Manjunath Kondaiah .pa_start = 0x48056000, 186882cbd1aeSG, Manjunath Kondaiah .pa_end = 0x4a0560ff, 186982cbd1aeSG, Manjunath Kondaiah .flags = ADDR_TYPE_RT 187082cbd1aeSG, Manjunath Kondaiah }, 187182cbd1aeSG, Manjunath Kondaiah }; 187282cbd1aeSG, Manjunath Kondaiah 187382cbd1aeSG, Manjunath Kondaiah /* dma_system -> L3 */ 187482cbd1aeSG, Manjunath Kondaiah static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { 187582cbd1aeSG, Manjunath Kondaiah .master = &omap2430_dma_system_hwmod, 187682cbd1aeSG, Manjunath Kondaiah .slave = &omap2430_l3_main_hwmod, 187782cbd1aeSG, Manjunath Kondaiah .clk = "core_l3_ck", 187882cbd1aeSG, Manjunath Kondaiah .user = OCP_USER_MPU | OCP_USER_SDMA, 187982cbd1aeSG, Manjunath Kondaiah }; 188082cbd1aeSG, Manjunath Kondaiah 188182cbd1aeSG, Manjunath Kondaiah /* dma_system master ports */ 188282cbd1aeSG, Manjunath Kondaiah static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = { 188382cbd1aeSG, Manjunath Kondaiah &omap2430_dma_system__l3, 188482cbd1aeSG, Manjunath Kondaiah }; 188582cbd1aeSG, Manjunath Kondaiah 188682cbd1aeSG, Manjunath Kondaiah /* l4_core -> dma_system */ 188782cbd1aeSG, Manjunath Kondaiah static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { 188882cbd1aeSG, Manjunath Kondaiah .master = &omap2430_l4_core_hwmod, 188982cbd1aeSG, Manjunath Kondaiah .slave = &omap2430_dma_system_hwmod, 189082cbd1aeSG, Manjunath Kondaiah .clk = "sdma_ick", 189182cbd1aeSG, Manjunath Kondaiah .addr = omap2430_dma_system_addrs, 189282cbd1aeSG, Manjunath Kondaiah .addr_cnt = ARRAY_SIZE(omap2430_dma_system_addrs), 189382cbd1aeSG, Manjunath Kondaiah .user = OCP_USER_MPU | OCP_USER_SDMA, 189482cbd1aeSG, Manjunath Kondaiah }; 189582cbd1aeSG, Manjunath Kondaiah 189682cbd1aeSG, Manjunath Kondaiah /* dma_system slave ports */ 189782cbd1aeSG, Manjunath Kondaiah static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = { 189882cbd1aeSG, Manjunath Kondaiah &omap2430_l4_core__dma_system, 189982cbd1aeSG, Manjunath Kondaiah }; 190082cbd1aeSG, Manjunath Kondaiah 190182cbd1aeSG, Manjunath Kondaiah static struct omap_hwmod omap2430_dma_system_hwmod = { 190282cbd1aeSG, Manjunath Kondaiah .name = "dma", 190382cbd1aeSG, Manjunath Kondaiah .class = &omap2430_dma_hwmod_class, 190482cbd1aeSG, Manjunath Kondaiah .mpu_irqs = omap2430_dma_system_irqs, 190582cbd1aeSG, Manjunath Kondaiah .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dma_system_irqs), 190682cbd1aeSG, Manjunath Kondaiah .main_clk = "core_l3_ck", 190782cbd1aeSG, Manjunath Kondaiah .slaves = omap2430_dma_system_slaves, 190882cbd1aeSG, Manjunath Kondaiah .slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves), 190982cbd1aeSG, Manjunath Kondaiah .masters = omap2430_dma_system_masters, 191082cbd1aeSG, Manjunath Kondaiah .masters_cnt = ARRAY_SIZE(omap2430_dma_system_masters), 191182cbd1aeSG, Manjunath Kondaiah .dev_attr = &dma_dev_attr, 191282cbd1aeSG, Manjunath Kondaiah .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 191382cbd1aeSG, Manjunath Kondaiah .flags = HWMOD_NO_IDLEST, 191482cbd1aeSG, Manjunath Kondaiah }; 191582cbd1aeSG, Manjunath Kondaiah 19167f904c78SCharulatha V /* 19177f904c78SCharulatha V * 'mcspi' class 19187f904c78SCharulatha V * multichannel serial port interface (mcspi) / master/slave synchronous serial 19197f904c78SCharulatha V * bus 19207f904c78SCharulatha V */ 19217f904c78SCharulatha V 19227f904c78SCharulatha V static struct omap_hwmod_class_sysconfig omap2430_mcspi_sysc = { 19237f904c78SCharulatha V .rev_offs = 0x0000, 19247f904c78SCharulatha V .sysc_offs = 0x0010, 19257f904c78SCharulatha V .syss_offs = 0x0014, 19267f904c78SCharulatha V .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 19277f904c78SCharulatha V SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 19287f904c78SCharulatha V SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), 19297f904c78SCharulatha V .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 19307f904c78SCharulatha V .sysc_fields = &omap_hwmod_sysc_type1, 19317f904c78SCharulatha V }; 19327f904c78SCharulatha V 19337f904c78SCharulatha V static struct omap_hwmod_class omap2430_mcspi_class = { 19347f904c78SCharulatha V .name = "mcspi", 19357f904c78SCharulatha V .sysc = &omap2430_mcspi_sysc, 19367f904c78SCharulatha V .rev = OMAP2_MCSPI_REV, 19377f904c78SCharulatha V }; 19387f904c78SCharulatha V 19397f904c78SCharulatha V /* mcspi1 */ 19407f904c78SCharulatha V static struct omap_hwmod_irq_info omap2430_mcspi1_mpu_irqs[] = { 19417f904c78SCharulatha V { .irq = 65 }, 19427f904c78SCharulatha V }; 19437f904c78SCharulatha V 19447f904c78SCharulatha V static struct omap_hwmod_dma_info omap2430_mcspi1_sdma_reqs[] = { 19457f904c78SCharulatha V { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */ 19467f904c78SCharulatha V { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */ 19477f904c78SCharulatha V { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */ 19487f904c78SCharulatha V { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */ 19497f904c78SCharulatha V { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */ 19507f904c78SCharulatha V { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */ 19517f904c78SCharulatha V { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */ 19527f904c78SCharulatha V { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */ 19537f904c78SCharulatha V }; 19547f904c78SCharulatha V 19557f904c78SCharulatha V static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = { 19567f904c78SCharulatha V &omap2430_l4_core__mcspi1, 19577f904c78SCharulatha V }; 19587f904c78SCharulatha V 19597f904c78SCharulatha V static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { 19607f904c78SCharulatha V .num_chipselect = 4, 19617f904c78SCharulatha V }; 19627f904c78SCharulatha V 19637f904c78SCharulatha V static struct omap_hwmod omap2430_mcspi1_hwmod = { 19647f904c78SCharulatha V .name = "mcspi1_hwmod", 19657f904c78SCharulatha V .mpu_irqs = omap2430_mcspi1_mpu_irqs, 19667f904c78SCharulatha V .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi1_mpu_irqs), 19677f904c78SCharulatha V .sdma_reqs = omap2430_mcspi1_sdma_reqs, 19687f904c78SCharulatha V .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi1_sdma_reqs), 19697f904c78SCharulatha V .main_clk = "mcspi1_fck", 19707f904c78SCharulatha V .prcm = { 19717f904c78SCharulatha V .omap2 = { 19727f904c78SCharulatha V .module_offs = CORE_MOD, 19737f904c78SCharulatha V .prcm_reg_id = 1, 19747f904c78SCharulatha V .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, 19757f904c78SCharulatha V .idlest_reg_id = 1, 19767f904c78SCharulatha V .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, 19777f904c78SCharulatha V }, 19787f904c78SCharulatha V }, 19797f904c78SCharulatha V .slaves = omap2430_mcspi1_slaves, 19807f904c78SCharulatha V .slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves), 19817f904c78SCharulatha V .class = &omap2430_mcspi_class, 19827f904c78SCharulatha V .dev_attr = &omap_mcspi1_dev_attr, 19837f904c78SCharulatha V .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 19847f904c78SCharulatha V }; 19857f904c78SCharulatha V 19867f904c78SCharulatha V /* mcspi2 */ 19877f904c78SCharulatha V static struct omap_hwmod_irq_info omap2430_mcspi2_mpu_irqs[] = { 19887f904c78SCharulatha V { .irq = 66 }, 19897f904c78SCharulatha V }; 19907f904c78SCharulatha V 19917f904c78SCharulatha V static struct omap_hwmod_dma_info omap2430_mcspi2_sdma_reqs[] = { 19927f904c78SCharulatha V { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */ 19937f904c78SCharulatha V { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */ 19947f904c78SCharulatha V { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */ 19957f904c78SCharulatha V { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */ 19967f904c78SCharulatha V }; 19977f904c78SCharulatha V 19987f904c78SCharulatha V static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = { 19997f904c78SCharulatha V &omap2430_l4_core__mcspi2, 20007f904c78SCharulatha V }; 20017f904c78SCharulatha V 20027f904c78SCharulatha V static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { 20037f904c78SCharulatha V .num_chipselect = 2, 20047f904c78SCharulatha V }; 20057f904c78SCharulatha V 20067f904c78SCharulatha V static struct omap_hwmod omap2430_mcspi2_hwmod = { 20077f904c78SCharulatha V .name = "mcspi2_hwmod", 20087f904c78SCharulatha V .mpu_irqs = omap2430_mcspi2_mpu_irqs, 20097f904c78SCharulatha V .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi2_mpu_irqs), 20107f904c78SCharulatha V .sdma_reqs = omap2430_mcspi2_sdma_reqs, 20117f904c78SCharulatha V .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi2_sdma_reqs), 20127f904c78SCharulatha V .main_clk = "mcspi2_fck", 20137f904c78SCharulatha V .prcm = { 20147f904c78SCharulatha V .omap2 = { 20157f904c78SCharulatha V .module_offs = CORE_MOD, 20167f904c78SCharulatha V .prcm_reg_id = 1, 20177f904c78SCharulatha V .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, 20187f904c78SCharulatha V .idlest_reg_id = 1, 20197f904c78SCharulatha V .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, 20207f904c78SCharulatha V }, 20217f904c78SCharulatha V }, 20227f904c78SCharulatha V .slaves = omap2430_mcspi2_slaves, 20237f904c78SCharulatha V .slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves), 20247f904c78SCharulatha V .class = &omap2430_mcspi_class, 20257f904c78SCharulatha V .dev_attr = &omap_mcspi2_dev_attr, 20267f904c78SCharulatha V .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 20277f904c78SCharulatha V }; 20287f904c78SCharulatha V 20297f904c78SCharulatha V /* mcspi3 */ 20307f904c78SCharulatha V static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = { 20317f904c78SCharulatha V { .irq = 91 }, 20327f904c78SCharulatha V }; 20337f904c78SCharulatha V 20347f904c78SCharulatha V static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = { 20357f904c78SCharulatha V { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */ 20367f904c78SCharulatha V { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */ 20377f904c78SCharulatha V { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */ 20387f904c78SCharulatha V { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */ 20397f904c78SCharulatha V }; 20407f904c78SCharulatha V 20417f904c78SCharulatha V static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = { 20427f904c78SCharulatha V &omap2430_l4_core__mcspi3, 20437f904c78SCharulatha V }; 20447f904c78SCharulatha V 20457f904c78SCharulatha V static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { 20467f904c78SCharulatha V .num_chipselect = 2, 20477f904c78SCharulatha V }; 20487f904c78SCharulatha V 20497f904c78SCharulatha V static struct omap_hwmod omap2430_mcspi3_hwmod = { 20507f904c78SCharulatha V .name = "mcspi3_hwmod", 20517f904c78SCharulatha V .mpu_irqs = omap2430_mcspi3_mpu_irqs, 20527f904c78SCharulatha V .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi3_mpu_irqs), 20537f904c78SCharulatha V .sdma_reqs = omap2430_mcspi3_sdma_reqs, 20547f904c78SCharulatha V .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi3_sdma_reqs), 20557f904c78SCharulatha V .main_clk = "mcspi3_fck", 20567f904c78SCharulatha V .prcm = { 20577f904c78SCharulatha V .omap2 = { 20587f904c78SCharulatha V .module_offs = CORE_MOD, 20597f904c78SCharulatha V .prcm_reg_id = 2, 20607f904c78SCharulatha V .module_bit = OMAP2430_EN_MCSPI3_SHIFT, 20617f904c78SCharulatha V .idlest_reg_id = 2, 20627f904c78SCharulatha V .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT, 20637f904c78SCharulatha V }, 20647f904c78SCharulatha V }, 20657f904c78SCharulatha V .slaves = omap2430_mcspi3_slaves, 20667f904c78SCharulatha V .slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves), 20677f904c78SCharulatha V .class = &omap2430_mcspi_class, 20687f904c78SCharulatha V .dev_attr = &omap_mcspi3_dev_attr, 20697f904c78SCharulatha V .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 20707f904c78SCharulatha V }; 20717f904c78SCharulatha V 207204aa67deSTony Lindgren /* 207344d02acfSHema HK * usbhsotg 207444d02acfSHema HK */ 207544d02acfSHema HK static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = { 207644d02acfSHema HK .rev_offs = 0x0400, 207744d02acfSHema HK .sysc_offs = 0x0404, 207844d02acfSHema HK .syss_offs = 0x0408, 207944d02acfSHema HK .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| 208044d02acfSHema HK SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 208144d02acfSHema HK SYSC_HAS_AUTOIDLE), 208244d02acfSHema HK .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 208344d02acfSHema HK MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 208444d02acfSHema HK .sysc_fields = &omap_hwmod_sysc_type1, 208544d02acfSHema HK }; 208644d02acfSHema HK 208744d02acfSHema HK static struct omap_hwmod_class usbotg_class = { 208844d02acfSHema HK .name = "usbotg", 208944d02acfSHema HK .sysc = &omap2430_usbhsotg_sysc, 209044d02acfSHema HK }; 209144d02acfSHema HK 209244d02acfSHema HK /* usb_otg_hs */ 209344d02acfSHema HK static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = { 209444d02acfSHema HK 209544d02acfSHema HK { .name = "mc", .irq = 92 }, 209644d02acfSHema HK { .name = "dma", .irq = 93 }, 209744d02acfSHema HK }; 209844d02acfSHema HK 209944d02acfSHema HK static struct omap_hwmod omap2430_usbhsotg_hwmod = { 210044d02acfSHema HK .name = "usb_otg_hs", 210144d02acfSHema HK .mpu_irqs = omap2430_usbhsotg_mpu_irqs, 210244d02acfSHema HK .mpu_irqs_cnt = ARRAY_SIZE(omap2430_usbhsotg_mpu_irqs), 210344d02acfSHema HK .main_clk = "usbhs_ick", 210444d02acfSHema HK .prcm = { 210544d02acfSHema HK .omap2 = { 210644d02acfSHema HK .prcm_reg_id = 1, 210744d02acfSHema HK .module_bit = OMAP2430_EN_USBHS_MASK, 210844d02acfSHema HK .module_offs = CORE_MOD, 210944d02acfSHema HK .idlest_reg_id = 1, 211044d02acfSHema HK .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT, 211144d02acfSHema HK }, 211244d02acfSHema HK }, 211344d02acfSHema HK .masters = omap2430_usbhsotg_masters, 211444d02acfSHema HK .masters_cnt = ARRAY_SIZE(omap2430_usbhsotg_masters), 211544d02acfSHema HK .slaves = omap2430_usbhsotg_slaves, 211644d02acfSHema HK .slaves_cnt = ARRAY_SIZE(omap2430_usbhsotg_slaves), 211744d02acfSHema HK .class = &usbotg_class, 211844d02acfSHema HK /* 211944d02acfSHema HK * Erratum ID: i479 idle_req / idle_ack mechanism potentially 212044d02acfSHema HK * broken when autoidle is enabled 212144d02acfSHema HK * workaround is to disable the autoidle bit at module level. 212244d02acfSHema HK */ 212344d02acfSHema HK .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE 212444d02acfSHema HK | HWMOD_SWSUP_MSTANDBY, 212544d02acfSHema HK .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 212644d02acfSHema HK }; 212744d02acfSHema HK 212804aa67deSTony Lindgren 212904aa67deSTony Lindgren 21307359154eSPaul Walmsley static __initdata struct omap_hwmod *omap2430_hwmods[] = { 21314a7cf90aSKevin Hilman &omap2430_l3_main_hwmod, 21327359154eSPaul Walmsley &omap2430_l4_core_hwmod, 21337359154eSPaul Walmsley &omap2430_l4_wkup_hwmod, 21347359154eSPaul Walmsley &omap2430_mpu_hwmod, 213508072acfSPaul Walmsley &omap2430_iva_hwmod, 2136b6b58229SThara Gopinath 2137b6b58229SThara Gopinath &omap2430_timer1_hwmod, 2138b6b58229SThara Gopinath &omap2430_timer2_hwmod, 2139b6b58229SThara Gopinath &omap2430_timer3_hwmod, 2140b6b58229SThara Gopinath &omap2430_timer4_hwmod, 2141b6b58229SThara Gopinath &omap2430_timer5_hwmod, 2142b6b58229SThara Gopinath &omap2430_timer6_hwmod, 2143b6b58229SThara Gopinath &omap2430_timer7_hwmod, 2144b6b58229SThara Gopinath &omap2430_timer8_hwmod, 2145b6b58229SThara Gopinath &omap2430_timer9_hwmod, 2146b6b58229SThara Gopinath &omap2430_timer10_hwmod, 2147b6b58229SThara Gopinath &omap2430_timer11_hwmod, 2148b6b58229SThara Gopinath &omap2430_timer12_hwmod, 2149b6b58229SThara Gopinath 2150165e2161SVaradarajan, Charulatha &omap2430_wd_timer2_hwmod, 2151046465b7SKevin Hilman &omap2430_uart1_hwmod, 2152046465b7SKevin Hilman &omap2430_uart2_hwmod, 2153046465b7SKevin Hilman &omap2430_uart3_hwmod, 2154de56dbb6SSenthilvadivu Guruswamy /* dss class */ 2155de56dbb6SSenthilvadivu Guruswamy &omap2430_dss_core_hwmod, 2156de56dbb6SSenthilvadivu Guruswamy &omap2430_dss_dispc_hwmod, 2157de56dbb6SSenthilvadivu Guruswamy &omap2430_dss_rfbi_hwmod, 2158de56dbb6SSenthilvadivu Guruswamy &omap2430_dss_venc_hwmod, 2159de56dbb6SSenthilvadivu Guruswamy /* i2c class */ 21602004290fSPaul Walmsley &omap2430_i2c1_hwmod, 21612004290fSPaul Walmsley &omap2430_i2c2_hwmod, 2162aeac0e44SVaradarajan, Charulatha 2163aeac0e44SVaradarajan, Charulatha /* gpio class */ 2164aeac0e44SVaradarajan, Charulatha &omap2430_gpio1_hwmod, 2165aeac0e44SVaradarajan, Charulatha &omap2430_gpio2_hwmod, 2166aeac0e44SVaradarajan, Charulatha &omap2430_gpio3_hwmod, 2167aeac0e44SVaradarajan, Charulatha &omap2430_gpio4_hwmod, 2168aeac0e44SVaradarajan, Charulatha &omap2430_gpio5_hwmod, 216982cbd1aeSG, Manjunath Kondaiah 217082cbd1aeSG, Manjunath Kondaiah /* dma_system class*/ 217182cbd1aeSG, Manjunath Kondaiah &omap2430_dma_system_hwmod, 21727f904c78SCharulatha V 21737f904c78SCharulatha V /* mcspi class */ 21747f904c78SCharulatha V &omap2430_mcspi1_hwmod, 21757f904c78SCharulatha V &omap2430_mcspi2_hwmod, 21767f904c78SCharulatha V &omap2430_mcspi3_hwmod, 217704aa67deSTony Lindgren 217844d02acfSHema HK /* usbotg class*/ 217944d02acfSHema HK &omap2430_usbhsotg_hwmod, 218004aa67deSTony Lindgren 21817359154eSPaul Walmsley NULL, 21827359154eSPaul Walmsley }; 21837359154eSPaul Walmsley 21847359154eSPaul Walmsley int __init omap2430_hwmod_init(void) 21857359154eSPaul Walmsley { 2186550c8092SPaul Walmsley return omap_hwmod_register(omap2430_hwmods); 21877359154eSPaul Walmsley } 2188