1 /*
2  * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
3  *
4  * Copyright (C) 2009-2011 Nokia Corporation
5  * Copyright (C) 2012 Texas Instruments, Inc.
6  * Paul Walmsley
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  *
12  * XXX handle crossbar/shared link difference for L3?
13  * XXX these should be marked initdata for multi-OMAP kernels
14  */
15 
16 #include <linux/i2c-omap.h>
17 #include <linux/platform_data/spi-omap2-mcspi.h>
18 #include <linux/omap-dma.h>
19 #include <plat/dmtimer.h>
20 
21 #include "omap_hwmod.h"
22 #include "l3_2xxx.h"
23 #include "l4_2xxx.h"
24 
25 #include "omap_hwmod_common_data.h"
26 
27 #include "cm-regbits-24xx.h"
28 #include "prm-regbits-24xx.h"
29 #include "i2c.h"
30 #include "mmc.h"
31 #include "serial.h"
32 #include "wd_timer.h"
33 
34 /*
35  * OMAP2420 hardware module integration data
36  *
37  * All of the data in this section should be autogeneratable from the
38  * TI hardware database or other technical documentation.  Data that
39  * is driver-specific or driver-kernel integration-specific belongs
40  * elsewhere.
41  */
42 
43 /*
44  * IP blocks
45  */
46 
47 /* IVA1 (IVA1) */
48 static struct omap_hwmod_class iva1_hwmod_class = {
49 	.name		= "iva1",
50 };
51 
52 static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
53 	{ .name = "iva", .rst_shift = 8 },
54 };
55 
56 static struct omap_hwmod omap2420_iva_hwmod = {
57 	.name		= "iva",
58 	.class		= &iva1_hwmod_class,
59 	.clkdm_name	= "iva1_clkdm",
60 	.rst_lines	= omap2420_iva_resets,
61 	.rst_lines_cnt	= ARRAY_SIZE(omap2420_iva_resets),
62 	.main_clk	= "iva1_ifck",
63 };
64 
65 /* DSP */
66 static struct omap_hwmod_class dsp_hwmod_class = {
67 	.name		= "dsp",
68 };
69 
70 static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
71 	{ .name = "logic", .rst_shift = 0 },
72 	{ .name = "mmu", .rst_shift = 1 },
73 };
74 
75 static struct omap_hwmod omap2420_dsp_hwmod = {
76 	.name		= "dsp",
77 	.class		= &dsp_hwmod_class,
78 	.clkdm_name	= "dsp_clkdm",
79 	.rst_lines	= omap2420_dsp_resets,
80 	.rst_lines_cnt	= ARRAY_SIZE(omap2420_dsp_resets),
81 	.main_clk	= "dsp_fck",
82 };
83 
84 /* I2C common */
85 static struct omap_hwmod_class_sysconfig i2c_sysc = {
86 	.rev_offs	= 0x00,
87 	.sysc_offs	= 0x20,
88 	.syss_offs	= 0x10,
89 	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
90 	.sysc_fields	= &omap_hwmod_sysc_type1,
91 };
92 
93 static struct omap_hwmod_class i2c_class = {
94 	.name		= "i2c",
95 	.sysc		= &i2c_sysc,
96 	.rev		= OMAP_I2C_IP_VERSION_1,
97 	.reset		= &omap_i2c_reset,
98 };
99 
100 static struct omap_i2c_dev_attr i2c_dev_attr = {
101 	.flags		= OMAP_I2C_FLAG_NO_FIFO |
102 			  OMAP_I2C_FLAG_SIMPLE_CLOCK |
103 			  OMAP_I2C_FLAG_16BIT_DATA_REG |
104 			  OMAP_I2C_FLAG_BUS_SHIFT_2,
105 };
106 
107 /* I2C1 */
108 static struct omap_hwmod omap2420_i2c1_hwmod = {
109 	.name		= "i2c1",
110 	.mpu_irqs	= omap2_i2c1_mpu_irqs,
111 	.sdma_reqs	= omap2_i2c1_sdma_reqs,
112 	.main_clk	= "i2c1_fck",
113 	.prcm		= {
114 		.omap2 = {
115 			.module_offs = CORE_MOD,
116 			.prcm_reg_id = 1,
117 			.module_bit = OMAP2420_EN_I2C1_SHIFT,
118 			.idlest_reg_id = 1,
119 			.idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
120 		},
121 	},
122 	.class		= &i2c_class,
123 	.dev_attr	= &i2c_dev_attr,
124 	/*
125 	 * From mach-omap2/pm24xx.c: "Putting MPU into the WFI state
126 	 * while a transfer is active seems to cause the I2C block to
127 	 * timeout. Why? Good question."
128 	 */
129 	.flags		= (HWMOD_16BIT_REG | HWMOD_BLOCK_WFI),
130 };
131 
132 /* I2C2 */
133 static struct omap_hwmod omap2420_i2c2_hwmod = {
134 	.name		= "i2c2",
135 	.mpu_irqs	= omap2_i2c2_mpu_irqs,
136 	.sdma_reqs	= omap2_i2c2_sdma_reqs,
137 	.main_clk	= "i2c2_fck",
138 	.prcm		= {
139 		.omap2 = {
140 			.module_offs = CORE_MOD,
141 			.prcm_reg_id = 1,
142 			.module_bit = OMAP2420_EN_I2C2_SHIFT,
143 			.idlest_reg_id = 1,
144 			.idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
145 		},
146 	},
147 	.class		= &i2c_class,
148 	.dev_attr	= &i2c_dev_attr,
149 	.flags		= HWMOD_16BIT_REG,
150 };
151 
152 /* dma attributes */
153 static struct omap_dma_dev_attr dma_dev_attr = {
154 	.dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
155 						IS_CSSA_32 | IS_CDSA_32,
156 	.lch_count = 32,
157 };
158 
159 static struct omap_hwmod omap2420_dma_system_hwmod = {
160 	.name		= "dma",
161 	.class		= &omap2xxx_dma_hwmod_class,
162 	.mpu_irqs	= omap2_dma_system_irqs,
163 	.main_clk	= "core_l3_ck",
164 	.dev_attr	= &dma_dev_attr,
165 	.flags		= HWMOD_NO_IDLEST,
166 };
167 
168 /* mailbox */
169 static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
170 	{ .name = "dsp", .irq = 26 + OMAP_INTC_START, },
171 	{ .name = "iva", .irq = 34 + OMAP_INTC_START, },
172 	{ .irq = -1 },
173 };
174 
175 static struct omap_hwmod omap2420_mailbox_hwmod = {
176 	.name		= "mailbox",
177 	.class		= &omap2xxx_mailbox_hwmod_class,
178 	.mpu_irqs	= omap2420_mailbox_irqs,
179 	.main_clk	= "mailboxes_ick",
180 	.prcm		= {
181 		.omap2 = {
182 			.prcm_reg_id = 1,
183 			.module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
184 			.module_offs = CORE_MOD,
185 			.idlest_reg_id = 1,
186 			.idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
187 		},
188 	},
189 };
190 
191 /*
192  * 'mcbsp' class
193  * multi channel buffered serial port controller
194  */
195 
196 static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
197 	.name = "mcbsp",
198 };
199 
200 static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
201 	{ .role = "pad_fck", .clk = "mcbsp_clks" },
202 	{ .role = "prcm_fck", .clk = "func_96m_ck" },
203 };
204 
205 /* mcbsp1 */
206 static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
207 	{ .name = "tx", .irq = 59 + OMAP_INTC_START, },
208 	{ .name = "rx", .irq = 60 + OMAP_INTC_START, },
209 	{ .irq = -1 },
210 };
211 
212 static struct omap_hwmod omap2420_mcbsp1_hwmod = {
213 	.name		= "mcbsp1",
214 	.class		= &omap2420_mcbsp_hwmod_class,
215 	.mpu_irqs	= omap2420_mcbsp1_irqs,
216 	.sdma_reqs	= omap2_mcbsp1_sdma_reqs,
217 	.main_clk	= "mcbsp1_fck",
218 	.prcm		= {
219 		.omap2 = {
220 			.prcm_reg_id = 1,
221 			.module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
222 			.module_offs = CORE_MOD,
223 			.idlest_reg_id = 1,
224 			.idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
225 		},
226 	},
227 	.opt_clks	= mcbsp_opt_clks,
228 	.opt_clks_cnt	= ARRAY_SIZE(mcbsp_opt_clks),
229 };
230 
231 /* mcbsp2 */
232 static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
233 	{ .name = "tx", .irq = 62 + OMAP_INTC_START, },
234 	{ .name = "rx", .irq = 63 + OMAP_INTC_START, },
235 	{ .irq = -1 },
236 };
237 
238 static struct omap_hwmod omap2420_mcbsp2_hwmod = {
239 	.name		= "mcbsp2",
240 	.class		= &omap2420_mcbsp_hwmod_class,
241 	.mpu_irqs	= omap2420_mcbsp2_irqs,
242 	.sdma_reqs	= omap2_mcbsp2_sdma_reqs,
243 	.main_clk	= "mcbsp2_fck",
244 	.prcm		= {
245 		.omap2 = {
246 			.prcm_reg_id = 1,
247 			.module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
248 			.module_offs = CORE_MOD,
249 			.idlest_reg_id = 1,
250 			.idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
251 		},
252 	},
253 	.opt_clks	= mcbsp_opt_clks,
254 	.opt_clks_cnt	= ARRAY_SIZE(mcbsp_opt_clks),
255 };
256 
257 static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
258 	.rev_offs	= 0x3c,
259 	.sysc_offs	= 0x64,
260 	.syss_offs	= 0x68,
261 	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
262 	.sysc_fields	= &omap_hwmod_sysc_type1,
263 };
264 
265 static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
266 	.name	= "msdi",
267 	.sysc	= &omap2420_msdi_sysc,
268 	.reset	= &omap_msdi_reset,
269 };
270 
271 /* msdi1 */
272 static struct omap_hwmod_irq_info omap2420_msdi1_irqs[] = {
273 	{ .irq = 83 + OMAP_INTC_START, },
274 	{ .irq = -1 },
275 };
276 
277 static struct omap_hwmod_dma_info omap2420_msdi1_sdma_reqs[] = {
278 	{ .name = "tx", .dma_req = 61 }, /* OMAP24XX_DMA_MMC1_TX */
279 	{ .name = "rx", .dma_req = 62 }, /* OMAP24XX_DMA_MMC1_RX */
280 	{ .dma_req = -1 }
281 };
282 
283 static struct omap_hwmod omap2420_msdi1_hwmod = {
284 	.name		= "msdi1",
285 	.class		= &omap2420_msdi_hwmod_class,
286 	.mpu_irqs	= omap2420_msdi1_irqs,
287 	.sdma_reqs	= omap2420_msdi1_sdma_reqs,
288 	.main_clk	= "mmc_fck",
289 	.prcm		= {
290 		.omap2 = {
291 			.prcm_reg_id = 1,
292 			.module_bit = OMAP2420_EN_MMC_SHIFT,
293 			.module_offs = CORE_MOD,
294 			.idlest_reg_id = 1,
295 			.idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
296 		},
297 	},
298 	.flags		= HWMOD_16BIT_REG,
299 };
300 
301 /* HDQ1W/1-wire */
302 static struct omap_hwmod omap2420_hdq1w_hwmod = {
303 	.name		= "hdq1w",
304 	.mpu_irqs	= omap2_hdq1w_mpu_irqs,
305 	.main_clk	= "hdq_fck",
306 	.prcm		= {
307 		.omap2 = {
308 			.module_offs = CORE_MOD,
309 			.prcm_reg_id = 1,
310 			.module_bit = OMAP24XX_EN_HDQ_SHIFT,
311 			.idlest_reg_id = 1,
312 			.idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
313 		},
314 	},
315 	.class		= &omap2_hdq1w_class,
316 };
317 
318 /*
319  * interfaces
320  */
321 
322 /* L4 CORE -> I2C1 interface */
323 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
324 	.master		= &omap2xxx_l4_core_hwmod,
325 	.slave		= &omap2420_i2c1_hwmod,
326 	.clk		= "i2c1_ick",
327 	.addr		= omap2_i2c1_addr_space,
328 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
329 };
330 
331 /* L4 CORE -> I2C2 interface */
332 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
333 	.master		= &omap2xxx_l4_core_hwmod,
334 	.slave		= &omap2420_i2c2_hwmod,
335 	.clk		= "i2c2_ick",
336 	.addr		= omap2_i2c2_addr_space,
337 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
338 };
339 
340 /* IVA <- L3 interface */
341 static struct omap_hwmod_ocp_if omap2420_l3__iva = {
342 	.master		= &omap2xxx_l3_main_hwmod,
343 	.slave		= &omap2420_iva_hwmod,
344 	.clk		= "core_l3_ck",
345 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
346 };
347 
348 /* DSP <- L3 interface */
349 static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
350 	.master		= &omap2xxx_l3_main_hwmod,
351 	.slave		= &omap2420_dsp_hwmod,
352 	.clk		= "dsp_ick",
353 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
354 };
355 
356 static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
357 	{
358 		.pa_start	= 0x48028000,
359 		.pa_end		= 0x48028000 + SZ_1K - 1,
360 		.flags		= ADDR_TYPE_RT
361 	},
362 	{ }
363 };
364 
365 /* l4_wkup -> timer1 */
366 static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
367 	.master		= &omap2xxx_l4_wkup_hwmod,
368 	.slave		= &omap2xxx_timer1_hwmod,
369 	.clk		= "gpt1_ick",
370 	.addr		= omap2420_timer1_addrs,
371 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
372 };
373 
374 /* l4_wkup -> wd_timer2 */
375 static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
376 	{
377 		.pa_start	= 0x48022000,
378 		.pa_end		= 0x4802207f,
379 		.flags		= ADDR_TYPE_RT
380 	},
381 	{ }
382 };
383 
384 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
385 	.master		= &omap2xxx_l4_wkup_hwmod,
386 	.slave		= &omap2xxx_wd_timer2_hwmod,
387 	.clk		= "mpu_wdt_ick",
388 	.addr		= omap2420_wd_timer2_addrs,
389 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
390 };
391 
392 /* l4_wkup -> gpio1 */
393 static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
394 	{
395 		.pa_start	= 0x48018000,
396 		.pa_end		= 0x480181ff,
397 		.flags		= ADDR_TYPE_RT
398 	},
399 	{ }
400 };
401 
402 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
403 	.master		= &omap2xxx_l4_wkup_hwmod,
404 	.slave		= &omap2xxx_gpio1_hwmod,
405 	.clk		= "gpios_ick",
406 	.addr		= omap2420_gpio1_addr_space,
407 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
408 };
409 
410 /* l4_wkup -> gpio2 */
411 static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
412 	{
413 		.pa_start	= 0x4801a000,
414 		.pa_end		= 0x4801a1ff,
415 		.flags		= ADDR_TYPE_RT
416 	},
417 	{ }
418 };
419 
420 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
421 	.master		= &omap2xxx_l4_wkup_hwmod,
422 	.slave		= &omap2xxx_gpio2_hwmod,
423 	.clk		= "gpios_ick",
424 	.addr		= omap2420_gpio2_addr_space,
425 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
426 };
427 
428 /* l4_wkup -> gpio3 */
429 static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
430 	{
431 		.pa_start	= 0x4801c000,
432 		.pa_end		= 0x4801c1ff,
433 		.flags		= ADDR_TYPE_RT
434 	},
435 	{ }
436 };
437 
438 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
439 	.master		= &omap2xxx_l4_wkup_hwmod,
440 	.slave		= &omap2xxx_gpio3_hwmod,
441 	.clk		= "gpios_ick",
442 	.addr		= omap2420_gpio3_addr_space,
443 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
444 };
445 
446 /* l4_wkup -> gpio4 */
447 static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
448 	{
449 		.pa_start	= 0x4801e000,
450 		.pa_end		= 0x4801e1ff,
451 		.flags		= ADDR_TYPE_RT
452 	},
453 	{ }
454 };
455 
456 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
457 	.master		= &omap2xxx_l4_wkup_hwmod,
458 	.slave		= &omap2xxx_gpio4_hwmod,
459 	.clk		= "gpios_ick",
460 	.addr		= omap2420_gpio4_addr_space,
461 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
462 };
463 
464 /* dma_system -> L3 */
465 static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
466 	.master		= &omap2420_dma_system_hwmod,
467 	.slave		= &omap2xxx_l3_main_hwmod,
468 	.clk		= "core_l3_ck",
469 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
470 };
471 
472 /* l4_core -> dma_system */
473 static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
474 	.master		= &omap2xxx_l4_core_hwmod,
475 	.slave		= &omap2420_dma_system_hwmod,
476 	.clk		= "sdma_ick",
477 	.addr		= omap2_dma_system_addrs,
478 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
479 };
480 
481 /* l4_core -> mailbox */
482 static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
483 	.master		= &omap2xxx_l4_core_hwmod,
484 	.slave		= &omap2420_mailbox_hwmod,
485 	.addr		= omap2_mailbox_addrs,
486 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
487 };
488 
489 /* l4_core -> mcbsp1 */
490 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
491 	.master		= &omap2xxx_l4_core_hwmod,
492 	.slave		= &omap2420_mcbsp1_hwmod,
493 	.clk		= "mcbsp1_ick",
494 	.addr		= omap2_mcbsp1_addrs,
495 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
496 };
497 
498 /* l4_core -> mcbsp2 */
499 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
500 	.master		= &omap2xxx_l4_core_hwmod,
501 	.slave		= &omap2420_mcbsp2_hwmod,
502 	.clk		= "mcbsp2_ick",
503 	.addr		= omap2xxx_mcbsp2_addrs,
504 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
505 };
506 
507 static struct omap_hwmod_addr_space omap2420_msdi1_addrs[] = {
508 	{
509 		.pa_start	= 0x4809c000,
510 		.pa_end		= 0x4809c000 + SZ_128 - 1,
511 		.flags		= ADDR_TYPE_RT,
512 	},
513 	{ }
514 };
515 
516 /* l4_core -> msdi1 */
517 static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
518 	.master		= &omap2xxx_l4_core_hwmod,
519 	.slave		= &omap2420_msdi1_hwmod,
520 	.clk		= "mmc_ick",
521 	.addr		= omap2420_msdi1_addrs,
522 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
523 };
524 
525 /* l4_core -> hdq1w interface */
526 static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
527 	.master		= &omap2xxx_l4_core_hwmod,
528 	.slave		= &omap2420_hdq1w_hwmod,
529 	.clk		= "hdq_ick",
530 	.addr		= omap2_hdq1w_addr_space,
531 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
532 	.flags		= OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
533 };
534 
535 
536 /* l4_wkup -> 32ksync_counter */
537 static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = {
538 	{
539 		.pa_start	= 0x48004000,
540 		.pa_end		= 0x4800401f,
541 		.flags		= ADDR_TYPE_RT
542 	},
543 	{ }
544 };
545 
546 static struct omap_hwmod_addr_space omap2420_gpmc_addrs[] = {
547 	{
548 		.pa_start	= 0x6800a000,
549 		.pa_end		= 0x6800afff,
550 		.flags		= ADDR_TYPE_RT
551 	},
552 	{ }
553 };
554 
555 static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
556 	.master		= &omap2xxx_l4_wkup_hwmod,
557 	.slave		= &omap2xxx_counter_32k_hwmod,
558 	.clk		= "sync_32k_ick",
559 	.addr		= omap2420_counter_32k_addrs,
560 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
561 };
562 
563 static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
564 	.master		= &omap2xxx_l3_main_hwmod,
565 	.slave		= &omap2xxx_gpmc_hwmod,
566 	.clk		= "core_l3_ck",
567 	.addr		= omap2420_gpmc_addrs,
568 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
569 };
570 
571 static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
572 	&omap2xxx_l3_main__l4_core,
573 	&omap2xxx_mpu__l3_main,
574 	&omap2xxx_dss__l3,
575 	&omap2xxx_l4_core__mcspi1,
576 	&omap2xxx_l4_core__mcspi2,
577 	&omap2xxx_l4_core__l4_wkup,
578 	&omap2_l4_core__uart1,
579 	&omap2_l4_core__uart2,
580 	&omap2_l4_core__uart3,
581 	&omap2420_l4_core__i2c1,
582 	&omap2420_l4_core__i2c2,
583 	&omap2420_l3__iva,
584 	&omap2420_l3__dsp,
585 	&omap2420_l4_wkup__timer1,
586 	&omap2xxx_l4_core__timer2,
587 	&omap2xxx_l4_core__timer3,
588 	&omap2xxx_l4_core__timer4,
589 	&omap2xxx_l4_core__timer5,
590 	&omap2xxx_l4_core__timer6,
591 	&omap2xxx_l4_core__timer7,
592 	&omap2xxx_l4_core__timer8,
593 	&omap2xxx_l4_core__timer9,
594 	&omap2xxx_l4_core__timer10,
595 	&omap2xxx_l4_core__timer11,
596 	&omap2xxx_l4_core__timer12,
597 	&omap2420_l4_wkup__wd_timer2,
598 	&omap2xxx_l4_core__dss,
599 	&omap2xxx_l4_core__dss_dispc,
600 	&omap2xxx_l4_core__dss_rfbi,
601 	&omap2xxx_l4_core__dss_venc,
602 	&omap2420_l4_wkup__gpio1,
603 	&omap2420_l4_wkup__gpio2,
604 	&omap2420_l4_wkup__gpio3,
605 	&omap2420_l4_wkup__gpio4,
606 	&omap2420_dma_system__l3,
607 	&omap2420_l4_core__dma_system,
608 	&omap2420_l4_core__mailbox,
609 	&omap2420_l4_core__mcbsp1,
610 	&omap2420_l4_core__mcbsp2,
611 	&omap2420_l4_core__msdi1,
612 	&omap2xxx_l4_core__rng,
613 	&omap2xxx_l4_core__sham,
614 	&omap2xxx_l4_core__aes,
615 	&omap2420_l4_core__hdq1w,
616 	&omap2420_l4_wkup__counter_32k,
617 	&omap2420_l3__gpmc,
618 	NULL,
619 };
620 
621 int __init omap2420_hwmod_init(void)
622 {
623 	omap_hwmod_init();
624 	return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
625 }
626