1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
4  *
5  * Copyright (C) 2009-2011 Nokia Corporation
6  * Copyright (C) 2012 Texas Instruments, Inc.
7  * Paul Walmsley
8  *
9  * XXX handle crossbar/shared link difference for L3?
10  * XXX these should be marked initdata for multi-OMAP kernels
11  */
12 
13 #include <linux/platform_data/i2c-omap.h>
14 
15 #include "omap_hwmod.h"
16 #include "l3_2xxx.h"
17 #include "l4_2xxx.h"
18 
19 #include "omap_hwmod_common_data.h"
20 
21 #include "cm-regbits-24xx.h"
22 #include "prm-regbits-24xx.h"
23 #include "i2c.h"
24 #include "mmc.h"
25 #include "serial.h"
26 #include "wd_timer.h"
27 
28 /*
29  * OMAP2420 hardware module integration data
30  *
31  * All of the data in this section should be autogeneratable from the
32  * TI hardware database or other technical documentation.  Data that
33  * is driver-specific or driver-kernel integration-specific belongs
34  * elsewhere.
35  */
36 
37 /*
38  * IP blocks
39  */
40 
41 /* IVA1 (IVA1) */
42 static struct omap_hwmod_class iva1_hwmod_class = {
43 	.name		= "iva1",
44 };
45 
46 static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
47 	{ .name = "iva", .rst_shift = 8 },
48 };
49 
50 static struct omap_hwmod omap2420_iva_hwmod = {
51 	.name		= "iva",
52 	.class		= &iva1_hwmod_class,
53 	.clkdm_name	= "iva1_clkdm",
54 	.rst_lines	= omap2420_iva_resets,
55 	.rst_lines_cnt	= ARRAY_SIZE(omap2420_iva_resets),
56 	.main_clk	= "iva1_ifck",
57 };
58 
59 /* DSP */
60 static struct omap_hwmod_class dsp_hwmod_class = {
61 	.name		= "dsp",
62 };
63 
64 static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
65 	{ .name = "logic", .rst_shift = 0 },
66 	{ .name = "mmu", .rst_shift = 1 },
67 };
68 
69 static struct omap_hwmod omap2420_dsp_hwmod = {
70 	.name		= "dsp",
71 	.class		= &dsp_hwmod_class,
72 	.clkdm_name	= "dsp_clkdm",
73 	.rst_lines	= omap2420_dsp_resets,
74 	.rst_lines_cnt	= ARRAY_SIZE(omap2420_dsp_resets),
75 	.main_clk	= "dsp_fck",
76 };
77 
78 /* I2C common */
79 static struct omap_hwmod_class_sysconfig i2c_sysc = {
80 	.rev_offs	= 0x00,
81 	.sysc_offs	= 0x20,
82 	.syss_offs	= 0x10,
83 	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
84 	.sysc_fields	= &omap_hwmod_sysc_type1,
85 };
86 
87 static struct omap_hwmod_class i2c_class = {
88 	.name		= "i2c",
89 	.sysc		= &i2c_sysc,
90 	.reset		= &omap_i2c_reset,
91 };
92 
93 /* I2C1 */
94 static struct omap_hwmod omap2420_i2c1_hwmod = {
95 	.name		= "i2c1",
96 	.main_clk	= "i2c1_fck",
97 	.prcm		= {
98 		.omap2 = {
99 			.module_offs = CORE_MOD,
100 			.idlest_reg_id = 1,
101 			.idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
102 		},
103 	},
104 	.class		= &i2c_class,
105 	/*
106 	 * From mach-omap2/pm24xx.c: "Putting MPU into the WFI state
107 	 * while a transfer is active seems to cause the I2C block to
108 	 * timeout. Why? Good question."
109 	 */
110 	.flags		= (HWMOD_16BIT_REG | HWMOD_BLOCK_WFI),
111 };
112 
113 /* I2C2 */
114 static struct omap_hwmod omap2420_i2c2_hwmod = {
115 	.name		= "i2c2",
116 	.main_clk	= "i2c2_fck",
117 	.prcm		= {
118 		.omap2 = {
119 			.module_offs = CORE_MOD,
120 			.idlest_reg_id = 1,
121 			.idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
122 		},
123 	},
124 	.class		= &i2c_class,
125 	.flags		= HWMOD_16BIT_REG,
126 };
127 
128 /* mailbox */
129 static struct omap_hwmod omap2420_mailbox_hwmod = {
130 	.name		= "mailbox",
131 	.class		= &omap2xxx_mailbox_hwmod_class,
132 	.main_clk	= "mailboxes_ick",
133 	.prcm		= {
134 		.omap2 = {
135 			.module_offs = CORE_MOD,
136 			.idlest_reg_id = 1,
137 			.idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
138 		},
139 	},
140 };
141 
142 /*
143  * 'mcbsp' class
144  * multi channel buffered serial port controller
145  */
146 
147 static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
148 	.name = "mcbsp",
149 };
150 
151 static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
152 	{ .role = "pad_fck", .clk = "mcbsp_clks" },
153 	{ .role = "prcm_fck", .clk = "func_96m_ck" },
154 };
155 
156 /* mcbsp1 */
157 static struct omap_hwmod omap2420_mcbsp1_hwmod = {
158 	.name		= "mcbsp1",
159 	.class		= &omap2420_mcbsp_hwmod_class,
160 	.main_clk	= "mcbsp1_fck",
161 	.prcm		= {
162 		.omap2 = {
163 			.module_offs = CORE_MOD,
164 			.idlest_reg_id = 1,
165 			.idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
166 		},
167 	},
168 	.opt_clks	= mcbsp_opt_clks,
169 	.opt_clks_cnt	= ARRAY_SIZE(mcbsp_opt_clks),
170 };
171 
172 /* mcbsp2 */
173 static struct omap_hwmod omap2420_mcbsp2_hwmod = {
174 	.name		= "mcbsp2",
175 	.class		= &omap2420_mcbsp_hwmod_class,
176 	.main_clk	= "mcbsp2_fck",
177 	.prcm		= {
178 		.omap2 = {
179 			.module_offs = CORE_MOD,
180 			.idlest_reg_id = 1,
181 			.idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
182 		},
183 	},
184 	.opt_clks	= mcbsp_opt_clks,
185 	.opt_clks_cnt	= ARRAY_SIZE(mcbsp_opt_clks),
186 };
187 
188 static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
189 	.rev_offs	= 0x3c,
190 	.sysc_offs	= 0x64,
191 	.syss_offs	= 0x68,
192 	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
193 	.sysc_fields	= &omap_hwmod_sysc_type1,
194 };
195 
196 static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
197 	.name	= "msdi",
198 	.sysc	= &omap2420_msdi_sysc,
199 	.reset	= &omap_msdi_reset,
200 };
201 
202 /* msdi1 */
203 static struct omap_hwmod omap2420_msdi1_hwmod = {
204 	.name		= "msdi1",
205 	.class		= &omap2420_msdi_hwmod_class,
206 	.main_clk	= "mmc_fck",
207 	.prcm		= {
208 		.omap2 = {
209 			.module_offs = CORE_MOD,
210 			.idlest_reg_id = 1,
211 			.idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
212 		},
213 	},
214 	.flags		= HWMOD_16BIT_REG,
215 };
216 
217 /* HDQ1W/1-wire */
218 static struct omap_hwmod omap2420_hdq1w_hwmod = {
219 	.name		= "hdq1w",
220 	.main_clk	= "hdq_fck",
221 	.prcm		= {
222 		.omap2 = {
223 			.module_offs = CORE_MOD,
224 			.idlest_reg_id = 1,
225 			.idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
226 		},
227 	},
228 	.class		= &omap2_hdq1w_class,
229 };
230 
231 /*
232  * interfaces
233  */
234 
235 /* L4 CORE -> I2C1 interface */
236 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
237 	.master		= &omap2xxx_l4_core_hwmod,
238 	.slave		= &omap2420_i2c1_hwmod,
239 	.clk		= "i2c1_ick",
240 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
241 };
242 
243 /* L4 CORE -> I2C2 interface */
244 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
245 	.master		= &omap2xxx_l4_core_hwmod,
246 	.slave		= &omap2420_i2c2_hwmod,
247 	.clk		= "i2c2_ick",
248 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
249 };
250 
251 /* IVA <- L3 interface */
252 static struct omap_hwmod_ocp_if omap2420_l3__iva = {
253 	.master		= &omap2xxx_l3_main_hwmod,
254 	.slave		= &omap2420_iva_hwmod,
255 	.clk		= "core_l3_ck",
256 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
257 };
258 
259 /* DSP <- L3 interface */
260 static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
261 	.master		= &omap2xxx_l3_main_hwmod,
262 	.slave		= &omap2420_dsp_hwmod,
263 	.clk		= "dsp_ick",
264 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
265 };
266 
267 /* l4_wkup -> wd_timer2 */
268 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
269 	.master		= &omap2xxx_l4_wkup_hwmod,
270 	.slave		= &omap2xxx_wd_timer2_hwmod,
271 	.clk		= "mpu_wdt_ick",
272 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
273 };
274 
275 /* l4_wkup -> gpio1 */
276 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
277 	.master		= &omap2xxx_l4_wkup_hwmod,
278 	.slave		= &omap2xxx_gpio1_hwmod,
279 	.clk		= "gpios_ick",
280 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
281 };
282 
283 /* l4_wkup -> gpio2 */
284 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
285 	.master		= &omap2xxx_l4_wkup_hwmod,
286 	.slave		= &omap2xxx_gpio2_hwmod,
287 	.clk		= "gpios_ick",
288 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
289 };
290 
291 /* l4_wkup -> gpio3 */
292 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
293 	.master		= &omap2xxx_l4_wkup_hwmod,
294 	.slave		= &omap2xxx_gpio3_hwmod,
295 	.clk		= "gpios_ick",
296 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
297 };
298 
299 /* l4_wkup -> gpio4 */
300 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
301 	.master		= &omap2xxx_l4_wkup_hwmod,
302 	.slave		= &omap2xxx_gpio4_hwmod,
303 	.clk		= "gpios_ick",
304 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
305 };
306 
307 /* l4_core -> mailbox */
308 static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
309 	.master		= &omap2xxx_l4_core_hwmod,
310 	.slave		= &omap2420_mailbox_hwmod,
311 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
312 };
313 
314 /* l4_core -> mcbsp1 */
315 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
316 	.master		= &omap2xxx_l4_core_hwmod,
317 	.slave		= &omap2420_mcbsp1_hwmod,
318 	.clk		= "mcbsp1_ick",
319 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
320 };
321 
322 /* l4_core -> mcbsp2 */
323 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
324 	.master		= &omap2xxx_l4_core_hwmod,
325 	.slave		= &omap2420_mcbsp2_hwmod,
326 	.clk		= "mcbsp2_ick",
327 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
328 };
329 
330 /* l4_core -> msdi1 */
331 static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
332 	.master		= &omap2xxx_l4_core_hwmod,
333 	.slave		= &omap2420_msdi1_hwmod,
334 	.clk		= "mmc_ick",
335 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
336 };
337 
338 /* l4_core -> hdq1w interface */
339 static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
340 	.master		= &omap2xxx_l4_core_hwmod,
341 	.slave		= &omap2420_hdq1w_hwmod,
342 	.clk		= "hdq_ick",
343 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
344 	.flags		= OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
345 };
346 
347 static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
348 	.master		= &omap2xxx_l3_main_hwmod,
349 	.slave		= &omap2xxx_gpmc_hwmod,
350 	.clk		= "core_l3_ck",
351 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
352 };
353 
354 static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
355 	&omap2xxx_l3_main__l4_core,
356 	&omap2xxx_mpu__l3_main,
357 	&omap2xxx_dss__l3,
358 	&omap2xxx_l4_core__mcspi1,
359 	&omap2xxx_l4_core__mcspi2,
360 	&omap2xxx_l4_core__l4_wkup,
361 	&omap2_l4_core__uart1,
362 	&omap2_l4_core__uart2,
363 	&omap2_l4_core__uart3,
364 	&omap2420_l4_core__i2c1,
365 	&omap2420_l4_core__i2c2,
366 	&omap2420_l3__iva,
367 	&omap2420_l3__dsp,
368 	&omap2xxx_l4_core__timer3,
369 	&omap2xxx_l4_core__timer4,
370 	&omap2xxx_l4_core__timer5,
371 	&omap2xxx_l4_core__timer6,
372 	&omap2xxx_l4_core__timer7,
373 	&omap2xxx_l4_core__timer8,
374 	&omap2xxx_l4_core__timer9,
375 	&omap2xxx_l4_core__timer10,
376 	&omap2xxx_l4_core__timer11,
377 	&omap2xxx_l4_core__timer12,
378 	&omap2420_l4_wkup__wd_timer2,
379 	&omap2xxx_l4_core__dss,
380 	&omap2xxx_l4_core__dss_dispc,
381 	&omap2xxx_l4_core__dss_rfbi,
382 	&omap2xxx_l4_core__dss_venc,
383 	&omap2420_l4_wkup__gpio1,
384 	&omap2420_l4_wkup__gpio2,
385 	&omap2420_l4_wkup__gpio3,
386 	&omap2420_l4_wkup__gpio4,
387 	&omap2420_l4_core__mailbox,
388 	&omap2420_l4_core__mcbsp1,
389 	&omap2420_l4_core__mcbsp2,
390 	&omap2420_l4_core__msdi1,
391 	&omap2xxx_l4_core__rng,
392 	&omap2xxx_l4_core__sham,
393 	&omap2xxx_l4_core__aes,
394 	&omap2420_l4_core__hdq1w,
395 	&omap2420_l3__gpmc,
396 	NULL,
397 };
398 
399 int __init omap2420_hwmod_init(void)
400 {
401 	omap_hwmod_init();
402 	return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
403 }
404