1 /*
2  * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
3  *
4  * Copyright (C) 2009-2011 Nokia Corporation
5  * Copyright (C) 2012 Texas Instruments, Inc.
6  * Paul Walmsley
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  *
12  * XXX handle crossbar/shared link difference for L3?
13  * XXX these should be marked initdata for multi-OMAP kernels
14  */
15 
16 #include <linux/platform_data/i2c-omap.h>
17 #include <linux/omap-dma.h>
18 
19 #include "omap_hwmod.h"
20 #include "l3_2xxx.h"
21 #include "l4_2xxx.h"
22 
23 #include "omap_hwmod_common_data.h"
24 
25 #include "cm-regbits-24xx.h"
26 #include "prm-regbits-24xx.h"
27 #include "i2c.h"
28 #include "mmc.h"
29 #include "serial.h"
30 #include "wd_timer.h"
31 
32 /*
33  * OMAP2420 hardware module integration data
34  *
35  * All of the data in this section should be autogeneratable from the
36  * TI hardware database or other technical documentation.  Data that
37  * is driver-specific or driver-kernel integration-specific belongs
38  * elsewhere.
39  */
40 
41 /*
42  * IP blocks
43  */
44 
45 /* IVA1 (IVA1) */
46 static struct omap_hwmod_class iva1_hwmod_class = {
47 	.name		= "iva1",
48 };
49 
50 static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
51 	{ .name = "iva", .rst_shift = 8 },
52 };
53 
54 static struct omap_hwmod omap2420_iva_hwmod = {
55 	.name		= "iva",
56 	.class		= &iva1_hwmod_class,
57 	.clkdm_name	= "iva1_clkdm",
58 	.rst_lines	= omap2420_iva_resets,
59 	.rst_lines_cnt	= ARRAY_SIZE(omap2420_iva_resets),
60 	.main_clk	= "iva1_ifck",
61 };
62 
63 /* DSP */
64 static struct omap_hwmod_class dsp_hwmod_class = {
65 	.name		= "dsp",
66 };
67 
68 static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
69 	{ .name = "logic", .rst_shift = 0 },
70 	{ .name = "mmu", .rst_shift = 1 },
71 };
72 
73 static struct omap_hwmod omap2420_dsp_hwmod = {
74 	.name		= "dsp",
75 	.class		= &dsp_hwmod_class,
76 	.clkdm_name	= "dsp_clkdm",
77 	.rst_lines	= omap2420_dsp_resets,
78 	.rst_lines_cnt	= ARRAY_SIZE(omap2420_dsp_resets),
79 	.main_clk	= "dsp_fck",
80 };
81 
82 /* I2C common */
83 static struct omap_hwmod_class_sysconfig i2c_sysc = {
84 	.rev_offs	= 0x00,
85 	.sysc_offs	= 0x20,
86 	.syss_offs	= 0x10,
87 	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
88 	.sysc_fields	= &omap_hwmod_sysc_type1,
89 };
90 
91 static struct omap_hwmod_class i2c_class = {
92 	.name		= "i2c",
93 	.sysc		= &i2c_sysc,
94 	.reset		= &omap_i2c_reset,
95 };
96 
97 /* I2C1 */
98 static struct omap_hwmod omap2420_i2c1_hwmod = {
99 	.name		= "i2c1",
100 	.main_clk	= "i2c1_fck",
101 	.prcm		= {
102 		.omap2 = {
103 			.module_offs = CORE_MOD,
104 			.idlest_reg_id = 1,
105 			.idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
106 		},
107 	},
108 	.class		= &i2c_class,
109 	/*
110 	 * From mach-omap2/pm24xx.c: "Putting MPU into the WFI state
111 	 * while a transfer is active seems to cause the I2C block to
112 	 * timeout. Why? Good question."
113 	 */
114 	.flags		= (HWMOD_16BIT_REG | HWMOD_BLOCK_WFI),
115 };
116 
117 /* I2C2 */
118 static struct omap_hwmod omap2420_i2c2_hwmod = {
119 	.name		= "i2c2",
120 	.main_clk	= "i2c2_fck",
121 	.prcm		= {
122 		.omap2 = {
123 			.module_offs = CORE_MOD,
124 			.idlest_reg_id = 1,
125 			.idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
126 		},
127 	},
128 	.class		= &i2c_class,
129 	.flags		= HWMOD_16BIT_REG,
130 };
131 
132 /* dma attributes */
133 static struct omap_dma_dev_attr dma_dev_attr = {
134 	.dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
135 						IS_CSSA_32 | IS_CDSA_32,
136 	.lch_count = 32,
137 };
138 
139 static struct omap_hwmod omap2420_dma_system_hwmod = {
140 	.name		= "dma",
141 	.class		= &omap2xxx_dma_hwmod_class,
142 	.main_clk	= "core_l3_ck",
143 	.dev_attr	= &dma_dev_attr,
144 	.flags		= HWMOD_NO_IDLEST,
145 };
146 
147 /* mailbox */
148 static struct omap_hwmod omap2420_mailbox_hwmod = {
149 	.name		= "mailbox",
150 	.class		= &omap2xxx_mailbox_hwmod_class,
151 	.main_clk	= "mailboxes_ick",
152 	.prcm		= {
153 		.omap2 = {
154 			.module_offs = CORE_MOD,
155 			.idlest_reg_id = 1,
156 			.idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
157 		},
158 	},
159 };
160 
161 /*
162  * 'mcbsp' class
163  * multi channel buffered serial port controller
164  */
165 
166 static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
167 	.name = "mcbsp",
168 };
169 
170 static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
171 	{ .role = "pad_fck", .clk = "mcbsp_clks" },
172 	{ .role = "prcm_fck", .clk = "func_96m_ck" },
173 };
174 
175 /* mcbsp1 */
176 static struct omap_hwmod omap2420_mcbsp1_hwmod = {
177 	.name		= "mcbsp1",
178 	.class		= &omap2420_mcbsp_hwmod_class,
179 	.main_clk	= "mcbsp1_fck",
180 	.prcm		= {
181 		.omap2 = {
182 			.module_offs = CORE_MOD,
183 			.idlest_reg_id = 1,
184 			.idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
185 		},
186 	},
187 	.opt_clks	= mcbsp_opt_clks,
188 	.opt_clks_cnt	= ARRAY_SIZE(mcbsp_opt_clks),
189 };
190 
191 /* mcbsp2 */
192 static struct omap_hwmod omap2420_mcbsp2_hwmod = {
193 	.name		= "mcbsp2",
194 	.class		= &omap2420_mcbsp_hwmod_class,
195 	.main_clk	= "mcbsp2_fck",
196 	.prcm		= {
197 		.omap2 = {
198 			.module_offs = CORE_MOD,
199 			.idlest_reg_id = 1,
200 			.idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
201 		},
202 	},
203 	.opt_clks	= mcbsp_opt_clks,
204 	.opt_clks_cnt	= ARRAY_SIZE(mcbsp_opt_clks),
205 };
206 
207 static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
208 	.rev_offs	= 0x3c,
209 	.sysc_offs	= 0x64,
210 	.syss_offs	= 0x68,
211 	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
212 	.sysc_fields	= &omap_hwmod_sysc_type1,
213 };
214 
215 static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
216 	.name	= "msdi",
217 	.sysc	= &omap2420_msdi_sysc,
218 	.reset	= &omap_msdi_reset,
219 };
220 
221 /* msdi1 */
222 static struct omap_hwmod omap2420_msdi1_hwmod = {
223 	.name		= "msdi1",
224 	.class		= &omap2420_msdi_hwmod_class,
225 	.main_clk	= "mmc_fck",
226 	.prcm		= {
227 		.omap2 = {
228 			.module_offs = CORE_MOD,
229 			.idlest_reg_id = 1,
230 			.idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
231 		},
232 	},
233 	.flags		= HWMOD_16BIT_REG,
234 };
235 
236 /* HDQ1W/1-wire */
237 static struct omap_hwmod omap2420_hdq1w_hwmod = {
238 	.name		= "hdq1w",
239 	.main_clk	= "hdq_fck",
240 	.prcm		= {
241 		.omap2 = {
242 			.module_offs = CORE_MOD,
243 			.idlest_reg_id = 1,
244 			.idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
245 		},
246 	},
247 	.class		= &omap2_hdq1w_class,
248 };
249 
250 /*
251  * interfaces
252  */
253 
254 /* L4 CORE -> I2C1 interface */
255 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
256 	.master		= &omap2xxx_l4_core_hwmod,
257 	.slave		= &omap2420_i2c1_hwmod,
258 	.clk		= "i2c1_ick",
259 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
260 };
261 
262 /* L4 CORE -> I2C2 interface */
263 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
264 	.master		= &omap2xxx_l4_core_hwmod,
265 	.slave		= &omap2420_i2c2_hwmod,
266 	.clk		= "i2c2_ick",
267 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
268 };
269 
270 /* IVA <- L3 interface */
271 static struct omap_hwmod_ocp_if omap2420_l3__iva = {
272 	.master		= &omap2xxx_l3_main_hwmod,
273 	.slave		= &omap2420_iva_hwmod,
274 	.clk		= "core_l3_ck",
275 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
276 };
277 
278 /* DSP <- L3 interface */
279 static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
280 	.master		= &omap2xxx_l3_main_hwmod,
281 	.slave		= &omap2420_dsp_hwmod,
282 	.clk		= "dsp_ick",
283 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
284 };
285 
286 /* l4_wkup -> timer1 */
287 static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
288 	.master		= &omap2xxx_l4_wkup_hwmod,
289 	.slave		= &omap2xxx_timer1_hwmod,
290 	.clk		= "gpt1_ick",
291 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
292 };
293 
294 /* l4_wkup -> wd_timer2 */
295 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
296 	.master		= &omap2xxx_l4_wkup_hwmod,
297 	.slave		= &omap2xxx_wd_timer2_hwmod,
298 	.clk		= "mpu_wdt_ick",
299 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
300 };
301 
302 /* l4_wkup -> gpio1 */
303 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
304 	.master		= &omap2xxx_l4_wkup_hwmod,
305 	.slave		= &omap2xxx_gpio1_hwmod,
306 	.clk		= "gpios_ick",
307 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
308 };
309 
310 /* l4_wkup -> gpio2 */
311 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
312 	.master		= &omap2xxx_l4_wkup_hwmod,
313 	.slave		= &omap2xxx_gpio2_hwmod,
314 	.clk		= "gpios_ick",
315 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
316 };
317 
318 /* l4_wkup -> gpio3 */
319 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
320 	.master		= &omap2xxx_l4_wkup_hwmod,
321 	.slave		= &omap2xxx_gpio3_hwmod,
322 	.clk		= "gpios_ick",
323 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
324 };
325 
326 /* l4_wkup -> gpio4 */
327 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
328 	.master		= &omap2xxx_l4_wkup_hwmod,
329 	.slave		= &omap2xxx_gpio4_hwmod,
330 	.clk		= "gpios_ick",
331 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
332 };
333 
334 /* dma_system -> L3 */
335 static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
336 	.master		= &omap2420_dma_system_hwmod,
337 	.slave		= &omap2xxx_l3_main_hwmod,
338 	.clk		= "core_l3_ck",
339 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
340 };
341 
342 /* l4_core -> dma_system */
343 static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
344 	.master		= &omap2xxx_l4_core_hwmod,
345 	.slave		= &omap2420_dma_system_hwmod,
346 	.clk		= "sdma_ick",
347 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
348 };
349 
350 /* l4_core -> mailbox */
351 static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
352 	.master		= &omap2xxx_l4_core_hwmod,
353 	.slave		= &omap2420_mailbox_hwmod,
354 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
355 };
356 
357 /* l4_core -> mcbsp1 */
358 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
359 	.master		= &omap2xxx_l4_core_hwmod,
360 	.slave		= &omap2420_mcbsp1_hwmod,
361 	.clk		= "mcbsp1_ick",
362 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
363 };
364 
365 /* l4_core -> mcbsp2 */
366 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
367 	.master		= &omap2xxx_l4_core_hwmod,
368 	.slave		= &omap2420_mcbsp2_hwmod,
369 	.clk		= "mcbsp2_ick",
370 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
371 };
372 
373 /* l4_core -> msdi1 */
374 static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
375 	.master		= &omap2xxx_l4_core_hwmod,
376 	.slave		= &omap2420_msdi1_hwmod,
377 	.clk		= "mmc_ick",
378 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
379 };
380 
381 /* l4_core -> hdq1w interface */
382 static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
383 	.master		= &omap2xxx_l4_core_hwmod,
384 	.slave		= &omap2420_hdq1w_hwmod,
385 	.clk		= "hdq_ick",
386 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
387 	.flags		= OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
388 };
389 
390 
391 /* l4_wkup -> 32ksync_counter */
392 static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
393 	.master		= &omap2xxx_l4_wkup_hwmod,
394 	.slave		= &omap2xxx_counter_32k_hwmod,
395 	.clk		= "sync_32k_ick",
396 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
397 };
398 
399 static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
400 	.master		= &omap2xxx_l3_main_hwmod,
401 	.slave		= &omap2xxx_gpmc_hwmod,
402 	.clk		= "core_l3_ck",
403 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
404 };
405 
406 static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
407 	&omap2xxx_l3_main__l4_core,
408 	&omap2xxx_mpu__l3_main,
409 	&omap2xxx_dss__l3,
410 	&omap2xxx_l4_core__mcspi1,
411 	&omap2xxx_l4_core__mcspi2,
412 	&omap2xxx_l4_core__l4_wkup,
413 	&omap2_l4_core__uart1,
414 	&omap2_l4_core__uart2,
415 	&omap2_l4_core__uart3,
416 	&omap2420_l4_core__i2c1,
417 	&omap2420_l4_core__i2c2,
418 	&omap2420_l3__iva,
419 	&omap2420_l3__dsp,
420 	&omap2420_l4_wkup__timer1,
421 	&omap2xxx_l4_core__timer2,
422 	&omap2xxx_l4_core__timer3,
423 	&omap2xxx_l4_core__timer4,
424 	&omap2xxx_l4_core__timer5,
425 	&omap2xxx_l4_core__timer6,
426 	&omap2xxx_l4_core__timer7,
427 	&omap2xxx_l4_core__timer8,
428 	&omap2xxx_l4_core__timer9,
429 	&omap2xxx_l4_core__timer10,
430 	&omap2xxx_l4_core__timer11,
431 	&omap2xxx_l4_core__timer12,
432 	&omap2420_l4_wkup__wd_timer2,
433 	&omap2xxx_l4_core__dss,
434 	&omap2xxx_l4_core__dss_dispc,
435 	&omap2xxx_l4_core__dss_rfbi,
436 	&omap2xxx_l4_core__dss_venc,
437 	&omap2420_l4_wkup__gpio1,
438 	&omap2420_l4_wkup__gpio2,
439 	&omap2420_l4_wkup__gpio3,
440 	&omap2420_l4_wkup__gpio4,
441 	&omap2420_dma_system__l3,
442 	&omap2420_l4_core__dma_system,
443 	&omap2420_l4_core__mailbox,
444 	&omap2420_l4_core__mcbsp1,
445 	&omap2420_l4_core__mcbsp2,
446 	&omap2420_l4_core__msdi1,
447 	&omap2xxx_l4_core__rng,
448 	&omap2xxx_l4_core__sham,
449 	&omap2xxx_l4_core__aes,
450 	&omap2420_l4_core__hdq1w,
451 	&omap2420_l4_wkup__counter_32k,
452 	&omap2420_l3__gpmc,
453 	NULL,
454 };
455 
456 int __init omap2420_hwmod_init(void)
457 {
458 	omap_hwmod_init();
459 	return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
460 }
461