xref: /openbmc/linux/arch/arm/mach-omap2/omap_hwmod.h (revision c819e2cf)
1 /*
2  * omap_hwmod macros, structures
3  *
4  * Copyright (C) 2009-2011 Nokia Corporation
5  * Copyright (C) 2011-2012 Texas Instruments, Inc.
6  * Paul Walmsley
7  *
8  * Created in collaboration with (alphabetical order): Benoît Cousson,
9  * Kevin Hilman, Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari
10  * Poussa, Anand Sawant, Santosh Shilimkar, Richard Woodruff
11  *
12  * This program is free software; you can redistribute it and/or modify
13  * it under the terms of the GNU General Public License version 2 as
14  * published by the Free Software Foundation.
15  *
16  * These headers and macros are used to define OMAP on-chip module
17  * data and their integration with other OMAP modules and Linux.
18  * Copious documentation and references can also be found in the
19  * omap_hwmod code, in arch/arm/mach-omap2/omap_hwmod.c (as of this
20  * writing).
21  *
22  * To do:
23  * - add interconnect error log structures
24  * - add pinmuxing
25  * - init_conn_id_bit (CONNID_BIT_VECTOR)
26  * - implement default hwmod SMS/SDRC flags?
27  * - move Linux-specific data ("non-ROM data") out
28  *
29  */
30 #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
31 #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
32 
33 #include <linux/kernel.h>
34 #include <linux/init.h>
35 #include <linux/list.h>
36 #include <linux/ioport.h>
37 #include <linux/spinlock.h>
38 
39 struct omap_device;
40 
41 extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1;
42 extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
43 extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3;
44 
45 /*
46  * OCP SYSCONFIG bit shifts/masks TYPE1. These are for IPs compliant
47  * with the original PRCM protocol defined for OMAP2420
48  */
49 #define SYSC_TYPE1_MIDLEMODE_SHIFT	12
50 #define SYSC_TYPE1_MIDLEMODE_MASK	(0x3 << SYSC_TYPE1_MIDLEMODE_SHIFT)
51 #define SYSC_TYPE1_CLOCKACTIVITY_SHIFT	8
52 #define SYSC_TYPE1_CLOCKACTIVITY_MASK	(0x3 << SYSC_TYPE1_CLOCKACTIVITY_SHIFT)
53 #define SYSC_TYPE1_SIDLEMODE_SHIFT	3
54 #define SYSC_TYPE1_SIDLEMODE_MASK	(0x3 << SYSC_TYPE1_SIDLEMODE_SHIFT)
55 #define SYSC_TYPE1_ENAWAKEUP_SHIFT	2
56 #define SYSC_TYPE1_ENAWAKEUP_MASK	(1 << SYSC_TYPE1_ENAWAKEUP_SHIFT)
57 #define SYSC_TYPE1_SOFTRESET_SHIFT	1
58 #define SYSC_TYPE1_SOFTRESET_MASK	(1 << SYSC_TYPE1_SOFTRESET_SHIFT)
59 #define SYSC_TYPE1_AUTOIDLE_SHIFT	0
60 #define SYSC_TYPE1_AUTOIDLE_MASK	(1 << SYSC_TYPE1_AUTOIDLE_SHIFT)
61 
62 /*
63  * OCP SYSCONFIG bit shifts/masks TYPE2. These are for IPs compliant
64  * with the new PRCM protocol defined for new OMAP4 IPs.
65  */
66 #define SYSC_TYPE2_SOFTRESET_SHIFT	0
67 #define SYSC_TYPE2_SOFTRESET_MASK	(1 << SYSC_TYPE2_SOFTRESET_SHIFT)
68 #define SYSC_TYPE2_SIDLEMODE_SHIFT	2
69 #define SYSC_TYPE2_SIDLEMODE_MASK	(0x3 << SYSC_TYPE2_SIDLEMODE_SHIFT)
70 #define SYSC_TYPE2_MIDLEMODE_SHIFT	4
71 #define SYSC_TYPE2_MIDLEMODE_MASK	(0x3 << SYSC_TYPE2_MIDLEMODE_SHIFT)
72 #define SYSC_TYPE2_DMADISABLE_SHIFT	16
73 #define SYSC_TYPE2_DMADISABLE_MASK	(0x1 << SYSC_TYPE2_DMADISABLE_SHIFT)
74 
75 /*
76  * OCP SYSCONFIG bit shifts/masks TYPE3.
77  * This is applicable for some IPs present in AM33XX
78  */
79 #define SYSC_TYPE3_SIDLEMODE_SHIFT	0
80 #define SYSC_TYPE3_SIDLEMODE_MASK	(0x3 << SYSC_TYPE3_SIDLEMODE_SHIFT)
81 #define SYSC_TYPE3_MIDLEMODE_SHIFT	2
82 #define SYSC_TYPE3_MIDLEMODE_MASK	(0x3 << SYSC_TYPE3_MIDLEMODE_SHIFT)
83 
84 /* OCP SYSSTATUS bit shifts/masks */
85 #define SYSS_RESETDONE_SHIFT		0
86 #define SYSS_RESETDONE_MASK		(1 << SYSS_RESETDONE_SHIFT)
87 
88 /* Master standby/slave idle mode flags */
89 #define HWMOD_IDLEMODE_FORCE		(1 << 0)
90 #define HWMOD_IDLEMODE_NO		(1 << 1)
91 #define HWMOD_IDLEMODE_SMART		(1 << 2)
92 #define HWMOD_IDLEMODE_SMART_WKUP	(1 << 3)
93 
94 /* modulemode control type (SW or HW) */
95 #define MODULEMODE_HWCTRL		1
96 #define MODULEMODE_SWCTRL		2
97 
98 #define DEBUG_OMAP2UART1_FLAGS	0
99 #define DEBUG_OMAP2UART2_FLAGS	0
100 #define DEBUG_OMAP2UART3_FLAGS	0
101 #define DEBUG_OMAP3UART3_FLAGS	0
102 #define DEBUG_OMAP3UART4_FLAGS	0
103 #define DEBUG_OMAP4UART3_FLAGS	0
104 #define DEBUG_OMAP4UART4_FLAGS	0
105 #define DEBUG_TI81XXUART1_FLAGS	0
106 #define DEBUG_TI81XXUART2_FLAGS	0
107 #define DEBUG_TI81XXUART3_FLAGS	0
108 #define DEBUG_AM33XXUART1_FLAGS	0
109 
110 #define DEBUG_OMAPUART_FLAGS	(HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET)
111 
112 #if defined(CONFIG_DEBUG_OMAP2UART1)
113 #undef DEBUG_OMAP2UART1_FLAGS
114 #define DEBUG_OMAP2UART1_FLAGS DEBUG_OMAPUART_FLAGS
115 #elif defined(CONFIG_DEBUG_OMAP2UART2)
116 #undef DEBUG_OMAP2UART2_FLAGS
117 #define DEBUG_OMAP2UART2_FLAGS DEBUG_OMAPUART_FLAGS
118 #elif defined(CONFIG_DEBUG_OMAP2UART3)
119 #undef DEBUG_OMAP2UART3_FLAGS
120 #define DEBUG_OMAP2UART3_FLAGS DEBUG_OMAPUART_FLAGS
121 #elif defined(CONFIG_DEBUG_OMAP3UART3)
122 #undef DEBUG_OMAP3UART3_FLAGS
123 #define DEBUG_OMAP3UART3_FLAGS DEBUG_OMAPUART_FLAGS
124 #elif defined(CONFIG_DEBUG_OMAP3UART4)
125 #undef DEBUG_OMAP3UART4_FLAGS
126 #define DEBUG_OMAP3UART4_FLAGS DEBUG_OMAPUART_FLAGS
127 #elif defined(CONFIG_DEBUG_OMAP4UART3)
128 #undef DEBUG_OMAP4UART3_FLAGS
129 #define DEBUG_OMAP4UART3_FLAGS DEBUG_OMAPUART_FLAGS
130 #elif defined(CONFIG_DEBUG_OMAP4UART4)
131 #undef DEBUG_OMAP4UART4_FLAGS
132 #define DEBUG_OMAP4UART4_FLAGS DEBUG_OMAPUART_FLAGS
133 #elif defined(CONFIG_DEBUG_TI81XXUART1)
134 #undef DEBUG_TI81XXUART1_FLAGS
135 #define DEBUG_TI81XXUART1_FLAGS DEBUG_OMAPUART_FLAGS
136 #elif defined(CONFIG_DEBUG_TI81XXUART2)
137 #undef DEBUG_TI81XXUART2_FLAGS
138 #define DEBUG_TI81XXUART2_FLAGS DEBUG_OMAPUART_FLAGS
139 #elif defined(CONFIG_DEBUG_TI81XXUART3)
140 #undef DEBUG_TI81XXUART3_FLAGS
141 #define DEBUG_TI81XXUART3_FLAGS DEBUG_OMAPUART_FLAGS
142 #elif defined(CONFIG_DEBUG_AM33XXUART1)
143 #undef DEBUG_AM33XXUART1_FLAGS
144 #define DEBUG_AM33XXUART1_FLAGS DEBUG_OMAPUART_FLAGS
145 #endif
146 
147 /**
148  * struct omap_hwmod_mux_info - hwmod specific mux configuration
149  * @pads:              array of omap_device_pad entries
150  * @nr_pads:           number of omap_device_pad entries
151  *
152  * Note that this is currently built during init as needed.
153  */
154 struct omap_hwmod_mux_info {
155 	int				nr_pads;
156 	struct omap_device_pad		*pads;
157 	int				nr_pads_dynamic;
158 	struct omap_device_pad		**pads_dynamic;
159 	int				*irqs;
160 	bool				enabled;
161 };
162 
163 /**
164  * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod
165  * @name: name of the IRQ channel (module local name)
166  * @irq: IRQ channel ID (should be non-negative except -1 = terminator)
167  *
168  * @name should be something short, e.g., "tx" or "rx".  It is for use
169  * by platform_get_resource_byname().  It is defined locally to the
170  * hwmod.
171  */
172 struct omap_hwmod_irq_info {
173 	const char	*name;
174 	s16		irq;
175 };
176 
177 /**
178  * struct omap_hwmod_dma_info - DMA channels used by the hwmod
179  * @name: name of the DMA channel (module local name)
180  * @dma_req: DMA request ID (should be non-negative except -1 = terminator)
181  *
182  * @name should be something short, e.g., "tx" or "rx".  It is for use
183  * by platform_get_resource_byname().  It is defined locally to the
184  * hwmod.
185  */
186 struct omap_hwmod_dma_info {
187 	const char	*name;
188 	s16		dma_req;
189 };
190 
191 /**
192  * struct omap_hwmod_rst_info - IPs reset lines use by hwmod
193  * @name: name of the reset line (module local name)
194  * @rst_shift: Offset of the reset bit
195  * @st_shift: Offset of the reset status bit (OMAP2/3 only)
196  *
197  * @name should be something short, e.g., "cpu0" or "rst". It is defined
198  * locally to the hwmod.
199  */
200 struct omap_hwmod_rst_info {
201 	const char	*name;
202 	u8		rst_shift;
203 	u8		st_shift;
204 };
205 
206 /**
207  * struct omap_hwmod_opt_clk - optional clocks used by this hwmod
208  * @role: "sys", "32k", "tv", etc -- for use in clk_get()
209  * @clk: opt clock: OMAP clock name
210  * @_clk: pointer to the struct clk (filled in at runtime)
211  *
212  * The module's interface clock and main functional clock should not
213  * be added as optional clocks.
214  */
215 struct omap_hwmod_opt_clk {
216 	const char	*role;
217 	const char	*clk;
218 	struct clk	*_clk;
219 };
220 
221 
222 /* omap_hwmod_omap2_firewall.flags bits */
223 #define OMAP_FIREWALL_L3		(1 << 0)
224 #define OMAP_FIREWALL_L4		(1 << 1)
225 
226 /**
227  * struct omap_hwmod_omap2_firewall - OMAP2/3 device firewall data
228  * @l3_perm_bit: bit shift for L3_PM_*_PERMISSION_*
229  * @l4_fw_region: L4 firewall region ID
230  * @l4_prot_group: L4 protection group ID
231  * @flags: (see omap_hwmod_omap2_firewall.flags macros above)
232  */
233 struct omap_hwmod_omap2_firewall {
234 	u8 l3_perm_bit;
235 	u8 l4_fw_region;
236 	u8 l4_prot_group;
237 	u8 flags;
238 };
239 
240 
241 /*
242  * omap_hwmod_addr_space.flags bits
243  *
244  * ADDR_MAP_ON_INIT: Map this address space during omap_hwmod init.
245  * ADDR_TYPE_RT: Address space contains module register target data.
246  */
247 #define ADDR_MAP_ON_INIT	(1 << 0)	/* XXX does not belong */
248 #define ADDR_TYPE_RT		(1 << 1)
249 
250 /**
251  * struct omap_hwmod_addr_space - address space handled by the hwmod
252  * @name: name of the address space
253  * @pa_start: starting physical address
254  * @pa_end: ending physical address
255  * @flags: (see omap_hwmod_addr_space.flags macros above)
256  *
257  * Address space doesn't necessarily follow physical interconnect
258  * structure.  GPMC is one example.
259  */
260 struct omap_hwmod_addr_space {
261 	const char *name;
262 	u32 pa_start;
263 	u32 pa_end;
264 	u8 flags;
265 };
266 
267 
268 /*
269  * omap_hwmod_ocp_if.user bits: these indicate the initiators that use this
270  * interface to interact with the hwmod.  Used to add sleep dependencies
271  * when the module is enabled or disabled.
272  */
273 #define OCP_USER_MPU			(1 << 0)
274 #define OCP_USER_SDMA			(1 << 1)
275 #define OCP_USER_DSP			(1 << 2)
276 #define OCP_USER_IVA			(1 << 3)
277 
278 /* omap_hwmod_ocp_if.flags bits */
279 #define OCPIF_SWSUP_IDLE		(1 << 0)
280 #define OCPIF_CAN_BURST			(1 << 1)
281 
282 /* omap_hwmod_ocp_if._int_flags possibilities */
283 #define _OCPIF_INT_FLAGS_REGISTERED	(1 << 0)
284 
285 
286 /**
287  * struct omap_hwmod_ocp_if - OCP interface data
288  * @master: struct omap_hwmod that initiates OCP transactions on this link
289  * @slave: struct omap_hwmod that responds to OCP transactions on this link
290  * @addr: address space associated with this link
291  * @clk: interface clock: OMAP clock name
292  * @_clk: pointer to the interface struct clk (filled in at runtime)
293  * @fw: interface firewall data
294  * @width: OCP data width
295  * @user: initiators using this interface (see OCP_USER_* macros above)
296  * @flags: OCP interface flags (see OCPIF_* macros above)
297  * @_int_flags: internal flags (see _OCPIF_INT_FLAGS* macros above)
298  *
299  * It may also be useful to add a tag_cnt field for OCP2.x devices.
300  *
301  * Parameter names beginning with an underscore are managed internally by
302  * the omap_hwmod code and should not be set during initialization.
303  */
304 struct omap_hwmod_ocp_if {
305 	struct omap_hwmod		*master;
306 	struct omap_hwmod		*slave;
307 	struct omap_hwmod_addr_space	*addr;
308 	const char			*clk;
309 	struct clk			*_clk;
310 	union {
311 		struct omap_hwmod_omap2_firewall omap2;
312 	}				fw;
313 	u8				width;
314 	u8				user;
315 	u8				flags;
316 	u8				_int_flags;
317 };
318 
319 
320 /* Macros for use in struct omap_hwmod_sysconfig */
321 
322 /* Flags for use in omap_hwmod_sysconfig.idlemodes */
323 #define MASTER_STANDBY_SHIFT	4
324 #define SLAVE_IDLE_SHIFT	0
325 #define SIDLE_FORCE		(HWMOD_IDLEMODE_FORCE << SLAVE_IDLE_SHIFT)
326 #define SIDLE_NO		(HWMOD_IDLEMODE_NO << SLAVE_IDLE_SHIFT)
327 #define SIDLE_SMART		(HWMOD_IDLEMODE_SMART << SLAVE_IDLE_SHIFT)
328 #define SIDLE_SMART_WKUP	(HWMOD_IDLEMODE_SMART_WKUP << SLAVE_IDLE_SHIFT)
329 #define MSTANDBY_FORCE		(HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT)
330 #define MSTANDBY_NO		(HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT)
331 #define MSTANDBY_SMART		(HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT)
332 #define MSTANDBY_SMART_WKUP	(HWMOD_IDLEMODE_SMART_WKUP << MASTER_STANDBY_SHIFT)
333 
334 /* omap_hwmod_sysconfig.sysc_flags capability flags */
335 #define SYSC_HAS_AUTOIDLE	(1 << 0)
336 #define SYSC_HAS_SOFTRESET	(1 << 1)
337 #define SYSC_HAS_ENAWAKEUP	(1 << 2)
338 #define SYSC_HAS_EMUFREE	(1 << 3)
339 #define SYSC_HAS_CLOCKACTIVITY	(1 << 4)
340 #define SYSC_HAS_SIDLEMODE	(1 << 5)
341 #define SYSC_HAS_MIDLEMODE	(1 << 6)
342 #define SYSS_HAS_RESET_STATUS	(1 << 7)
343 #define SYSC_NO_CACHE		(1 << 8)  /* XXX SW flag, belongs elsewhere */
344 #define SYSC_HAS_RESET_STATUS	(1 << 9)
345 #define SYSC_HAS_DMADISABLE	(1 << 10)
346 
347 /* omap_hwmod_sysconfig.clockact flags */
348 #define CLOCKACT_TEST_BOTH	0x0
349 #define CLOCKACT_TEST_MAIN	0x1
350 #define CLOCKACT_TEST_ICLK	0x2
351 #define CLOCKACT_TEST_NONE	0x3
352 
353 /**
354  * struct omap_hwmod_sysc_fields - hwmod OCP_SYSCONFIG register field offsets.
355  * @midle_shift: Offset of the midle bit
356  * @clkact_shift: Offset of the clockactivity bit
357  * @sidle_shift: Offset of the sidle bit
358  * @enwkup_shift: Offset of the enawakeup bit
359  * @srst_shift: Offset of the softreset bit
360  * @autoidle_shift: Offset of the autoidle bit
361  * @dmadisable_shift: Offset of the dmadisable bit
362  */
363 struct omap_hwmod_sysc_fields {
364 	u8 midle_shift;
365 	u8 clkact_shift;
366 	u8 sidle_shift;
367 	u8 enwkup_shift;
368 	u8 srst_shift;
369 	u8 autoidle_shift;
370 	u8 dmadisable_shift;
371 };
372 
373 /**
374  * struct omap_hwmod_class_sysconfig - hwmod class OCP_SYS* data
375  * @rev_offs: IP block revision register offset (from module base addr)
376  * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr)
377  * @syss_offs: OCP_SYSSTATUS register offset (from module base addr)
378  * @srst_udelay: Delay needed after doing a softreset in usecs
379  * @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART}
380  * @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported
381  * @clockact: the default value of the module CLOCKACTIVITY bits
382  *
383  * @clockact describes to the module which clocks are likely to be
384  * disabled when the PRCM issues its idle request to the module.  Some
385  * modules have separate clockdomains for the interface clock and main
386  * functional clock, and can check whether they should acknowledge the
387  * idle request based on the internal module functionality that has
388  * been associated with the clocks marked in @clockact.  This field is
389  * only used if HWMOD_SET_DEFAULT_CLOCKACT is set (see below)
390  *
391  * @sysc_fields: structure containing the offset positions of various bits in
392  * SYSCONFIG register. This can be populated using omap_hwmod_sysc_type1 or
393  * omap_hwmod_sysc_type2 defined in omap_hwmod_common_data.c depending on
394  * whether the device ip is compliant with the original PRCM protocol
395  * defined for OMAP2420 or the new PRCM protocol for new OMAP4 IPs.
396  * If the device follows a different scheme for the sysconfig register ,
397  * then this field has to be populated with the correct offset structure.
398  */
399 struct omap_hwmod_class_sysconfig {
400 	u32 rev_offs;
401 	u32 sysc_offs;
402 	u32 syss_offs;
403 	u16 sysc_flags;
404 	struct omap_hwmod_sysc_fields *sysc_fields;
405 	u8 srst_udelay;
406 	u8 idlemodes;
407 	u8 clockact;
408 };
409 
410 /**
411  * struct omap_hwmod_omap2_prcm - OMAP2/3-specific PRCM data
412  * @module_offs: PRCM submodule offset from the start of the PRM/CM
413  * @prcm_reg_id: PRCM register ID (e.g., 3 for CM_AUTOIDLE3)
414  * @module_bit: register bit shift for AUTOIDLE, WKST, WKEN, GRPSEL regs
415  * @idlest_reg_id: IDLEST register ID (e.g., 3 for CM_IDLEST3)
416  * @idlest_idle_bit: register bit shift for CM_IDLEST slave idle bit
417  * @idlest_stdby_bit: register bit shift for CM_IDLEST master standby bit
418  *
419  * @prcm_reg_id and @module_bit are specific to the AUTOIDLE, WKST,
420  * WKEN, GRPSEL registers.  In an ideal world, no extra information
421  * would be needed for IDLEST information, but alas, there are some
422  * exceptions, so @idlest_reg_id, @idlest_idle_bit, @idlest_stdby_bit
423  * are needed for the IDLEST registers (c.f. 2430 I2CHS, 3430 USBHOST)
424  */
425 struct omap_hwmod_omap2_prcm {
426 	s16 module_offs;
427 	u8 prcm_reg_id;
428 	u8 module_bit;
429 	u8 idlest_reg_id;
430 	u8 idlest_idle_bit;
431 	u8 idlest_stdby_bit;
432 };
433 
434 /*
435  * Possible values for struct omap_hwmod_omap4_prcm.flags
436  *
437  * HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT: Some IP blocks don't have a PRCM
438  *     module-level context loss register associated with them; this
439  *     flag bit should be set in those cases
440  */
441 #define HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT		(1 << 0)
442 
443 /**
444  * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
445  * @clkctrl_offs: offset of the PRCM clock control register
446  * @rstctrl_offs: offset of the XXX_RSTCTRL register located in the PRM
447  * @context_offs: offset of the RM_*_CONTEXT register
448  * @lostcontext_mask: bitmask for selecting bits from RM_*_CONTEXT register
449  * @rstst_reg: (AM33XX only) address of the XXX_RSTST register in the PRM
450  * @submodule_wkdep_bit: bit shift of the WKDEP range
451  * @flags: PRCM register capabilities for this IP block
452  * @modulemode: allowable modulemodes
453  * @context_lost_counter: Count of module level context lost
454  *
455  * If @lostcontext_mask is not defined, context loss check code uses
456  * whole register without masking. @lostcontext_mask should only be
457  * defined in cases where @context_offs register is shared by two or
458  * more hwmods.
459  */
460 struct omap_hwmod_omap4_prcm {
461 	u16		clkctrl_offs;
462 	u16		rstctrl_offs;
463 	u16		rstst_offs;
464 	u16		context_offs;
465 	u32		lostcontext_mask;
466 	u8		submodule_wkdep_bit;
467 	u8		modulemode;
468 	u8		flags;
469 	int		context_lost_counter;
470 };
471 
472 
473 /*
474  * omap_hwmod.flags definitions
475  *
476  * HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out
477  *     of idle, rather than relying on module smart-idle
478  * HWMOD_SWSUP_MSTANDBY: omap_hwmod code should manually bring module in and
479  *     out of standby, rather than relying on module smart-standby
480  * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for
481  *     SDRAM controller, etc. XXX probably belongs outside the main hwmod file
482  *     XXX Should be HWMOD_SETUP_NO_RESET
483  * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM
484  *     controller, etc. XXX probably belongs outside the main hwmod file
485  *     XXX Should be HWMOD_SETUP_NO_IDLE
486  * HWMOD_NO_OCP_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE)
487  *     when module is enabled, rather than the default, which is to
488  *     enable autoidle
489  * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup
490  * HWMOD_NO_IDLEST: this module does not have idle status - this is the case
491  *     only for few initiator modules on OMAP2 & 3.
492  * HWMOD_CONTROL_OPT_CLKS_IN_RESET: Enable all optional clocks during reset.
493  *     This is needed for devices like DSS that require optional clocks enabled
494  *     in order to complete the reset. Optional clocks will be disabled
495  *     again after the reset.
496  * HWMOD_16BIT_REG: Module has 16bit registers
497  * HWMOD_EXT_OPT_MAIN_CLK: The only main functional clock source for
498  *     this IP block comes from an off-chip source and is not always
499  *     enabled.  This prevents the hwmod code from being able to
500  *     enable and reset the IP block early.  XXX Eventually it should
501  *     be possible to query the clock framework for this information.
502  * HWMOD_BLOCK_WFI: Some OMAP peripherals apparently don't work
503  *     correctly if the MPU is allowed to go idle while the
504  *     peripherals are active.  This is apparently true for the I2C on
505  *     OMAP2420, and also the EMAC on AM3517/3505.  It's unlikely that
506  *     this is really true -- we're probably not configuring something
507  *     correctly, or this is being abused to deal with some PM latency
508  *     issues -- but we're currently suffering from a shortage of
509  *     folks who are able to track these issues down properly.
510  * HWMOD_FORCE_MSTANDBY: Always keep MIDLEMODE bits cleared so that device
511  *     is kept in force-standby mode. Failing to do so causes PM problems
512  *     with musb on OMAP3630 at least. Note that musb has a dedicated register
513  *     to control MSTANDBY signal when MIDLEMODE is set to force-standby.
514  * HWMOD_SWSUP_SIDLE_ACT: omap_hwmod code should manually bring the module
515  *     out of idle, but rely on smart-idle to the put it back in idle,
516  *     so the wakeups are still functional (Only known case for now is UART)
517  * HWMOD_RECONFIG_IO_CHAIN: omap_hwmod code needs to reconfigure wake-up
518  *     events by calling _reconfigure_io_chain() when a device is enabled
519  *     or idled.
520  */
521 #define HWMOD_SWSUP_SIDLE			(1 << 0)
522 #define HWMOD_SWSUP_MSTANDBY			(1 << 1)
523 #define HWMOD_INIT_NO_RESET			(1 << 2)
524 #define HWMOD_INIT_NO_IDLE			(1 << 3)
525 #define HWMOD_NO_OCP_AUTOIDLE			(1 << 4)
526 #define HWMOD_SET_DEFAULT_CLOCKACT		(1 << 5)
527 #define HWMOD_NO_IDLEST				(1 << 6)
528 #define HWMOD_CONTROL_OPT_CLKS_IN_RESET		(1 << 7)
529 #define HWMOD_16BIT_REG				(1 << 8)
530 #define HWMOD_EXT_OPT_MAIN_CLK			(1 << 9)
531 #define HWMOD_BLOCK_WFI				(1 << 10)
532 #define HWMOD_FORCE_MSTANDBY			(1 << 11)
533 #define HWMOD_SWSUP_SIDLE_ACT			(1 << 12)
534 #define HWMOD_RECONFIG_IO_CHAIN			(1 << 13)
535 
536 /*
537  * omap_hwmod._int_flags definitions
538  * These are for internal use only and are managed by the omap_hwmod code.
539  *
540  * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module
541  * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached
542  * _HWMOD_SKIP_ENABLE: set if hwmod enabled during init (HWMOD_INIT_NO_IDLE) -
543  *     causes the first call to _enable() to only update the pinmux
544  */
545 #define _HWMOD_NO_MPU_PORT			(1 << 0)
546 #define _HWMOD_SYSCONFIG_LOADED			(1 << 1)
547 #define _HWMOD_SKIP_ENABLE			(1 << 2)
548 
549 /*
550  * omap_hwmod._state definitions
551  *
552  * INITIALIZED: reset (optionally), initialized, enabled, disabled
553  *              (optionally)
554  *
555  *
556  */
557 #define _HWMOD_STATE_UNKNOWN			0
558 #define _HWMOD_STATE_REGISTERED			1
559 #define _HWMOD_STATE_CLKS_INITED		2
560 #define _HWMOD_STATE_INITIALIZED		3
561 #define _HWMOD_STATE_ENABLED			4
562 #define _HWMOD_STATE_IDLE			5
563 #define _HWMOD_STATE_DISABLED			6
564 
565 /**
566  * struct omap_hwmod_class - the type of an IP block
567  * @name: name of the hwmod_class
568  * @sysc: device SYSCONFIG/SYSSTATUS register data
569  * @rev: revision of the IP class
570  * @pre_shutdown: ptr to fn to be executed immediately prior to device shutdown
571  * @reset: ptr to fn to be executed in place of the standard hwmod reset fn
572  * @enable_preprogram:  ptr to fn to be executed during device enable
573  *
574  * Represent the class of a OMAP hardware "modules" (e.g. timer,
575  * smartreflex, gpio, uart...)
576  *
577  * @pre_shutdown is a function that will be run immediately before
578  * hwmod clocks are disabled, etc.  It is intended for use for hwmods
579  * like the MPU watchdog, which cannot be disabled with the standard
580  * omap_hwmod_shutdown().  The function should return 0 upon success,
581  * or some negative error upon failure.  Returning an error will cause
582  * omap_hwmod_shutdown() to abort the device shutdown and return an
583  * error.
584  *
585  * If @reset is defined, then the function it points to will be
586  * executed in place of the standard hwmod _reset() code in
587  * mach-omap2/omap_hwmod.c.  This is needed for IP blocks which have
588  * unusual reset sequences - usually processor IP blocks like the IVA.
589  */
590 struct omap_hwmod_class {
591 	const char				*name;
592 	struct omap_hwmod_class_sysconfig	*sysc;
593 	u32					rev;
594 	int					(*pre_shutdown)(struct omap_hwmod *oh);
595 	int					(*reset)(struct omap_hwmod *oh);
596 	int					(*enable_preprogram)(struct omap_hwmod *oh);
597 };
598 
599 /**
600  * struct omap_hwmod_link - internal structure linking hwmods with ocp_ifs
601  * @ocp_if: OCP interface structure record pointer
602  * @node: list_head pointing to next struct omap_hwmod_link in a list
603  */
604 struct omap_hwmod_link {
605 	struct omap_hwmod_ocp_if	*ocp_if;
606 	struct list_head		node;
607 };
608 
609 /**
610  * struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks)
611  * @name: name of the hwmod
612  * @class: struct omap_hwmod_class * to the class of this hwmod
613  * @od: struct omap_device currently associated with this hwmod (internal use)
614  * @mpu_irqs: ptr to an array of MPU IRQs
615  * @sdma_reqs: ptr to an array of System DMA request IDs
616  * @prcm: PRCM data pertaining to this hwmod
617  * @main_clk: main clock: OMAP clock name
618  * @_clk: pointer to the main struct clk (filled in at runtime)
619  * @opt_clks: other device clocks that drivers can request (0..*)
620  * @voltdm: pointer to voltage domain (filled in at runtime)
621  * @dev_attr: arbitrary device attributes that can be passed to the driver
622  * @_sysc_cache: internal-use hwmod flags
623  * @mpu_rt_idx: index of device address space for register target (for DT boot)
624  * @_mpu_rt_va: cached register target start address (internal use)
625  * @_mpu_port: cached MPU register target slave (internal use)
626  * @opt_clks_cnt: number of @opt_clks
627  * @master_cnt: number of @master entries
628  * @slaves_cnt: number of @slave entries
629  * @response_lat: device OCP response latency (in interface clock cycles)
630  * @_int_flags: internal-use hwmod flags
631  * @_state: internal-use hwmod state
632  * @_postsetup_state: internal-use state to leave the hwmod in after _setup()
633  * @flags: hwmod flags (documented below)
634  * @_lock: spinlock serializing operations on this hwmod
635  * @node: list node for hwmod list (internal use)
636  * @parent_hwmod: (temporary) a pointer to the hierarchical parent of this hwmod
637  *
638  * @main_clk refers to this module's "main clock," which for our
639  * purposes is defined as "the functional clock needed for register
640  * accesses to complete."  Modules may not have a main clock if the
641  * interface clock also serves as a main clock.
642  *
643  * Parameter names beginning with an underscore are managed internally by
644  * the omap_hwmod code and should not be set during initialization.
645  *
646  * @masters and @slaves are now deprecated.
647  *
648  * @parent_hwmod is temporary; there should be no need for it, as this
649  * information should already be expressed in the OCP interface
650  * structures.  @parent_hwmod is present as a workaround until we improve
651  * handling for hwmods with multiple parents (e.g., OMAP4+ DSS with
652  * multiple register targets across different interconnects).
653  */
654 struct omap_hwmod {
655 	const char			*name;
656 	struct omap_hwmod_class		*class;
657 	struct omap_device		*od;
658 	struct omap_hwmod_mux_info	*mux;
659 	struct omap_hwmod_irq_info	*mpu_irqs;
660 	struct omap_hwmod_dma_info	*sdma_reqs;
661 	struct omap_hwmod_rst_info	*rst_lines;
662 	union {
663 		struct omap_hwmod_omap2_prcm omap2;
664 		struct omap_hwmod_omap4_prcm omap4;
665 	}				prcm;
666 	const char			*main_clk;
667 	struct clk			*_clk;
668 	struct omap_hwmod_opt_clk	*opt_clks;
669 	char				*clkdm_name;
670 	struct clockdomain		*clkdm;
671 	struct list_head		master_ports; /* connect to *_IA */
672 	struct list_head		slave_ports; /* connect to *_TA */
673 	void				*dev_attr;
674 	u32				_sysc_cache;
675 	void __iomem			*_mpu_rt_va;
676 	spinlock_t			_lock;
677 	struct list_head		node;
678 	struct omap_hwmod_ocp_if	*_mpu_port;
679 	unsigned int			(*xlate_irq)(unsigned int);
680 	u16				flags;
681 	u8				mpu_rt_idx;
682 	u8				response_lat;
683 	u8				rst_lines_cnt;
684 	u8				opt_clks_cnt;
685 	u8				masters_cnt;
686 	u8				slaves_cnt;
687 	u8				hwmods_cnt;
688 	u8				_int_flags;
689 	u8				_state;
690 	u8				_postsetup_state;
691 	struct omap_hwmod		*parent_hwmod;
692 };
693 
694 struct omap_hwmod *omap_hwmod_lookup(const char *name);
695 int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
696 			void *data);
697 
698 int __init omap_hwmod_setup_one(const char *name);
699 
700 int omap_hwmod_enable(struct omap_hwmod *oh);
701 int omap_hwmod_idle(struct omap_hwmod *oh);
702 int omap_hwmod_shutdown(struct omap_hwmod *oh);
703 
704 int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name);
705 int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name);
706 int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name);
707 
708 int omap_hwmod_enable_clocks(struct omap_hwmod *oh);
709 int omap_hwmod_disable_clocks(struct omap_hwmod *oh);
710 
711 int omap_hwmod_reset(struct omap_hwmod *oh);
712 void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
713 
714 void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs);
715 u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs);
716 int omap_hwmod_softreset(struct omap_hwmod *oh);
717 
718 int omap_hwmod_count_resources(struct omap_hwmod *oh, unsigned long flags);
719 int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
720 int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res);
721 int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type,
722 				   const char *name, struct resource *res);
723 
724 struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh);
725 void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh);
726 
727 int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh,
728 				 struct omap_hwmod *init_oh);
729 int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
730 				 struct omap_hwmod *init_oh);
731 
732 int omap_hwmod_enable_wakeup(struct omap_hwmod *oh);
733 int omap_hwmod_disable_wakeup(struct omap_hwmod *oh);
734 
735 int omap_hwmod_for_each_by_class(const char *classname,
736 				 int (*fn)(struct omap_hwmod *oh,
737 					   void *user),
738 				 void *user);
739 
740 int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state);
741 int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh);
742 
743 int omap_hwmod_no_setup_reset(struct omap_hwmod *oh);
744 
745 int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx);
746 
747 extern void __init omap_hwmod_init(void);
748 
749 const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh);
750 
751 /*
752  *
753  */
754 
755 extern int omap_hwmod_aess_preprogram(struct omap_hwmod *oh);
756 
757 /*
758  * Chip variant-specific hwmod init routines - XXX should be converted
759  * to use initcalls once the initial boot ordering is straightened out
760  */
761 extern int omap2420_hwmod_init(void);
762 extern int omap2430_hwmod_init(void);
763 extern int omap3xxx_hwmod_init(void);
764 extern int omap44xx_hwmod_init(void);
765 extern int omap54xx_hwmod_init(void);
766 extern int am33xx_hwmod_init(void);
767 extern int dra7xx_hwmod_init(void);
768 int am43xx_hwmod_init(void);
769 
770 extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
771 
772 #endif
773