1501f0c75SSantosh Shilimkar /* 2501f0c75SSantosh Shilimkar * omap4-sar-layout.h: OMAP4 SAR RAM layout header file 3501f0c75SSantosh Shilimkar * 4501f0c75SSantosh Shilimkar * Copyright (C) 2011 Texas Instruments, Inc. 5501f0c75SSantosh Shilimkar * Santosh Shilimkar <santosh.shilimkar@ti.com> 6501f0c75SSantosh Shilimkar * 7501f0c75SSantosh Shilimkar * This program is free software; you can redistribute it and/or modify 8501f0c75SSantosh Shilimkar * it under the terms of the GNU General Public License version 2 as 9501f0c75SSantosh Shilimkar * published by the Free Software Foundation. 10501f0c75SSantosh Shilimkar */ 11501f0c75SSantosh Shilimkar #ifndef OMAP_ARCH_OMAP4_SAR_LAYOUT_H 12501f0c75SSantosh Shilimkar #define OMAP_ARCH_OMAP4_SAR_LAYOUT_H 13501f0c75SSantosh Shilimkar 14501f0c75SSantosh Shilimkar /* 15247c445cSSantosh Shilimkar * SAR BANK offsets from base address OMAP44XX/54XX_SAR_RAM_BASE 16501f0c75SSantosh Shilimkar */ 17501f0c75SSantosh Shilimkar #define SAR_BANK1_OFFSET 0x0000 18501f0c75SSantosh Shilimkar #define SAR_BANK2_OFFSET 0x1000 19501f0c75SSantosh Shilimkar #define SAR_BANK3_OFFSET 0x2000 20501f0c75SSantosh Shilimkar #define SAR_BANK4_OFFSET 0x3000 21501f0c75SSantosh Shilimkar 22b2b9762fSSantosh Shilimkar /* Scratch pad memory offsets from SAR_BANK1 */ 23f98d5fe8STero Kristo #define SCU_OFFSET0 0xfe4 24f98d5fe8STero Kristo #define SCU_OFFSET1 0xfe8 25f98d5fe8STero Kristo #define OMAP_TYPE_OFFSET 0xfec 26f98d5fe8STero Kristo #define L2X0_SAVE_OFFSET0 0xff0 27f98d5fe8STero Kristo #define L2X0_SAVE_OFFSET1 0xff4 28f98d5fe8STero Kristo #define L2X0_AUXCTRL_OFFSET 0xff8 29f98d5fe8STero Kristo #define L2X0_PREFETCH_CTRL_OFFSET 0xffc 30b2b9762fSSantosh Shilimkar 31e33509c1STony Lindgren /* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK1 */ 32b2b9762fSSantosh Shilimkar #define CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xa04 33b2b9762fSSantosh Shilimkar #define CPU1_WAKEUP_NS_PA_ADDR_OFFSET 0xa08 348a8be46aSTony Lindgren #define OMAP5_CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xe00 358a8be46aSTony Lindgren #define OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET 0xe04 36b2b9762fSSantosh Shilimkar 370f3cf2ecSSantosh Shilimkar #define SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x500) 380f3cf2ecSSantosh Shilimkar #define SAR_SECURE_RAM_SIZE_OFFSET (SAR_BANK3_OFFSET + 0x504) 390f3cf2ecSSantosh Shilimkar #define SAR_SECRAM_SAVED_AT_OFFSET (SAR_BANK3_OFFSET + 0x508) 400f3cf2ecSSantosh Shilimkar 410f3cf2ecSSantosh Shilimkar /* WakeUpGen save restore offset from OMAP44XX_SAR_RAM_BASE */ 420f3cf2ecSSantosh Shilimkar #define WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x684) 430f3cf2ecSSantosh Shilimkar #define WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x694) 440f3cf2ecSSantosh Shilimkar #define WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x6a4) 450f3cf2ecSSantosh Shilimkar #define WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x6b4) 460f3cf2ecSSantosh Shilimkar #define AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0x6c4) 470f3cf2ecSSantosh Shilimkar #define AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x6c8) 480f3cf2ecSSantosh Shilimkar #define PTMSYNCREQ_MASK_OFFSET (SAR_BANK3_OFFSET + 0x6cc) 490f3cf2ecSSantosh Shilimkar #define PTMSYNCREQ_EN_OFFSET (SAR_BANK3_OFFSET + 0x6d0) 500f3cf2ecSSantosh Shilimkar #define SAR_BACKUP_STATUS_WAKEUPGEN 0x10 510f3cf2ecSSantosh Shilimkar 52247c445cSSantosh Shilimkar /* WakeUpGen save restore offset from OMAP54XX_SAR_RAM_BASE */ 5313fcef94SSantosh Shilimkar #define OMAP5_WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x9dc) 5413fcef94SSantosh Shilimkar #define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x9f0) 5513fcef94SSantosh Shilimkar #define OMAP5_WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0xa04) 5613fcef94SSantosh Shilimkar #define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0xa18) 5713fcef94SSantosh Shilimkar #define OMAP5_AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0xa2c) 5813fcef94SSantosh Shilimkar #define OMAP5_AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x930) 5913fcef94SSantosh Shilimkar #define OMAP5_AMBA_IF_MODE_OFFSET (SAR_BANK3_OFFSET + 0xa34) 60247c445cSSantosh Shilimkar #define OMAP5_SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x800) 61247c445cSSantosh Shilimkar 62501f0c75SSantosh Shilimkar #endif 63