1501f0c75SSantosh Shilimkar /* 2501f0c75SSantosh Shilimkar * omap4-sar-layout.h: OMAP4 SAR RAM layout header file 3501f0c75SSantosh Shilimkar * 4501f0c75SSantosh Shilimkar * Copyright (C) 2011 Texas Instruments, Inc. 5501f0c75SSantosh Shilimkar * Santosh Shilimkar <santosh.shilimkar@ti.com> 6501f0c75SSantosh Shilimkar * 7501f0c75SSantosh Shilimkar * This program is free software; you can redistribute it and/or modify 8501f0c75SSantosh Shilimkar * it under the terms of the GNU General Public License version 2 as 9501f0c75SSantosh Shilimkar * published by the Free Software Foundation. 10501f0c75SSantosh Shilimkar */ 11501f0c75SSantosh Shilimkar #ifndef OMAP_ARCH_OMAP4_SAR_LAYOUT_H 12501f0c75SSantosh Shilimkar #define OMAP_ARCH_OMAP4_SAR_LAYOUT_H 13501f0c75SSantosh Shilimkar 14501f0c75SSantosh Shilimkar /* 15501f0c75SSantosh Shilimkar * SAR BANK offsets from base address OMAP44XX_SAR_RAM_BASE 16501f0c75SSantosh Shilimkar */ 17501f0c75SSantosh Shilimkar #define SAR_BANK1_OFFSET 0x0000 18501f0c75SSantosh Shilimkar #define SAR_BANK2_OFFSET 0x1000 19501f0c75SSantosh Shilimkar #define SAR_BANK3_OFFSET 0x2000 20501f0c75SSantosh Shilimkar #define SAR_BANK4_OFFSET 0x3000 21501f0c75SSantosh Shilimkar 22b2b9762fSSantosh Shilimkar /* Scratch pad memory offsets from SAR_BANK1 */ 23b2b9762fSSantosh Shilimkar #define SCU_OFFSET0 0xd00 24b2b9762fSSantosh Shilimkar #define SCU_OFFSET1 0xd04 25b2b9762fSSantosh Shilimkar #define OMAP_TYPE_OFFSET 0xd10 26b2b9762fSSantosh Shilimkar 27b2b9762fSSantosh Shilimkar /* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK3 */ 28b2b9762fSSantosh Shilimkar #define CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xa04 29b2b9762fSSantosh Shilimkar #define CPU1_WAKEUP_NS_PA_ADDR_OFFSET 0xa08 30b2b9762fSSantosh Shilimkar 310f3cf2ecSSantosh Shilimkar #define SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x500) 320f3cf2ecSSantosh Shilimkar #define SAR_SECURE_RAM_SIZE_OFFSET (SAR_BANK3_OFFSET + 0x504) 330f3cf2ecSSantosh Shilimkar #define SAR_SECRAM_SAVED_AT_OFFSET (SAR_BANK3_OFFSET + 0x508) 340f3cf2ecSSantosh Shilimkar 350f3cf2ecSSantosh Shilimkar /* WakeUpGen save restore offset from OMAP44XX_SAR_RAM_BASE */ 360f3cf2ecSSantosh Shilimkar #define WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x684) 370f3cf2ecSSantosh Shilimkar #define WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x694) 380f3cf2ecSSantosh Shilimkar #define WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x6a4) 390f3cf2ecSSantosh Shilimkar #define WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x6b4) 400f3cf2ecSSantosh Shilimkar #define AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0x6c4) 410f3cf2ecSSantosh Shilimkar #define AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x6c8) 420f3cf2ecSSantosh Shilimkar #define PTMSYNCREQ_MASK_OFFSET (SAR_BANK3_OFFSET + 0x6cc) 430f3cf2ecSSantosh Shilimkar #define PTMSYNCREQ_EN_OFFSET (SAR_BANK3_OFFSET + 0x6d0) 440f3cf2ecSSantosh Shilimkar #define SAR_BACKUP_STATUS_WAKEUPGEN 0x10 450f3cf2ecSSantosh Shilimkar 46501f0c75SSantosh Shilimkar #endif 47