1 /* 2 * OMAP4 SMP source file. It contains platform specific fucntions 3 * needed for the linux smp kernel. 4 * 5 * Copyright (C) 2009 Texas Instruments, Inc. 6 * 7 * Author: 8 * Santosh Shilimkar <santosh.shilimkar@ti.com> 9 * 10 * Platform file needed for the OMAP4 SMP. This file is based on arm 11 * realview smp platform. 12 * * Copyright (c) 2002 ARM Limited. 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License version 2 as 16 * published by the Free Software Foundation. 17 */ 18 #include <linux/init.h> 19 #include <linux/device.h> 20 #include <linux/jiffies.h> 21 #include <linux/smp.h> 22 #include <linux/io.h> 23 24 #include <asm/localtimer.h> 25 #include <asm/smp_scu.h> 26 #include <mach/hardware.h> 27 28 /* Registers used for communicating startup information */ 29 #define OMAP4_AUXCOREBOOT_REG0 (OMAP44XX_VA_WKUPGEN_BASE + 0x800) 30 #define OMAP4_AUXCOREBOOT_REG1 (OMAP44XX_VA_WKUPGEN_BASE + 0x804) 31 32 /* SCU base address */ 33 static void __iomem *scu_base = OMAP44XX_VA_SCU_BASE; 34 35 /* 36 * Use SCU config register to count number of cores 37 */ 38 static inline unsigned int get_core_count(void) 39 { 40 if (scu_base) 41 return scu_get_core_count(scu_base); 42 return 1; 43 } 44 45 static DEFINE_SPINLOCK(boot_lock); 46 47 void __cpuinit platform_secondary_init(unsigned int cpu) 48 { 49 trace_hardirqs_off(); 50 51 /* 52 * If any interrupts are already enabled for the primary 53 * core (e.g. timer irq), then they will not have been enabled 54 * for us: do so 55 */ 56 57 gic_cpu_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)); 58 59 /* 60 * Synchronise with the boot thread. 61 */ 62 spin_lock(&boot_lock); 63 spin_unlock(&boot_lock); 64 } 65 66 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) 67 { 68 unsigned long timeout; 69 70 /* 71 * Set synchronisation state between this boot processor 72 * and the secondary one 73 */ 74 spin_lock(&boot_lock); 75 76 /* 77 * Update the AuxCoreBoot1 with boot state for secondary core. 78 * omap_secondary_startup() routine will hold the secondary core till 79 * the AuxCoreBoot1 register is updated with cpu state 80 * A barrier is added to ensure that write buffer is drained 81 */ 82 __raw_writel(cpu, OMAP4_AUXCOREBOOT_REG1); 83 smp_wmb(); 84 85 timeout = jiffies + (1 * HZ); 86 while (time_before(jiffies, timeout)) 87 ; 88 89 /* 90 * Now the secondary core is starting up let it run its 91 * calibrations, then wait for it to finish 92 */ 93 spin_unlock(&boot_lock); 94 95 return 0; 96 } 97 98 static void __init wakeup_secondary(void) 99 { 100 /* 101 * Write the address of secondary startup routine into the 102 * AuxCoreBoot0 where ROM code will jump and start executing 103 * on secondary core once out of WFE 104 * A barrier is added to ensure that write buffer is drained 105 */ 106 __raw_writel(virt_to_phys(omap_secondary_startup), \ 107 OMAP4_AUXCOREBOOT_REG0); 108 smp_wmb(); 109 110 /* 111 * Send a 'sev' to wake the secondary core from WFE. 112 */ 113 set_event(); 114 mb(); 115 } 116 117 /* 118 * Initialise the CPU possible map early - this describes the CPUs 119 * which may be present or become present in the system. 120 */ 121 void __init smp_init_cpus(void) 122 { 123 unsigned int i, ncores = get_core_count(); 124 125 for (i = 0; i < ncores; i++) 126 set_cpu_possible(i, true); 127 } 128 129 void __init smp_prepare_cpus(unsigned int max_cpus) 130 { 131 unsigned int ncores = get_core_count(); 132 unsigned int cpu = smp_processor_id(); 133 int i; 134 135 /* sanity check */ 136 if (ncores == 0) { 137 printk(KERN_ERR 138 "OMAP4: strange core count of 0? Default to 1\n"); 139 ncores = 1; 140 } 141 142 if (ncores > NR_CPUS) { 143 printk(KERN_WARNING 144 "OMAP4: no. of cores (%d) greater than configured " 145 "maximum of %d - clipping\n", 146 ncores, NR_CPUS); 147 ncores = NR_CPUS; 148 } 149 smp_store_cpu_info(cpu); 150 151 /* 152 * are we trying to boot more cores than exist? 153 */ 154 if (max_cpus > ncores) 155 max_cpus = ncores; 156 157 /* 158 * Initialise the present map, which describes the set of CPUs 159 * actually populated at the present time. 160 */ 161 for (i = 0; i < max_cpus; i++) 162 set_cpu_present(i, true); 163 164 if (max_cpus > 1) { 165 /* 166 * Enable the local timer or broadcast device for the 167 * boot CPU, but only if we have more than one CPU. 168 */ 169 percpu_timer_setup(); 170 171 /* 172 * Initialise the SCU and wake up the secondary core using 173 * wakeup_secondary(). 174 */ 175 scu_enable(scu_base); 176 wakeup_secondary(); 177 } 178 } 179