1 /* 2 * OMAP4 SMP source file. It contains platform specific fucntions 3 * needed for the linux smp kernel. 4 * 5 * Copyright (C) 2009 Texas Instruments, Inc. 6 * 7 * Author: 8 * Santosh Shilimkar <santosh.shilimkar@ti.com> 9 * 10 * Platform file needed for the OMAP4 SMP. This file is based on arm 11 * realview smp platform. 12 * * Copyright (c) 2002 ARM Limited. 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License version 2 as 16 * published by the Free Software Foundation. 17 */ 18 #include <linux/init.h> 19 #include <linux/device.h> 20 #include <linux/smp.h> 21 #include <linux/io.h> 22 #include <linux/irqchip/arm-gic.h> 23 24 #include <asm/smp_scu.h> 25 26 #include "omap-secure.h" 27 #include "omap-wakeupgen.h" 28 #include <asm/cputype.h> 29 30 #include "soc.h" 31 #include "iomap.h" 32 #include "common.h" 33 #include "clockdomain.h" 34 #include "pm.h" 35 36 #define CPU_MASK 0xff0ffff0 37 #define CPU_CORTEX_A9 0x410FC090 38 #define CPU_CORTEX_A15 0x410FC0F0 39 40 #define OMAP5_CORE_COUNT 0x2 41 42 u16 pm44xx_errata; 43 44 /* SCU base address */ 45 static void __iomem *scu_base; 46 47 static DEFINE_SPINLOCK(boot_lock); 48 49 void __iomem *omap4_get_scu_base(void) 50 { 51 return scu_base; 52 } 53 54 static void omap4_secondary_init(unsigned int cpu) 55 { 56 /* 57 * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device. 58 * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA 59 * init and for CPU1, a secure PPA API provided. CPU0 must be ON 60 * while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+. 61 * OMAP443X GP devices- SMP bit isn't accessible. 62 * OMAP446X GP devices - SMP bit access is enabled on both CPUs. 63 */ 64 if (cpu_is_omap443x() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) 65 omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX, 66 4, 0, 0, 0, 0, 0); 67 68 /* 69 * Synchronise with the boot thread. 70 */ 71 spin_lock(&boot_lock); 72 spin_unlock(&boot_lock); 73 } 74 75 static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle) 76 { 77 static struct clockdomain *cpu1_clkdm; 78 static bool booted; 79 static struct powerdomain *cpu1_pwrdm; 80 void __iomem *base = omap_get_wakeupgen_base(); 81 82 /* 83 * Set synchronisation state between this boot processor 84 * and the secondary one 85 */ 86 spin_lock(&boot_lock); 87 88 /* 89 * Update the AuxCoreBoot0 with boot state for secondary core. 90 * omap4_secondary_startup() routine will hold the secondary core till 91 * the AuxCoreBoot1 register is updated with cpu state 92 * A barrier is added to ensure that write buffer is drained 93 */ 94 if (omap_secure_apis_support()) 95 omap_modify_auxcoreboot0(0x200, 0xfffffdff); 96 else 97 __raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0); 98 99 if (!cpu1_clkdm && !cpu1_pwrdm) { 100 cpu1_clkdm = clkdm_lookup("mpu1_clkdm"); 101 cpu1_pwrdm = pwrdm_lookup("cpu1_pwrdm"); 102 } 103 104 /* 105 * The SGI(Software Generated Interrupts) are not wakeup capable 106 * from low power states. This is known limitation on OMAP4 and 107 * needs to be worked around by using software forced clockdomain 108 * wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to 109 * software force wakeup. The clockdomain is then put back to 110 * hardware supervised mode. 111 * More details can be found in OMAP4430 TRM - Version J 112 * Section : 113 * 4.3.4.2 Power States of CPU0 and CPU1 114 */ 115 if (booted && cpu1_pwrdm && cpu1_clkdm) { 116 /* 117 * GIC distributor control register has changed between 118 * CortexA9 r1pX and r2pX. The Control Register secure 119 * banked version is now composed of 2 bits: 120 * bit 0 == Secure Enable 121 * bit 1 == Non-Secure Enable 122 * The Non-Secure banked register has not changed 123 * Because the ROM Code is based on the r1pX GIC, the CPU1 124 * GIC restoration will cause a problem to CPU0 Non-Secure SW. 125 * The workaround must be: 126 * 1) Before doing the CPU1 wakeup, CPU0 must disable 127 * the GIC distributor 128 * 2) CPU1 must re-enable the GIC distributor on 129 * it's wakeup path. 130 */ 131 if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) { 132 local_irq_disable(); 133 gic_dist_disable(); 134 } 135 136 /* 137 * Ensure that CPU power state is set to ON to avoid CPU 138 * powerdomain transition on wfi 139 */ 140 clkdm_wakeup(cpu1_clkdm); 141 omap_set_pwrdm_state(cpu1_pwrdm, PWRDM_POWER_ON); 142 clkdm_allow_idle(cpu1_clkdm); 143 144 if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) { 145 while (gic_dist_disabled()) { 146 udelay(1); 147 cpu_relax(); 148 } 149 gic_timer_retrigger(); 150 local_irq_enable(); 151 } 152 } else { 153 dsb_sev(); 154 booted = true; 155 } 156 157 arch_send_wakeup_ipi_mask(cpumask_of(cpu)); 158 159 /* 160 * Now the secondary core is starting up let it run its 161 * calibrations, then wait for it to finish 162 */ 163 spin_unlock(&boot_lock); 164 165 return 0; 166 } 167 168 /* 169 * Initialise the CPU possible map early - this describes the CPUs 170 * which may be present or become present in the system. 171 */ 172 static void __init omap4_smp_init_cpus(void) 173 { 174 unsigned int i = 0, ncores = 1, cpu_id; 175 176 /* Use ARM cpuid check here, as SoC detection will not work so early */ 177 cpu_id = read_cpuid_id() & CPU_MASK; 178 if (cpu_id == CPU_CORTEX_A9) { 179 /* 180 * Currently we can't call ioremap here because 181 * SoC detection won't work until after init_early. 182 */ 183 scu_base = OMAP2_L4_IO_ADDRESS(scu_a9_get_base()); 184 BUG_ON(!scu_base); 185 ncores = scu_get_core_count(scu_base); 186 } else if (cpu_id == CPU_CORTEX_A15) { 187 ncores = OMAP5_CORE_COUNT; 188 } 189 190 /* sanity check */ 191 if (ncores > nr_cpu_ids) { 192 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", 193 ncores, nr_cpu_ids); 194 ncores = nr_cpu_ids; 195 } 196 197 for (i = 0; i < ncores; i++) 198 set_cpu_possible(i, true); 199 } 200 201 static void __init omap4_smp_prepare_cpus(unsigned int max_cpus) 202 { 203 void *startup_addr = omap4_secondary_startup; 204 void __iomem *base = omap_get_wakeupgen_base(); 205 206 /* 207 * Initialise the SCU and wake up the secondary core using 208 * wakeup_secondary(). 209 */ 210 if (scu_base) 211 scu_enable(scu_base); 212 213 if (cpu_is_omap446x()) { 214 startup_addr = omap4460_secondary_startup; 215 pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD; 216 } 217 218 /* 219 * Write the address of secondary startup routine into the 220 * AuxCoreBoot1 where ROM code will jump and start executing 221 * on secondary core once out of WFE 222 * A barrier is added to ensure that write buffer is drained 223 */ 224 if (omap_secure_apis_support()) 225 omap_auxcoreboot_addr(virt_to_phys(startup_addr)); 226 else 227 __raw_writel(virt_to_phys(omap5_secondary_startup), 228 base + OMAP_AUX_CORE_BOOT_1); 229 230 } 231 232 struct smp_operations omap4_smp_ops __initdata = { 233 .smp_init_cpus = omap4_smp_init_cpus, 234 .smp_prepare_cpus = omap4_smp_prepare_cpus, 235 .smp_secondary_init = omap4_secondary_init, 236 .smp_boot_secondary = omap4_boot_secondary, 237 #ifdef CONFIG_HOTPLUG_CPU 238 .cpu_die = omap4_cpu_die, 239 #endif 240 }; 241