1 /* 2 * OMAP4 SMP source file. It contains platform specific functions 3 * needed for the linux smp kernel. 4 * 5 * Copyright (C) 2009 Texas Instruments, Inc. 6 * 7 * Author: 8 * Santosh Shilimkar <santosh.shilimkar@ti.com> 9 * 10 * Platform file needed for the OMAP4 SMP. This file is based on arm 11 * realview smp platform. 12 * * Copyright (c) 2002 ARM Limited. 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License version 2 as 16 * published by the Free Software Foundation. 17 */ 18 #include <linux/init.h> 19 #include <linux/device.h> 20 #include <linux/smp.h> 21 #include <linux/io.h> 22 #include <linux/irqchip/arm-gic.h> 23 24 #include <asm/smp_scu.h> 25 #include <asm/virt.h> 26 27 #include "omap-secure.h" 28 #include "omap-wakeupgen.h" 29 #include <asm/cputype.h> 30 31 #include "soc.h" 32 #include "iomap.h" 33 #include "common.h" 34 #include "clockdomain.h" 35 #include "pm.h" 36 37 #define CPU_MASK 0xff0ffff0 38 #define CPU_CORTEX_A9 0x410FC090 39 #define CPU_CORTEX_A15 0x410FC0F0 40 41 #define OMAP5_CORE_COUNT 0x2 42 43 struct omap_smp_config { 44 unsigned long cpu1_rstctrl_pa; 45 void __iomem *cpu1_rstctrl_va; 46 void __iomem *scu_base; 47 void *startup_addr; 48 }; 49 50 static struct omap_smp_config cfg; 51 52 static const struct omap_smp_config omap443x_cfg __initconst = { 53 .cpu1_rstctrl_pa = 0x4824380c, 54 .startup_addr = omap4_secondary_startup, 55 }; 56 57 static const struct omap_smp_config omap446x_cfg __initconst = { 58 .cpu1_rstctrl_pa = 0x4824380c, 59 .startup_addr = omap4460_secondary_startup, 60 }; 61 62 static const struct omap_smp_config omap5_cfg __initconst = { 63 .cpu1_rstctrl_pa = 0x48243810, 64 .startup_addr = omap5_secondary_startup, 65 }; 66 67 static DEFINE_SPINLOCK(boot_lock); 68 69 void __iomem *omap4_get_scu_base(void) 70 { 71 return cfg.scu_base; 72 } 73 74 #ifdef CONFIG_OMAP5_ERRATA_801819 75 void omap5_erratum_workaround_801819(void) 76 { 77 u32 acr, revidr; 78 u32 acr_mask; 79 80 /* REVIDR[3] indicates erratum fix available on silicon */ 81 asm volatile ("mrc p15, 0, %0, c0, c0, 6" : "=r" (revidr)); 82 if (revidr & (0x1 << 3)) 83 return; 84 85 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); 86 /* 87 * BIT(27) - Disables streaming. All write-allocate lines allocate in 88 * the L1 or L2 cache. 89 * BIT(25) - Disables streaming. All write-allocate lines allocate in 90 * the L1 cache. 91 */ 92 acr_mask = (0x3 << 25) | (0x3 << 27); 93 /* do we already have it done.. if yes, skip expensive smc */ 94 if ((acr & acr_mask) == acr_mask) 95 return; 96 97 acr |= acr_mask; 98 omap_smc1(OMAP5_DRA7_MON_SET_ACR_INDEX, acr); 99 100 pr_debug("%s: ARM erratum workaround 801819 applied on CPU%d\n", 101 __func__, smp_processor_id()); 102 } 103 #else 104 static inline void omap5_erratum_workaround_801819(void) { } 105 #endif 106 107 static void omap4_secondary_init(unsigned int cpu) 108 { 109 /* 110 * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device. 111 * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA 112 * init and for CPU1, a secure PPA API provided. CPU0 must be ON 113 * while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+. 114 * OMAP443X GP devices- SMP bit isn't accessible. 115 * OMAP446X GP devices - SMP bit access is enabled on both CPUs. 116 */ 117 if (soc_is_omap443x() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) 118 omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX, 119 4, 0, 0, 0, 0, 0); 120 121 if (soc_is_omap54xx() || soc_is_dra7xx()) { 122 /* 123 * Configure the CNTFRQ register for the secondary cpu's which 124 * indicates the frequency of the cpu local timers. 125 */ 126 set_cntfreq(); 127 /* Configure ACR to disable streaming WA for 801819 */ 128 omap5_erratum_workaround_801819(); 129 } 130 131 /* 132 * Synchronise with the boot thread. 133 */ 134 spin_lock(&boot_lock); 135 spin_unlock(&boot_lock); 136 } 137 138 static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle) 139 { 140 static struct clockdomain *cpu1_clkdm; 141 static bool booted; 142 static struct powerdomain *cpu1_pwrdm; 143 void __iomem *base = omap_get_wakeupgen_base(); 144 145 /* 146 * Set synchronisation state between this boot processor 147 * and the secondary one 148 */ 149 spin_lock(&boot_lock); 150 151 /* 152 * Update the AuxCoreBoot0 with boot state for secondary core. 153 * omap4_secondary_startup() routine will hold the secondary core till 154 * the AuxCoreBoot1 register is updated with cpu state 155 * A barrier is added to ensure that write buffer is drained 156 */ 157 if (omap_secure_apis_support()) 158 omap_modify_auxcoreboot0(0x200, 0xfffffdff); 159 else 160 writel_relaxed(0x20, base + OMAP_AUX_CORE_BOOT_0); 161 162 if (!cpu1_clkdm && !cpu1_pwrdm) { 163 cpu1_clkdm = clkdm_lookup("mpu1_clkdm"); 164 cpu1_pwrdm = pwrdm_lookup("cpu1_pwrdm"); 165 } 166 167 /* 168 * The SGI(Software Generated Interrupts) are not wakeup capable 169 * from low power states. This is known limitation on OMAP4 and 170 * needs to be worked around by using software forced clockdomain 171 * wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to 172 * software force wakeup. The clockdomain is then put back to 173 * hardware supervised mode. 174 * More details can be found in OMAP4430 TRM - Version J 175 * Section : 176 * 4.3.4.2 Power States of CPU0 and CPU1 177 */ 178 if (booted && cpu1_pwrdm && cpu1_clkdm) { 179 /* 180 * GIC distributor control register has changed between 181 * CortexA9 r1pX and r2pX. The Control Register secure 182 * banked version is now composed of 2 bits: 183 * bit 0 == Secure Enable 184 * bit 1 == Non-Secure Enable 185 * The Non-Secure banked register has not changed 186 * Because the ROM Code is based on the r1pX GIC, the CPU1 187 * GIC restoration will cause a problem to CPU0 Non-Secure SW. 188 * The workaround must be: 189 * 1) Before doing the CPU1 wakeup, CPU0 must disable 190 * the GIC distributor 191 * 2) CPU1 must re-enable the GIC distributor on 192 * it's wakeup path. 193 */ 194 if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) { 195 local_irq_disable(); 196 gic_dist_disable(); 197 } 198 199 /* 200 * Ensure that CPU power state is set to ON to avoid CPU 201 * powerdomain transition on wfi 202 */ 203 clkdm_deny_idle_nolock(cpu1_clkdm); 204 pwrdm_set_next_pwrst(cpu1_pwrdm, PWRDM_POWER_ON); 205 clkdm_allow_idle_nolock(cpu1_clkdm); 206 207 if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) { 208 while (gic_dist_disabled()) { 209 udelay(1); 210 cpu_relax(); 211 } 212 gic_timer_retrigger(); 213 local_irq_enable(); 214 } 215 } else { 216 dsb_sev(); 217 booted = true; 218 } 219 220 arch_send_wakeup_ipi_mask(cpumask_of(cpu)); 221 222 /* 223 * Now the secondary core is starting up let it run its 224 * calibrations, then wait for it to finish 225 */ 226 spin_unlock(&boot_lock); 227 228 return 0; 229 } 230 231 /* 232 * Initialise the CPU possible map early - this describes the CPUs 233 * which may be present or become present in the system. 234 */ 235 static void __init omap4_smp_init_cpus(void) 236 { 237 unsigned int i = 0, ncores = 1, cpu_id; 238 239 /* Use ARM cpuid check here, as SoC detection will not work so early */ 240 cpu_id = read_cpuid_id() & CPU_MASK; 241 if (cpu_id == CPU_CORTEX_A9) { 242 /* 243 * Currently we can't call ioremap here because 244 * SoC detection won't work until after init_early. 245 */ 246 cfg.scu_base = OMAP2_L4_IO_ADDRESS(scu_a9_get_base()); 247 BUG_ON(!cfg.scu_base); 248 ncores = scu_get_core_count(cfg.scu_base); 249 } else if (cpu_id == CPU_CORTEX_A15) { 250 ncores = OMAP5_CORE_COUNT; 251 } 252 253 /* sanity check */ 254 if (ncores > nr_cpu_ids) { 255 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", 256 ncores, nr_cpu_ids); 257 ncores = nr_cpu_ids; 258 } 259 260 for (i = 0; i < ncores; i++) 261 set_cpu_possible(i, true); 262 } 263 264 static void __init omap4_smp_prepare_cpus(unsigned int max_cpus) 265 { 266 void __iomem *base = omap_get_wakeupgen_base(); 267 const struct omap_smp_config *c = NULL; 268 269 if (soc_is_omap443x()) 270 c = &omap443x_cfg; 271 else if (soc_is_omap446x()) 272 c = &omap446x_cfg; 273 else if (soc_is_dra74x() || soc_is_omap54xx()) 274 c = &omap5_cfg; 275 276 if (!c) { 277 pr_err("%s Unknown SMP SoC?\n", __func__); 278 return; 279 } 280 281 /* Must preserve cfg.scu_base set earlier */ 282 cfg.cpu1_rstctrl_pa = c->cpu1_rstctrl_pa; 283 cfg.startup_addr = c->startup_addr; 284 285 if (soc_is_dra74x() || soc_is_omap54xx()) { 286 if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE) 287 cfg.startup_addr = omap5_secondary_hyp_startup; 288 omap5_erratum_workaround_801819(); 289 } 290 291 cfg.cpu1_rstctrl_va = ioremap(cfg.cpu1_rstctrl_pa, 4); 292 if (!cfg.cpu1_rstctrl_va) 293 return; 294 295 /* 296 * Initialise the SCU and wake up the secondary core using 297 * wakeup_secondary(). 298 */ 299 if (cfg.scu_base) 300 scu_enable(cfg.scu_base); 301 302 /* 303 * Reset CPU1 before configuring, otherwise kexec will 304 * end up trying to use old kernel startup address. 305 */ 306 if (cfg.cpu1_rstctrl_va) { 307 writel_relaxed(1, cfg.cpu1_rstctrl_va); 308 readl_relaxed(cfg.cpu1_rstctrl_va); 309 writel_relaxed(0, cfg.cpu1_rstctrl_va); 310 } 311 312 /* 313 * Write the address of secondary startup routine into the 314 * AuxCoreBoot1 where ROM code will jump and start executing 315 * on secondary core once out of WFE 316 * A barrier is added to ensure that write buffer is drained 317 */ 318 if (omap_secure_apis_support()) 319 omap_auxcoreboot_addr(virt_to_phys(cfg.startup_addr)); 320 else 321 writel_relaxed(virt_to_phys(cfg.startup_addr), 322 base + OMAP_AUX_CORE_BOOT_1); 323 } 324 325 const struct smp_operations omap4_smp_ops __initconst = { 326 .smp_init_cpus = omap4_smp_init_cpus, 327 .smp_prepare_cpus = omap4_smp_prepare_cpus, 328 .smp_secondary_init = omap4_secondary_init, 329 .smp_boot_secondary = omap4_boot_secondary, 330 #ifdef CONFIG_HOTPLUG_CPU 331 .cpu_die = omap4_cpu_die, 332 .cpu_kill = omap4_cpu_kill, 333 #endif 334 }; 335