xref: /openbmc/linux/arch/arm/mach-omap2/omap-smp.c (revision 0edbfea5)
1 /*
2  * OMAP4 SMP source file. It contains platform specific functions
3  * needed for the linux smp kernel.
4  *
5  * Copyright (C) 2009 Texas Instruments, Inc.
6  *
7  * Author:
8  *      Santosh Shilimkar <santosh.shilimkar@ti.com>
9  *
10  * Platform file needed for the OMAP4 SMP. This file is based on arm
11  * realview smp platform.
12  * * Copyright (c) 2002 ARM Limited.
13  *
14  * This program is free software; you can redistribute it and/or modify
15  * it under the terms of the GNU General Public License version 2 as
16  * published by the Free Software Foundation.
17  */
18 #include <linux/init.h>
19 #include <linux/device.h>
20 #include <linux/smp.h>
21 #include <linux/io.h>
22 #include <linux/irqchip/arm-gic.h>
23 
24 #include <asm/smp_scu.h>
25 #include <asm/virt.h>
26 
27 #include "omap-secure.h"
28 #include "omap-wakeupgen.h"
29 #include <asm/cputype.h>
30 
31 #include "soc.h"
32 #include "iomap.h"
33 #include "common.h"
34 #include "clockdomain.h"
35 #include "pm.h"
36 
37 #define CPU_MASK		0xff0ffff0
38 #define CPU_CORTEX_A9		0x410FC090
39 #define CPU_CORTEX_A15		0x410FC0F0
40 
41 #define OMAP5_CORE_COUNT	0x2
42 
43 /* SCU base address */
44 static void __iomem *scu_base;
45 
46 static DEFINE_SPINLOCK(boot_lock);
47 
48 void __iomem *omap4_get_scu_base(void)
49 {
50 	return scu_base;
51 }
52 
53 static void omap4_secondary_init(unsigned int cpu)
54 {
55 	/*
56 	 * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
57 	 * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA
58 	 * init and for CPU1, a secure PPA API provided. CPU0 must be ON
59 	 * while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+.
60 	 * OMAP443X GP devices- SMP bit isn't accessible.
61 	 * OMAP446X GP devices - SMP bit access is enabled on both CPUs.
62 	 */
63 	if (cpu_is_omap443x() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
64 		omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX,
65 							4, 0, 0, 0, 0, 0);
66 
67 	/*
68 	 * Configure the CNTFRQ register for the secondary cpu's which
69 	 * indicates the frequency of the cpu local timers.
70 	 */
71 	if (soc_is_omap54xx() || soc_is_dra7xx())
72 		set_cntfreq();
73 
74 	/*
75 	 * Synchronise with the boot thread.
76 	 */
77 	spin_lock(&boot_lock);
78 	spin_unlock(&boot_lock);
79 }
80 
81 static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
82 {
83 	static struct clockdomain *cpu1_clkdm;
84 	static bool booted;
85 	static struct powerdomain *cpu1_pwrdm;
86 	void __iomem *base = omap_get_wakeupgen_base();
87 
88 	/*
89 	 * Set synchronisation state between this boot processor
90 	 * and the secondary one
91 	 */
92 	spin_lock(&boot_lock);
93 
94 	/*
95 	 * Update the AuxCoreBoot0 with boot state for secondary core.
96 	 * omap4_secondary_startup() routine will hold the secondary core till
97 	 * the AuxCoreBoot1 register is updated with cpu state
98 	 * A barrier is added to ensure that write buffer is drained
99 	 */
100 	if (omap_secure_apis_support())
101 		omap_modify_auxcoreboot0(0x200, 0xfffffdff);
102 	else
103 		writel_relaxed(0x20, base + OMAP_AUX_CORE_BOOT_0);
104 
105 	if (!cpu1_clkdm && !cpu1_pwrdm) {
106 		cpu1_clkdm = clkdm_lookup("mpu1_clkdm");
107 		cpu1_pwrdm = pwrdm_lookup("cpu1_pwrdm");
108 	}
109 
110 	/*
111 	 * The SGI(Software Generated Interrupts) are not wakeup capable
112 	 * from low power states. This is known limitation on OMAP4 and
113 	 * needs to be worked around by using software forced clockdomain
114 	 * wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to
115 	 * software force wakeup. The clockdomain is then put back to
116 	 * hardware supervised mode.
117 	 * More details can be found in OMAP4430 TRM - Version J
118 	 * Section :
119 	 *	4.3.4.2 Power States of CPU0 and CPU1
120 	 */
121 	if (booted && cpu1_pwrdm && cpu1_clkdm) {
122 		/*
123 		 * GIC distributor control register has changed between
124 		 * CortexA9 r1pX and r2pX. The Control Register secure
125 		 * banked version is now composed of 2 bits:
126 		 * bit 0 == Secure Enable
127 		 * bit 1 == Non-Secure Enable
128 		 * The Non-Secure banked register has not changed
129 		 * Because the ROM Code is based on the r1pX GIC, the CPU1
130 		 * GIC restoration will cause a problem to CPU0 Non-Secure SW.
131 		 * The workaround must be:
132 		 * 1) Before doing the CPU1 wakeup, CPU0 must disable
133 		 * the GIC distributor
134 		 * 2) CPU1 must re-enable the GIC distributor on
135 		 * it's wakeup path.
136 		 */
137 		if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) {
138 			local_irq_disable();
139 			gic_dist_disable();
140 		}
141 
142 		/*
143 		 * Ensure that CPU power state is set to ON to avoid CPU
144 		 * powerdomain transition on wfi
145 		 */
146 		clkdm_wakeup_nolock(cpu1_clkdm);
147 		pwrdm_set_next_pwrst(cpu1_pwrdm, PWRDM_POWER_ON);
148 		clkdm_allow_idle_nolock(cpu1_clkdm);
149 
150 		if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) {
151 			while (gic_dist_disabled()) {
152 				udelay(1);
153 				cpu_relax();
154 			}
155 			gic_timer_retrigger();
156 			local_irq_enable();
157 		}
158 	} else {
159 		dsb_sev();
160 		booted = true;
161 	}
162 
163 	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
164 
165 	/*
166 	 * Now the secondary core is starting up let it run its
167 	 * calibrations, then wait for it to finish
168 	 */
169 	spin_unlock(&boot_lock);
170 
171 	return 0;
172 }
173 
174 /*
175  * Initialise the CPU possible map early - this describes the CPUs
176  * which may be present or become present in the system.
177  */
178 static void __init omap4_smp_init_cpus(void)
179 {
180 	unsigned int i = 0, ncores = 1, cpu_id;
181 
182 	/* Use ARM cpuid check here, as SoC detection will not work so early */
183 	cpu_id = read_cpuid_id() & CPU_MASK;
184 	if (cpu_id == CPU_CORTEX_A9) {
185 		/*
186 		 * Currently we can't call ioremap here because
187 		 * SoC detection won't work until after init_early.
188 		 */
189 		scu_base =  OMAP2_L4_IO_ADDRESS(scu_a9_get_base());
190 		BUG_ON(!scu_base);
191 		ncores = scu_get_core_count(scu_base);
192 	} else if (cpu_id == CPU_CORTEX_A15) {
193 		ncores = OMAP5_CORE_COUNT;
194 	}
195 
196 	/* sanity check */
197 	if (ncores > nr_cpu_ids) {
198 		pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
199 			ncores, nr_cpu_ids);
200 		ncores = nr_cpu_ids;
201 	}
202 
203 	for (i = 0; i < ncores; i++)
204 		set_cpu_possible(i, true);
205 }
206 
207 static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
208 {
209 	void *startup_addr = omap4_secondary_startup;
210 	void __iomem *base = omap_get_wakeupgen_base();
211 
212 	/*
213 	 * Initialise the SCU and wake up the secondary core using
214 	 * wakeup_secondary().
215 	 */
216 	if (scu_base)
217 		scu_enable(scu_base);
218 
219 	if (cpu_is_omap446x())
220 		startup_addr = omap4460_secondary_startup;
221 
222 	/*
223 	 * Write the address of secondary startup routine into the
224 	 * AuxCoreBoot1 where ROM code will jump and start executing
225 	 * on secondary core once out of WFE
226 	 * A barrier is added to ensure that write buffer is drained
227 	 */
228 	if (omap_secure_apis_support())
229 		omap_auxcoreboot_addr(virt_to_phys(startup_addr));
230 	else
231 		/*
232 		 * If the boot CPU is in HYP mode then start secondary
233 		 * CPU in HYP mode as well.
234 		 */
235 		if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE)
236 			writel_relaxed(virt_to_phys(omap5_secondary_hyp_startup),
237 				       base + OMAP_AUX_CORE_BOOT_1);
238 		else
239 			writel_relaxed(virt_to_phys(omap5_secondary_startup),
240 				       base + OMAP_AUX_CORE_BOOT_1);
241 
242 }
243 
244 const struct smp_operations omap4_smp_ops __initconst = {
245 	.smp_init_cpus		= omap4_smp_init_cpus,
246 	.smp_prepare_cpus	= omap4_smp_prepare_cpus,
247 	.smp_secondary_init	= omap4_secondary_init,
248 	.smp_boot_secondary	= omap4_boot_secondary,
249 #ifdef CONFIG_HOTPLUG_CPU
250 	.cpu_die		= omap4_cpu_die,
251 #endif
252 };
253