1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * omap-secure.h: OMAP Secure infrastructure header. 4 * 5 * Copyright (C) 2011 Texas Instruments, Inc. 6 * Santosh Shilimkar <santosh.shilimkar@ti.com> 7 * Copyright (C) 2012 Ivaylo Dimitrov <freemangordon@abv.bg> 8 * Copyright (C) 2013 Pali Rohár <pali.rohar@gmail.com> 9 */ 10 #ifndef OMAP_ARCH_OMAP_SECURE_H 11 #define OMAP_ARCH_OMAP_SECURE_H 12 13 #include <linux/types.h> 14 15 /* Monitor error code */ 16 #define API_HAL_RET_VALUE_NS2S_CONVERSION_ERROR 0xFFFFFFFE 17 #define API_HAL_RET_VALUE_SERVICE_UNKNWON 0xFFFFFFFF 18 19 /* HAL API error codes */ 20 #define API_HAL_RET_VALUE_OK 0x00 21 #define API_HAL_RET_VALUE_FAIL 0x01 22 23 /* Secure HAL API flags */ 24 #define FLAG_START_CRITICAL 0x4 25 #define FLAG_IRQFIQ_MASK 0x3 26 #define FLAG_IRQ_ENABLE 0x2 27 #define FLAG_FIQ_ENABLE 0x1 28 #define NO_FLAG 0x0 29 30 /* Maximum Secure memory storage size */ 31 #define OMAP_SECURE_RAM_STORAGE (88 * SZ_1K) 32 33 #define OMAP3_SAVE_SECURE_RAM_SZ 0x803F 34 35 /* Secure low power HAL API index */ 36 #define OMAP4_HAL_SAVESECURERAM_INDEX 0x1a 37 #define OMAP4_HAL_SAVEHW_INDEX 0x1b 38 #define OMAP4_HAL_SAVEALL_INDEX 0x1c 39 #define OMAP4_HAL_SAVEGIC_INDEX 0x1d 40 41 /* Secure Monitor mode APIs */ 42 #define OMAP4_MON_SCU_PWR_INDEX 0x108 43 #define OMAP4_MON_L2X0_DBG_CTRL_INDEX 0x100 44 #define OMAP4_MON_L2X0_CTRL_INDEX 0x102 45 #define OMAP4_MON_L2X0_AUXCTRL_INDEX 0x109 46 #define OMAP4_MON_L2X0_PREFETCH_INDEX 0x113 47 48 #define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX 0x109 49 #define OMAP5_MON_AMBA_IF_INDEX 0x108 50 #define OMAP5_DRA7_MON_SET_ACR_INDEX 0x107 51 52 /* Secure PPA(Primary Protected Application) APIs */ 53 #define OMAP4_PPA_L2_POR_INDEX 0x23 54 #define OMAP4_PPA_CPU_ACTRL_SMP_INDEX 0x25 55 56 #define AM43xx_PPA_SVC_PM_SUSPEND 0x71 57 #define AM43xx_PPA_SVC_PM_RESUME 0x72 58 59 /* Secure RX-51 PPA (Primary Protected Application) APIs */ 60 #define RX51_PPA_HWRNG 29 61 #define RX51_PPA_L2_INVAL 40 62 #define RX51_PPA_WRITE_ACR 42 63 64 #ifndef __ASSEMBLER__ 65 66 extern u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, 67 u32 arg1, u32 arg2, u32 arg3, u32 arg4); 68 extern void omap_smccc_smc(u32 fn, u32 arg); 69 extern void omap_smc1(u32 fn, u32 arg); 70 extern u32 omap_smc2(u32 id, u32 falg, u32 pargs); 71 extern u32 omap_smc3(u32 id, u32 process, u32 flag, u32 pargs); 72 extern phys_addr_t omap_secure_ram_mempool_base(void); 73 extern int omap_secure_ram_reserve_memblock(void); 74 extern u32 save_secure_ram_context(u32 args_pa); 75 extern u32 omap3_save_secure_ram(void __iomem *save_regs, int size); 76 77 extern u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs, 78 u32 arg1, u32 arg2, u32 arg3, u32 arg4); 79 extern u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits); 80 extern u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag); 81 82 extern bool optee_available; 83 void omap_secure_init(void); 84 85 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER 86 void set_cntfreq(void); 87 #else 88 static inline void set_cntfreq(void) 89 { 90 } 91 #endif 92 93 #endif /* __ASSEMBLER__ */ 94 #endif /* OMAP_ARCH_OMAP_SECURE_H */ 95