1 /* 2 * OMAP Secure API infrastructure. 3 * 4 * Copyright (C) 2011 Texas Instruments, Inc. 5 * Santosh Shilimkar <santosh.shilimkar@ti.com> 6 * Copyright (C) 2012 Ivaylo Dimitrov <freemangordon@abv.bg> 7 * Copyright (C) 2013 Pali Rohár <pali.rohar@gmail.com> 8 * 9 * 10 * This program is free software,you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #include <linux/kernel.h> 16 #include <linux/init.h> 17 #include <linux/io.h> 18 #include <linux/memblock.h> 19 20 #include <asm/cacheflush.h> 21 #include <asm/memblock.h> 22 23 #include "omap-secure.h" 24 25 static phys_addr_t omap_secure_memblock_base; 26 27 /** 28 * omap_sec_dispatcher: Routine to dispatch low power secure 29 * service routines 30 * @idx: The HAL API index 31 * @flag: The flag indicating criticality of operation 32 * @nargs: Number of valid arguments out of four. 33 * @arg1, arg2, arg3 args4: Parameters passed to secure API 34 * 35 * Return the non-zero error value on failure. 36 */ 37 u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2, 38 u32 arg3, u32 arg4) 39 { 40 u32 ret; 41 u32 param[5]; 42 43 param[0] = nargs; 44 param[1] = arg1; 45 param[2] = arg2; 46 param[3] = arg3; 47 param[4] = arg4; 48 49 /* 50 * Secure API needs physical address 51 * pointer for the parameters 52 */ 53 flush_cache_all(); 54 outer_clean_range(__pa(param), __pa(param + 5)); 55 ret = omap_smc2(idx, flag, __pa(param)); 56 57 return ret; 58 } 59 60 /* Allocate the memory to save secure ram */ 61 int __init omap_secure_ram_reserve_memblock(void) 62 { 63 u32 size = OMAP_SECURE_RAM_STORAGE; 64 65 size = ALIGN(size, SECTION_SIZE); 66 omap_secure_memblock_base = arm_memblock_steal(size, SECTION_SIZE); 67 68 return 0; 69 } 70 71 phys_addr_t omap_secure_ram_mempool_base(void) 72 { 73 return omap_secure_memblock_base; 74 } 75 76 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 77 u32 omap3_save_secure_ram(void __iomem *addr, int size) 78 { 79 u32 ret; 80 u32 param[5]; 81 82 if (size != OMAP3_SAVE_SECURE_RAM_SZ) 83 return OMAP3_SAVE_SECURE_RAM_SZ; 84 85 param[0] = 4; /* Number of arguments */ 86 param[1] = __pa(addr); /* Physical address for saving */ 87 param[2] = 0; 88 param[3] = 1; 89 param[4] = 1; 90 91 ret = save_secure_ram_context(__pa(param)); 92 93 return ret; 94 } 95 #endif 96 97 /** 98 * rx51_secure_dispatcher: Routine to dispatch secure PPA API calls 99 * @idx: The PPA API index 100 * @process: Process ID 101 * @flag: The flag indicating criticality of operation 102 * @nargs: Number of valid arguments out of four. 103 * @arg1, arg2, arg3 args4: Parameters passed to secure API 104 * 105 * Return the non-zero error value on failure. 106 * 107 * NOTE: rx51_secure_dispatcher differs from omap_secure_dispatcher because 108 * it calling omap_smc3() instead omap_smc2() and param[0] is nargs+1 109 */ 110 u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs, 111 u32 arg1, u32 arg2, u32 arg3, u32 arg4) 112 { 113 u32 ret; 114 u32 param[5]; 115 116 param[0] = nargs+1; /* RX-51 needs number of arguments + 1 */ 117 param[1] = arg1; 118 param[2] = arg2; 119 param[3] = arg3; 120 param[4] = arg4; 121 122 /* 123 * Secure API needs physical address 124 * pointer for the parameters 125 */ 126 local_irq_disable(); 127 local_fiq_disable(); 128 flush_cache_all(); 129 outer_clean_range(__pa(param), __pa(param + 5)); 130 ret = omap_smc3(idx, process, flag, __pa(param)); 131 flush_cache_all(); 132 local_fiq_enable(); 133 local_irq_enable(); 134 135 return ret; 136 } 137 138 /** 139 * rx51_secure_update_aux_cr: Routine to modify the contents of Auxiliary Control Register 140 * @set_bits: bits to set in ACR 141 * @clr_bits: bits to clear in ACR 142 * 143 * Return the non-zero error value on failure. 144 */ 145 u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits) 146 { 147 u32 acr; 148 149 /* Read ACR */ 150 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); 151 acr &= ~clear_bits; 152 acr |= set_bits; 153 154 return rx51_secure_dispatcher(RX51_PPA_WRITE_ACR, 155 0, 156 FLAG_START_CRITICAL, 157 1, acr, 0, 0, 0); 158 } 159 160 /** 161 * rx51_secure_rng_call: Routine for HW random generator 162 */ 163 u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag) 164 { 165 return rx51_secure_dispatcher(RX51_PPA_HWRNG, 166 0, 167 NO_FLAG, 168 3, ptr, count, flag, 0); 169 } 170