1 /* 2 * OMAP MPUSS low power code 3 * 4 * Copyright (C) 2011 Texas Instruments, Inc. 5 * Santosh Shilimkar <santosh.shilimkar@ti.com> 6 * 7 * OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU 8 * Local timer and Watchdog, GIC, SCU, PL310 L2 cache controller, 9 * CPU0 and CPU1 LPRM modules. 10 * CPU0, CPU1 and MPUSS each have there own power domain and 11 * hence multiple low power combinations of MPUSS are possible. 12 * 13 * The CPU0 and CPU1 can't support Closed switch Retention (CSWR) 14 * because the mode is not supported by hw constraints of dormant 15 * mode. While waking up from the dormant mode, a reset signal 16 * to the Cortex-A9 processor must be asserted by the external 17 * power controller. 18 * 19 * With architectural inputs and hardware recommendations, only 20 * below modes are supported from power gain vs latency point of view. 21 * 22 * CPU0 CPU1 MPUSS 23 * ---------------------------------------------- 24 * ON ON ON 25 * ON(Inactive) OFF ON(Inactive) 26 * OFF OFF CSWR 27 * OFF OFF OSWR 28 * OFF OFF OFF(Device OFF *TBD) 29 * ---------------------------------------------- 30 * 31 * Note: CPU0 is the master core and it is the last CPU to go down 32 * and first to wake-up when MPUSS low power states are excercised 33 * 34 * 35 * This program is free software; you can redistribute it and/or modify 36 * it under the terms of the GNU General Public License version 2 as 37 * published by the Free Software Foundation. 38 */ 39 40 #include <linux/kernel.h> 41 #include <linux/io.h> 42 #include <linux/errno.h> 43 #include <linux/linkage.h> 44 #include <linux/smp.h> 45 46 #include <asm/cacheflush.h> 47 #include <asm/tlbflush.h> 48 #include <asm/smp_scu.h> 49 #include <asm/pgalloc.h> 50 #include <asm/suspend.h> 51 #include <asm/hardware/cache-l2x0.h> 52 53 #include "soc.h" 54 #include "common.h" 55 #include "omap44xx.h" 56 #include "omap4-sar-layout.h" 57 #include "pm.h" 58 #include "prcm_mpu44xx.h" 59 #include "prminst44xx.h" 60 #include "prcm44xx.h" 61 #include "prm44xx.h" 62 #include "prm-regbits-44xx.h" 63 64 #ifdef CONFIG_SMP 65 66 struct omap4_cpu_pm_info { 67 struct powerdomain *pwrdm; 68 void __iomem *scu_sar_addr; 69 void __iomem *wkup_sar_addr; 70 void __iomem *l2x0_sar_addr; 71 void (*secondary_startup)(void); 72 }; 73 74 static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info); 75 static struct powerdomain *mpuss_pd; 76 static void __iomem *sar_base; 77 78 /* 79 * Program the wakeup routine address for the CPU0 and CPU1 80 * used for OFF or DORMANT wakeup. 81 */ 82 static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr) 83 { 84 struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); 85 86 __raw_writel(addr, pm_info->wkup_sar_addr); 87 } 88 89 /* 90 * Set the CPUx powerdomain's previous power state 91 */ 92 static inline void set_cpu_next_pwrst(unsigned int cpu_id, 93 unsigned int power_state) 94 { 95 struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); 96 97 pwrdm_set_next_pwrst(pm_info->pwrdm, power_state); 98 } 99 100 /* 101 * Read CPU's previous power state 102 */ 103 static inline unsigned int read_cpu_prev_pwrst(unsigned int cpu_id) 104 { 105 struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); 106 107 return pwrdm_read_prev_pwrst(pm_info->pwrdm); 108 } 109 110 /* 111 * Clear the CPUx powerdomain's previous power state 112 */ 113 static inline void clear_cpu_prev_pwrst(unsigned int cpu_id) 114 { 115 struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); 116 117 pwrdm_clear_all_prev_pwrst(pm_info->pwrdm); 118 } 119 120 /* 121 * Store the SCU power status value to scratchpad memory 122 */ 123 static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state) 124 { 125 struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); 126 u32 scu_pwr_st; 127 128 switch (cpu_state) { 129 case PWRDM_POWER_RET: 130 scu_pwr_st = SCU_PM_DORMANT; 131 break; 132 case PWRDM_POWER_OFF: 133 scu_pwr_st = SCU_PM_POWEROFF; 134 break; 135 case PWRDM_POWER_ON: 136 case PWRDM_POWER_INACTIVE: 137 default: 138 scu_pwr_st = SCU_PM_NORMAL; 139 break; 140 } 141 142 __raw_writel(scu_pwr_st, pm_info->scu_sar_addr); 143 } 144 145 /* Helper functions for MPUSS OSWR */ 146 static inline void mpuss_clear_prev_logic_pwrst(void) 147 { 148 u32 reg; 149 150 reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, 151 OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET); 152 omap4_prminst_write_inst_reg(reg, OMAP4430_PRM_PARTITION, 153 OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET); 154 } 155 156 static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id) 157 { 158 u32 reg; 159 160 if (cpu_id) { 161 reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST, 162 OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET); 163 omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST, 164 OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET); 165 } else { 166 reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST, 167 OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET); 168 omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST, 169 OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET); 170 } 171 } 172 173 /** 174 * omap4_mpuss_read_prev_context_state: 175 * Function returns the MPUSS previous context state 176 */ 177 u32 omap4_mpuss_read_prev_context_state(void) 178 { 179 u32 reg; 180 181 reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, 182 OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET); 183 reg &= OMAP4430_LOSTCONTEXT_DFF_MASK; 184 return reg; 185 } 186 187 /* 188 * Store the CPU cluster state for L2X0 low power operations. 189 */ 190 static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state) 191 { 192 struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); 193 194 __raw_writel(save_state, pm_info->l2x0_sar_addr); 195 } 196 197 /* 198 * Save the L2X0 AUXCTRL and POR value to SAR memory. Its used to 199 * in every restore MPUSS OFF path. 200 */ 201 #ifdef CONFIG_CACHE_L2X0 202 static void save_l2x0_context(void) 203 { 204 u32 val; 205 void __iomem *l2x0_base = omap4_get_l2cache_base(); 206 207 val = __raw_readl(l2x0_base + L2X0_AUX_CTRL); 208 __raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET); 209 val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL); 210 __raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET); 211 } 212 #else 213 static void save_l2x0_context(void) 214 {} 215 #endif 216 217 /** 218 * omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function 219 * The purpose of this function is to manage low power programming 220 * of OMAP4 MPUSS subsystem 221 * @cpu : CPU ID 222 * @power_state: Low power state. 223 * 224 * MPUSS states for the context save: 225 * save_state = 226 * 0 - Nothing lost and no need to save: MPUSS INACTIVE 227 * 1 - CPUx L1 and logic lost: MPUSS CSWR 228 * 2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR 229 * 3 - CPUx L1 and logic lost + GIC + L2 lost: DEVICE OFF 230 */ 231 int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state) 232 { 233 unsigned int save_state = 0; 234 unsigned int wakeup_cpu; 235 236 if (omap_rev() == OMAP4430_REV_ES1_0) 237 return -ENXIO; 238 239 switch (power_state) { 240 case PWRDM_POWER_ON: 241 case PWRDM_POWER_INACTIVE: 242 save_state = 0; 243 break; 244 case PWRDM_POWER_OFF: 245 save_state = 1; 246 break; 247 case PWRDM_POWER_RET: 248 default: 249 /* 250 * CPUx CSWR is invalid hardware state. Also CPUx OSWR 251 * doesn't make much scense, since logic is lost and $L1 252 * needs to be cleaned because of coherency. This makes 253 * CPUx OSWR equivalent to CPUX OFF and hence not supported 254 */ 255 WARN_ON(1); 256 return -ENXIO; 257 } 258 259 pwrdm_pre_transition(NULL); 260 261 /* 262 * Check MPUSS next state and save interrupt controller if needed. 263 * In MPUSS OSWR or device OFF, interrupt controller contest is lost. 264 */ 265 mpuss_clear_prev_logic_pwrst(); 266 if ((pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_RET) && 267 (pwrdm_read_logic_retst(mpuss_pd) == PWRDM_POWER_OFF)) 268 save_state = 2; 269 270 cpu_clear_prev_logic_pwrst(cpu); 271 set_cpu_next_pwrst(cpu, power_state); 272 set_cpu_wakeup_addr(cpu, virt_to_phys(omap4_cpu_resume)); 273 scu_pwrst_prepare(cpu, power_state); 274 l2x0_pwrst_prepare(cpu, save_state); 275 276 /* 277 * Call low level function with targeted low power state. 278 */ 279 cpu_suspend(save_state, omap4_finish_suspend); 280 281 /* 282 * Restore the CPUx power state to ON otherwise CPUx 283 * power domain can transitions to programmed low power 284 * state while doing WFI outside the low powe code. On 285 * secure devices, CPUx does WFI which can result in 286 * domain transition 287 */ 288 wakeup_cpu = smp_processor_id(); 289 set_cpu_next_pwrst(wakeup_cpu, PWRDM_POWER_ON); 290 291 pwrdm_post_transition(NULL); 292 293 return 0; 294 } 295 296 /** 297 * omap4_hotplug_cpu: OMAP4 CPU hotplug entry 298 * @cpu : CPU ID 299 * @power_state: CPU low power state. 300 */ 301 int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state) 302 { 303 unsigned int cpu_state = 0; 304 struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu); 305 306 if (omap_rev() == OMAP4430_REV_ES1_0) 307 return -ENXIO; 308 309 if (power_state == PWRDM_POWER_OFF) 310 cpu_state = 1; 311 312 clear_cpu_prev_pwrst(cpu); 313 set_cpu_next_pwrst(cpu, power_state); 314 set_cpu_wakeup_addr(cpu, virt_to_phys(pm_info->secondary_startup)); 315 scu_pwrst_prepare(cpu, power_state); 316 317 /* 318 * CPU never retuns back if targeted power state is OFF mode. 319 * CPU ONLINE follows normal CPU ONLINE ptah via 320 * omap_secondary_startup(). 321 */ 322 omap4_finish_suspend(cpu_state); 323 324 set_cpu_next_pwrst(cpu, PWRDM_POWER_ON); 325 return 0; 326 } 327 328 329 /* 330 * Initialise OMAP4 MPUSS 331 */ 332 int __init omap4_mpuss_init(void) 333 { 334 struct omap4_cpu_pm_info *pm_info; 335 336 if (omap_rev() == OMAP4430_REV_ES1_0) { 337 WARN(1, "Power Management not supported on OMAP4430 ES1.0\n"); 338 return -ENODEV; 339 } 340 341 sar_base = omap4_get_sar_ram_base(); 342 343 /* Initilaise per CPU PM information */ 344 pm_info = &per_cpu(omap4_pm_info, 0x0); 345 pm_info->scu_sar_addr = sar_base + SCU_OFFSET0; 346 pm_info->wkup_sar_addr = sar_base + CPU0_WAKEUP_NS_PA_ADDR_OFFSET; 347 pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0; 348 pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm"); 349 if (!pm_info->pwrdm) { 350 pr_err("Lookup failed for CPU0 pwrdm\n"); 351 return -ENODEV; 352 } 353 354 /* Clear CPU previous power domain state */ 355 pwrdm_clear_all_prev_pwrst(pm_info->pwrdm); 356 cpu_clear_prev_logic_pwrst(0); 357 358 /* Initialise CPU0 power domain state to ON */ 359 pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON); 360 361 pm_info = &per_cpu(omap4_pm_info, 0x1); 362 pm_info->scu_sar_addr = sar_base + SCU_OFFSET1; 363 pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET; 364 pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1; 365 if (cpu_is_omap446x()) 366 pm_info->secondary_startup = omap_secondary_startup_4460; 367 else 368 pm_info->secondary_startup = omap_secondary_startup; 369 370 pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm"); 371 if (!pm_info->pwrdm) { 372 pr_err("Lookup failed for CPU1 pwrdm\n"); 373 return -ENODEV; 374 } 375 376 /* Clear CPU previous power domain state */ 377 pwrdm_clear_all_prev_pwrst(pm_info->pwrdm); 378 cpu_clear_prev_logic_pwrst(1); 379 380 /* Initialise CPU1 power domain state to ON */ 381 pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON); 382 383 mpuss_pd = pwrdm_lookup("mpu_pwrdm"); 384 if (!mpuss_pd) { 385 pr_err("Failed to lookup MPUSS power domain\n"); 386 return -ENODEV; 387 } 388 pwrdm_clear_all_prev_pwrst(mpuss_pd); 389 mpuss_clear_prev_logic_pwrst(); 390 391 /* Save device type on scratchpad for low level code to use */ 392 if (omap_type() != OMAP2_DEVICE_TYPE_GP) 393 __raw_writel(1, sar_base + OMAP_TYPE_OFFSET); 394 else 395 __raw_writel(0, sar_base + OMAP_TYPE_OFFSET); 396 397 save_l2x0_context(); 398 399 return 0; 400 } 401 402 #endif 403