1 /* 2 * OMAP MPUSS low power code 3 * 4 * Copyright (C) 2011 Texas Instruments, Inc. 5 * Santosh Shilimkar <santosh.shilimkar@ti.com> 6 * 7 * OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU 8 * Local timer and Watchdog, GIC, SCU, PL310 L2 cache controller, 9 * CPU0 and CPU1 LPRM modules. 10 * CPU0, CPU1 and MPUSS each have there own power domain and 11 * hence multiple low power combinations of MPUSS are possible. 12 * 13 * The CPU0 and CPU1 can't support Closed switch Retention (CSWR) 14 * because the mode is not supported by hw constraints of dormant 15 * mode. While waking up from the dormant mode, a reset signal 16 * to the Cortex-A9 processor must be asserted by the external 17 * power controller. 18 * 19 * With architectural inputs and hardware recommendations, only 20 * below modes are supported from power gain vs latency point of view. 21 * 22 * CPU0 CPU1 MPUSS 23 * ---------------------------------------------- 24 * ON ON ON 25 * ON(Inactive) OFF ON(Inactive) 26 * OFF OFF CSWR 27 * OFF OFF OSWR 28 * OFF OFF OFF(Device OFF *TBD) 29 * ---------------------------------------------- 30 * 31 * Note: CPU0 is the master core and it is the last CPU to go down 32 * and first to wake-up when MPUSS low power states are excercised 33 * 34 * 35 * This program is free software; you can redistribute it and/or modify 36 * it under the terms of the GNU General Public License version 2 as 37 * published by the Free Software Foundation. 38 */ 39 40 #include <linux/kernel.h> 41 #include <linux/io.h> 42 #include <linux/errno.h> 43 #include <linux/linkage.h> 44 #include <linux/smp.h> 45 46 #include <asm/cacheflush.h> 47 #include <asm/tlbflush.h> 48 #include <asm/smp_scu.h> 49 #include <asm/pgalloc.h> 50 #include <asm/suspend.h> 51 #include <asm/virt.h> 52 #include <asm/hardware/cache-l2x0.h> 53 54 #include "soc.h" 55 #include "common.h" 56 #include "omap44xx.h" 57 #include "omap4-sar-layout.h" 58 #include "pm.h" 59 #include "prcm_mpu44xx.h" 60 #include "prcm_mpu54xx.h" 61 #include "prminst44xx.h" 62 #include "prcm44xx.h" 63 #include "prm44xx.h" 64 #include "prm-regbits-44xx.h" 65 66 static void __iomem *sar_base; 67 68 #if defined(CONFIG_PM) && defined(CONFIG_SMP) 69 70 struct omap4_cpu_pm_info { 71 struct powerdomain *pwrdm; 72 void __iomem *scu_sar_addr; 73 void __iomem *wkup_sar_addr; 74 void __iomem *l2x0_sar_addr; 75 }; 76 77 /** 78 * struct cpu_pm_ops - CPU pm operations 79 * @finish_suspend: CPU suspend finisher function pointer 80 * @resume: CPU resume function pointer 81 * @scu_prepare: CPU Snoop Control program function pointer 82 * @hotplug_restart: CPU restart function pointer 83 * 84 * Structure holds functions pointer for CPU low power operations like 85 * suspend, resume and scu programming. 86 */ 87 struct cpu_pm_ops { 88 int (*finish_suspend)(unsigned long cpu_state); 89 void (*resume)(void); 90 void (*scu_prepare)(unsigned int cpu_id, unsigned int cpu_state); 91 void (*hotplug_restart)(void); 92 }; 93 94 static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info); 95 static struct powerdomain *mpuss_pd; 96 static u32 cpu_context_offset; 97 98 static int default_finish_suspend(unsigned long cpu_state) 99 { 100 omap_do_wfi(); 101 return 0; 102 } 103 104 static void dummy_cpu_resume(void) 105 {} 106 107 static void dummy_scu_prepare(unsigned int cpu_id, unsigned int cpu_state) 108 {} 109 110 static struct cpu_pm_ops omap_pm_ops = { 111 .finish_suspend = default_finish_suspend, 112 .resume = dummy_cpu_resume, 113 .scu_prepare = dummy_scu_prepare, 114 .hotplug_restart = dummy_cpu_resume, 115 }; 116 117 /* 118 * Program the wakeup routine address for the CPU0 and CPU1 119 * used for OFF or DORMANT wakeup. 120 */ 121 static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr) 122 { 123 struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); 124 125 if (pm_info->wkup_sar_addr) 126 writel_relaxed(addr, pm_info->wkup_sar_addr); 127 } 128 129 /* 130 * Store the SCU power status value to scratchpad memory 131 */ 132 static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state) 133 { 134 struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); 135 u32 scu_pwr_st; 136 137 switch (cpu_state) { 138 case PWRDM_POWER_RET: 139 scu_pwr_st = SCU_PM_DORMANT; 140 break; 141 case PWRDM_POWER_OFF: 142 scu_pwr_st = SCU_PM_POWEROFF; 143 break; 144 case PWRDM_POWER_ON: 145 case PWRDM_POWER_INACTIVE: 146 default: 147 scu_pwr_st = SCU_PM_NORMAL; 148 break; 149 } 150 151 if (pm_info->scu_sar_addr) 152 writel_relaxed(scu_pwr_st, pm_info->scu_sar_addr); 153 } 154 155 /* Helper functions for MPUSS OSWR */ 156 static inline void mpuss_clear_prev_logic_pwrst(void) 157 { 158 u32 reg; 159 160 reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, 161 OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET); 162 omap4_prminst_write_inst_reg(reg, OMAP4430_PRM_PARTITION, 163 OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET); 164 } 165 166 static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id) 167 { 168 u32 reg; 169 170 if (cpu_id) { 171 reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST, 172 cpu_context_offset); 173 omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST, 174 cpu_context_offset); 175 } else { 176 reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST, 177 cpu_context_offset); 178 omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST, 179 cpu_context_offset); 180 } 181 } 182 183 /* 184 * Store the CPU cluster state for L2X0 low power operations. 185 */ 186 static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state) 187 { 188 struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); 189 190 if (pm_info->l2x0_sar_addr) 191 writel_relaxed(save_state, pm_info->l2x0_sar_addr); 192 } 193 194 /* 195 * Save the L2X0 AUXCTRL and POR value to SAR memory. Its used to 196 * in every restore MPUSS OFF path. 197 */ 198 #ifdef CONFIG_CACHE_L2X0 199 static void __init save_l2x0_context(void) 200 { 201 void __iomem *l2x0_base = omap4_get_l2cache_base(); 202 203 if (l2x0_base && sar_base) { 204 writel_relaxed(l2x0_saved_regs.aux_ctrl, 205 sar_base + L2X0_AUXCTRL_OFFSET); 206 writel_relaxed(l2x0_saved_regs.prefetch_ctrl, 207 sar_base + L2X0_PREFETCH_CTRL_OFFSET); 208 } 209 } 210 #else 211 static void __init save_l2x0_context(void) 212 {} 213 #endif 214 215 /** 216 * omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function 217 * The purpose of this function is to manage low power programming 218 * of OMAP4 MPUSS subsystem 219 * @cpu : CPU ID 220 * @power_state: Low power state. 221 * 222 * MPUSS states for the context save: 223 * save_state = 224 * 0 - Nothing lost and no need to save: MPUSS INACTIVE 225 * 1 - CPUx L1 and logic lost: MPUSS CSWR 226 * 2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR 227 * 3 - CPUx L1 and logic lost + GIC + L2 lost: DEVICE OFF 228 */ 229 int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state) 230 { 231 struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu); 232 unsigned int save_state = 0, cpu_logic_state = PWRDM_POWER_RET; 233 unsigned int wakeup_cpu; 234 235 if (omap_rev() == OMAP4430_REV_ES1_0) 236 return -ENXIO; 237 238 switch (power_state) { 239 case PWRDM_POWER_ON: 240 case PWRDM_POWER_INACTIVE: 241 save_state = 0; 242 break; 243 case PWRDM_POWER_OFF: 244 cpu_logic_state = PWRDM_POWER_OFF; 245 save_state = 1; 246 break; 247 case PWRDM_POWER_RET: 248 if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE)) 249 save_state = 0; 250 break; 251 default: 252 /* 253 * CPUx CSWR is invalid hardware state. Also CPUx OSWR 254 * doesn't make much scense, since logic is lost and $L1 255 * needs to be cleaned because of coherency. This makes 256 * CPUx OSWR equivalent to CPUX OFF and hence not supported 257 */ 258 WARN_ON(1); 259 return -ENXIO; 260 } 261 262 pwrdm_pre_transition(NULL); 263 264 /* 265 * Check MPUSS next state and save interrupt controller if needed. 266 * In MPUSS OSWR or device OFF, interrupt controller contest is lost. 267 */ 268 mpuss_clear_prev_logic_pwrst(); 269 if ((pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_RET) && 270 (pwrdm_read_logic_retst(mpuss_pd) == PWRDM_POWER_OFF)) 271 save_state = 2; 272 273 cpu_clear_prev_logic_pwrst(cpu); 274 pwrdm_set_next_pwrst(pm_info->pwrdm, power_state); 275 pwrdm_set_logic_retst(pm_info->pwrdm, cpu_logic_state); 276 set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.resume)); 277 omap_pm_ops.scu_prepare(cpu, power_state); 278 l2x0_pwrst_prepare(cpu, save_state); 279 280 /* 281 * Call low level function with targeted low power state. 282 */ 283 if (save_state) 284 cpu_suspend(save_state, omap_pm_ops.finish_suspend); 285 else 286 omap_pm_ops.finish_suspend(save_state); 287 288 if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD) && cpu) 289 gic_dist_enable(); 290 291 /* 292 * Restore the CPUx power state to ON otherwise CPUx 293 * power domain can transitions to programmed low power 294 * state while doing WFI outside the low powe code. On 295 * secure devices, CPUx does WFI which can result in 296 * domain transition 297 */ 298 wakeup_cpu = smp_processor_id(); 299 pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON); 300 301 pwrdm_post_transition(NULL); 302 303 return 0; 304 } 305 306 /** 307 * omap4_hotplug_cpu: OMAP4 CPU hotplug entry 308 * @cpu : CPU ID 309 * @power_state: CPU low power state. 310 */ 311 int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state) 312 { 313 struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu); 314 unsigned int cpu_state = 0; 315 316 if (omap_rev() == OMAP4430_REV_ES1_0) 317 return -ENXIO; 318 319 /* Use the achievable power state for the domain */ 320 power_state = pwrdm_get_valid_lp_state(pm_info->pwrdm, 321 false, power_state); 322 323 if (power_state == PWRDM_POWER_OFF) 324 cpu_state = 1; 325 326 pwrdm_clear_all_prev_pwrst(pm_info->pwrdm); 327 pwrdm_set_next_pwrst(pm_info->pwrdm, power_state); 328 set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.hotplug_restart)); 329 omap_pm_ops.scu_prepare(cpu, power_state); 330 331 /* 332 * CPU never retuns back if targeted power state is OFF mode. 333 * CPU ONLINE follows normal CPU ONLINE ptah via 334 * omap4_secondary_startup(). 335 */ 336 omap_pm_ops.finish_suspend(cpu_state); 337 338 pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON); 339 return 0; 340 } 341 342 343 /* 344 * Enable Mercury Fast HG retention mode by default. 345 */ 346 static void enable_mercury_retention_mode(void) 347 { 348 u32 reg; 349 350 reg = omap4_prcm_mpu_read_inst_reg(OMAP54XX_PRCM_MPU_DEVICE_INST, 351 OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET); 352 /* Enable HG_EN, HG_RAMPUP = fast mode */ 353 reg |= BIT(24) | BIT(25); 354 omap4_prcm_mpu_write_inst_reg(reg, OMAP54XX_PRCM_MPU_DEVICE_INST, 355 OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET); 356 } 357 358 /* 359 * Initialise OMAP4 MPUSS 360 */ 361 int __init omap4_mpuss_init(void) 362 { 363 struct omap4_cpu_pm_info *pm_info; 364 365 if (omap_rev() == OMAP4430_REV_ES1_0) { 366 WARN(1, "Power Management not supported on OMAP4430 ES1.0\n"); 367 return -ENODEV; 368 } 369 370 /* Initilaise per CPU PM information */ 371 pm_info = &per_cpu(omap4_pm_info, 0x0); 372 if (sar_base) { 373 pm_info->scu_sar_addr = sar_base + SCU_OFFSET0; 374 if (cpu_is_omap44xx()) 375 pm_info->wkup_sar_addr = sar_base + 376 CPU0_WAKEUP_NS_PA_ADDR_OFFSET; 377 else 378 pm_info->wkup_sar_addr = sar_base + 379 OMAP5_CPU0_WAKEUP_NS_PA_ADDR_OFFSET; 380 pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0; 381 } 382 pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm"); 383 if (!pm_info->pwrdm) { 384 pr_err("Lookup failed for CPU0 pwrdm\n"); 385 return -ENODEV; 386 } 387 388 /* Clear CPU previous power domain state */ 389 pwrdm_clear_all_prev_pwrst(pm_info->pwrdm); 390 cpu_clear_prev_logic_pwrst(0); 391 392 /* Initialise CPU0 power domain state to ON */ 393 pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON); 394 395 pm_info = &per_cpu(omap4_pm_info, 0x1); 396 if (sar_base) { 397 pm_info->scu_sar_addr = sar_base + SCU_OFFSET1; 398 if (cpu_is_omap44xx()) 399 pm_info->wkup_sar_addr = sar_base + 400 CPU1_WAKEUP_NS_PA_ADDR_OFFSET; 401 else 402 pm_info->wkup_sar_addr = sar_base + 403 OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET; 404 pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1; 405 } 406 407 pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm"); 408 if (!pm_info->pwrdm) { 409 pr_err("Lookup failed for CPU1 pwrdm\n"); 410 return -ENODEV; 411 } 412 413 /* Clear CPU previous power domain state */ 414 pwrdm_clear_all_prev_pwrst(pm_info->pwrdm); 415 cpu_clear_prev_logic_pwrst(1); 416 417 /* Initialise CPU1 power domain state to ON */ 418 pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON); 419 420 mpuss_pd = pwrdm_lookup("mpu_pwrdm"); 421 if (!mpuss_pd) { 422 pr_err("Failed to lookup MPUSS power domain\n"); 423 return -ENODEV; 424 } 425 pwrdm_clear_all_prev_pwrst(mpuss_pd); 426 mpuss_clear_prev_logic_pwrst(); 427 428 if (sar_base) { 429 /* Save device type on scratchpad for low level code to use */ 430 writel_relaxed((omap_type() != OMAP2_DEVICE_TYPE_GP) ? 1 : 0, 431 sar_base + OMAP_TYPE_OFFSET); 432 save_l2x0_context(); 433 } 434 435 if (cpu_is_omap44xx()) { 436 omap_pm_ops.finish_suspend = omap4_finish_suspend; 437 omap_pm_ops.resume = omap4_cpu_resume; 438 omap_pm_ops.scu_prepare = scu_pwrst_prepare; 439 omap_pm_ops.hotplug_restart = omap4_secondary_startup; 440 cpu_context_offset = OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET; 441 } else if (soc_is_omap54xx() || soc_is_dra7xx()) { 442 cpu_context_offset = OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET; 443 enable_mercury_retention_mode(); 444 } 445 446 if (cpu_is_omap446x()) 447 omap_pm_ops.hotplug_restart = omap4460_secondary_startup; 448 449 return 0; 450 } 451 452 #endif 453 454 /* 455 * For kexec, we must set CPU1_WAKEUP_NS_PA_ADDR to point to 456 * current kernel's secondary_startup() early before 457 * clockdomains_init(). Otherwise clockdomain_init() can 458 * wake CPU1 and cause a hang. 459 */ 460 void __init omap4_mpuss_early_init(void) 461 { 462 unsigned long startup_pa; 463 464 if (!(cpu_is_omap44xx() || soc_is_omap54xx())) 465 return; 466 467 sar_base = omap4_get_sar_ram_base(); 468 469 if (cpu_is_omap443x()) 470 startup_pa = virt_to_phys(omap4_secondary_startup); 471 else if (cpu_is_omap446x()) 472 startup_pa = virt_to_phys(omap4460_secondary_startup); 473 else if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE) 474 startup_pa = virt_to_phys(omap5_secondary_hyp_startup); 475 else 476 startup_pa = virt_to_phys(omap5_secondary_startup); 477 478 if (cpu_is_omap44xx()) 479 writel_relaxed(startup_pa, sar_base + 480 CPU1_WAKEUP_NS_PA_ADDR_OFFSET); 481 else 482 writel_relaxed(startup_pa, sar_base + 483 OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET); 484 } 485