1/* 2 * Secondary CPU startup routine source file. 3 * 4 * Copyright (C) 2009 Texas Instruments, Inc. 5 * 6 * Author: 7 * Santosh Shilimkar <santosh.shilimkar@ti.com> 8 * 9 * Interface functions needed for the SMP. This file is based on arm 10 * realview smp platform. 11 * Copyright (c) 2003 ARM Limited. 12 * 13 * This program is free software,you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License version 2 as 15 * published by the Free Software Foundation. 16 */ 17 18#include <linux/linkage.h> 19#include <linux/init.h> 20 21#include "omap44xx.h" 22 23/* Physical address needed since MMU not enabled yet on secondary core */ 24#define AUX_CORE_BOOT0_PA 0x48281800 25 26/* 27 * OMAP5 specific entry point for secondary CPU to jump from ROM 28 * code. This routine also provides a holding flag into which 29 * secondary core is held until we're ready for it to initialise. 30 * The primary core will update this flag using a hardware 31+ * register AuxCoreBoot0. 32 */ 33ENTRY(omap5_secondary_startup) 34wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 35 ldr r0, [r2] 36 mov r0, r0, lsr #5 37 mrc p15, 0, r4, c0, c0, 5 38 and r4, r4, #0x0f 39 cmp r0, r4 40 bne wait 41 b secondary_startup 42END(omap5_secondary_startup) 43/* 44 * OMAP4 specific entry point for secondary CPU to jump from ROM 45 * code. This routine also provides a holding flag into which 46 * secondary core is held until we're ready for it to initialise. 47 * The primary core will update this flag using a hardware 48 * register AuxCoreBoot0. 49 */ 50ENTRY(omap4_secondary_startup) 51hold: ldr r12,=0x103 52 dsb 53 smc #0 @ read from AuxCoreBoot0 54 mov r0, r0, lsr #9 55 mrc p15, 0, r4, c0, c0, 5 56 and r4, r4, #0x0f 57 cmp r0, r4 58 bne hold 59 60 /* 61 * we've been released from the wait loop,secondary_stack 62 * should now contain the SVC stack for this core 63 */ 64 b secondary_startup 65ENDPROC(omap4_secondary_startup) 66 67ENTRY(omap4460_secondary_startup) 68hold_2: ldr r12,=0x103 69 dsb 70 smc #0 @ read from AuxCoreBoot0 71 mov r0, r0, lsr #9 72 mrc p15, 0, r4, c0, c0, 5 73 and r4, r4, #0x0f 74 cmp r0, r4 75 bne hold_2 76 77 /* 78 * GIC distributor control register has changed between 79 * CortexA9 r1pX and r2pX. The Control Register secure 80 * banked version is now composed of 2 bits: 81 * bit 0 == Secure Enable 82 * bit 1 == Non-Secure Enable 83 * The Non-Secure banked register has not changed 84 * Because the ROM Code is based on the r1pX GIC, the CPU1 85 * GIC restoration will cause a problem to CPU0 Non-Secure SW. 86 * The workaround must be: 87 * 1) Before doing the CPU1 wakeup, CPU0 must disable 88 * the GIC distributor 89 * 2) CPU1 must re-enable the GIC distributor on 90 * it's wakeup path. 91 */ 92 ldr r1, =OMAP44XX_GIC_DIST_BASE 93 ldr r0, [r1] 94 orr r0, #1 95 str r0, [r1] 96 97 /* 98 * we've been released from the wait loop,secondary_stack 99 * should now contain the SVC stack for this core 100 */ 101 b secondary_startup 102ENDPROC(omap4460_secondary_startup) 103