1/*
2 * Secondary CPU startup routine source file.
3 *
4 * Copyright (C) 2009 Texas Instruments, Inc.
5 *
6 * Author:
7 *      Santosh Shilimkar <santosh.shilimkar@ti.com>
8 *
9 * Interface functions needed for the SMP. This file is based on arm
10 * realview smp platform.
11 * Copyright (c) 2003 ARM Limited.
12 *
13 * This program is free software,you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/linkage.h>
19#include <linux/init.h>
20
21/* Physical address needed since MMU not enabled yet on secondary core */
22#define OMAP4_AUX_CORE_BOOT1_PA			0x48281804
23
24	__INIT
25
26/*
27 * OMAP4 specific entry point for secondary CPU to jump from ROM
28 * code.  This routine also provides a holding flag into which
29 * secondary core is held until we're ready for it to initialise.
30 * The primary core will update this flag using a hardware
31 * register AuxCoreBoot0.
32 */
33ENTRY(omap_secondary_startup)
34hold:	ldr	r12,=0x103
35	dsb
36	smc	#0			@ read from AuxCoreBoot0
37	mov	r0, r0, lsr #9
38	mrc	p15, 0, r4, c0, c0, 5
39	and	r4, r4, #0x0f
40	cmp	r0, r4
41	bne	hold
42
43	/*
44	 * we've been released from the wait loop,secondary_stack
45	 * should now contain the SVC stack for this core
46	 */
47	b	secondary_startup
48END(omap_secondary_startup)
49
50
51ENTRY(omap_modify_auxcoreboot0)
52	stmfd   sp!, {r1-r12, lr}
53	ldr	r12, =0x104
54	dsb
55	smc	#0
56	ldmfd   sp!, {r1-r12, pc}
57END(omap_modify_auxcoreboot0)
58
59ENTRY(omap_auxcoreboot_addr)
60	stmfd   sp!, {r2-r12, lr}
61	ldr	r12, =0x105
62	dsb
63	smc	#0
64	ldmfd   sp!, {r2-r12, pc}
65END(omap_auxcoreboot_addr)
66