1/*
2 * Secondary CPU startup routine source file.
3 *
4 * Copyright (C) 2009 Texas Instruments, Inc.
5 *
6 * Author:
7 *      Santosh Shilimkar <santosh.shilimkar@ti.com>
8 *
9 * Interface functions needed for the SMP. This file is based on arm
10 * realview smp platform.
11 * Copyright (c) 2003 ARM Limited.
12 *
13 * This program is free software,you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/linkage.h>
19#include <linux/init.h>
20
21#include "omap44xx.h"
22
23	__CPUINIT
24
25/* Physical address needed since MMU not enabled yet on secondary core */
26#define AUX_CORE_BOOT0_PA			0x48281800
27
28/*
29 * OMAP5 specific entry point for secondary CPU to jump from ROM
30 * code.  This routine also provides a holding flag into which
31 * secondary core is held until we're ready for it to initialise.
32 * The primary core will update this flag using a hardware
33+ * register AuxCoreBoot0.
34 */
35ENTRY(omap5_secondary_startup)
36wait:	ldr	r2, =AUX_CORE_BOOT0_PA	@ read from AuxCoreBoot0
37	ldr	r0, [r2]
38	mov	r0, r0, lsr #5
39	mrc	p15, 0, r4, c0, c0, 5
40	and	r4, r4, #0x0f
41	cmp	r0, r4
42	bne	wait
43	b	secondary_startup
44END(omap5_secondary_startup)
45/*
46 * OMAP4 specific entry point for secondary CPU to jump from ROM
47 * code.  This routine also provides a holding flag into which
48 * secondary core is held until we're ready for it to initialise.
49 * The primary core will update this flag using a hardware
50 * register AuxCoreBoot0.
51 */
52ENTRY(omap_secondary_startup)
53hold:	ldr	r12,=0x103
54	dsb
55	smc	#0			@ read from AuxCoreBoot0
56	mov	r0, r0, lsr #9
57	mrc	p15, 0, r4, c0, c0, 5
58	and	r4, r4, #0x0f
59	cmp	r0, r4
60	bne	hold
61
62	/*
63	 * we've been released from the wait loop,secondary_stack
64	 * should now contain the SVC stack for this core
65	 */
66	b	secondary_startup
67ENDPROC(omap_secondary_startup)
68
69ENTRY(omap_secondary_startup_4460)
70hold_2:	ldr	r12,=0x103
71	dsb
72	smc	#0			@ read from AuxCoreBoot0
73	mov	r0, r0, lsr #9
74	mrc	p15, 0, r4, c0, c0, 5
75	and	r4, r4, #0x0f
76	cmp	r0, r4
77	bne	hold_2
78
79	/*
80	 * GIC distributor control register has changed between
81	 * CortexA9 r1pX and r2pX. The Control Register secure
82	 * banked version is now composed of 2 bits:
83	 * bit 0 == Secure Enable
84	 * bit 1 == Non-Secure Enable
85	 * The Non-Secure banked register has not changed
86	 * Because the ROM Code is based on the r1pX GIC, the CPU1
87	 * GIC restoration will cause a problem to CPU0 Non-Secure SW.
88	 * The workaround must be:
89	 * 1) Before doing the CPU1 wakeup, CPU0 must disable
90	 * the GIC distributor
91	 * 2) CPU1 must re-enable the GIC distributor on
92	 * it's wakeup path.
93	 */
94	ldr	r1, =OMAP44XX_GIC_DIST_BASE
95	ldr	r0, [r1]
96	orr	r0, #1
97	str	r0, [r1]
98
99	/*
100	 * we've been released from the wait loop,secondary_stack
101	 * should now contain the SVC stack for this core
102	 */
103	b	secondary_startup
104ENDPROC(omap_secondary_startup_4460)
105