1/*
2 * Secondary CPU startup routine source file.
3 *
4 * Copyright (C) 2009-2014 Texas Instruments, Inc.
5 *
6 * Author:
7 *      Santosh Shilimkar <santosh.shilimkar@ti.com>
8 *
9 * Interface functions needed for the SMP. This file is based on arm
10 * realview smp platform.
11 * Copyright (c) 2003 ARM Limited.
12 *
13 * This program is free software,you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/linkage.h>
19#include <linux/init.h>
20
21#include "omap44xx.h"
22
23/* Physical address needed since MMU not enabled yet on secondary core */
24#define AUX_CORE_BOOT0_PA			0x48281800
25#define API_HYP_ENTRY				0x102
26
27/*
28 * OMAP5 specific entry point for secondary CPU to jump from ROM
29 * code.  This routine also provides a holding flag into which
30 * secondary core is held until we're ready for it to initialise.
31 * The primary core will update this flag using a hardware
32 * register AuxCoreBoot0.
33 */
34ENTRY(omap5_secondary_startup)
35wait:	ldr	r2, =AUX_CORE_BOOT0_PA	@ read from AuxCoreBoot0
36	ldr	r0, [r2]
37	mov	r0, r0, lsr #5
38	mrc	p15, 0, r4, c0, c0, 5
39	and	r4, r4, #0x0f
40	cmp	r0, r4
41	bne	wait
42	b	secondary_startup
43ENDPROC(omap5_secondary_startup)
44/*
45 * Same as omap5_secondary_startup except we call into the ROM to
46 * enable HYP mode first.  This is called instead of
47 * omap5_secondary_startup if the primary CPU was put into HYP mode by
48 * the boot loader.
49 */
50ENTRY(omap5_secondary_hyp_startup)
51wait_2:	ldr	r2, =AUX_CORE_BOOT0_PA	@ read from AuxCoreBoot0
52	ldr	r0, [r2]
53	mov	r0, r0, lsr #5
54	mrc	p15, 0, r4, c0, c0, 5
55	and	r4, r4, #0x0f
56	cmp	r0, r4
57	bne	wait_2
58	ldr	r12, =API_HYP_ENTRY
59	adr	r0, hyp_boot
60	smc	#0
61hyp_boot:
62	b	secondary_startup
63ENDPROC(omap5_secondary_hyp_startup)
64/*
65 * OMAP4 specific entry point for secondary CPU to jump from ROM
66 * code.  This routine also provides a holding flag into which
67 * secondary core is held until we're ready for it to initialise.
68 * The primary core will update this flag using a hardware
69 * register AuxCoreBoot0.
70 */
71ENTRY(omap4_secondary_startup)
72hold:	ldr	r12,=0x103
73	dsb
74	smc	#0			@ read from AuxCoreBoot0
75	mov	r0, r0, lsr #9
76	mrc	p15, 0, r4, c0, c0, 5
77	and	r4, r4, #0x0f
78	cmp	r0, r4
79	bne	hold
80
81	/*
82	 * we've been released from the wait loop,secondary_stack
83	 * should now contain the SVC stack for this core
84	 */
85	b	secondary_startup
86ENDPROC(omap4_secondary_startup)
87
88ENTRY(omap4460_secondary_startup)
89hold_2:	ldr	r12,=0x103
90	dsb
91	smc	#0			@ read from AuxCoreBoot0
92	mov	r0, r0, lsr #9
93	mrc	p15, 0, r4, c0, c0, 5
94	and	r4, r4, #0x0f
95	cmp	r0, r4
96	bne	hold_2
97
98	/*
99	 * GIC distributor control register has changed between
100	 * CortexA9 r1pX and r2pX. The Control Register secure
101	 * banked version is now composed of 2 bits:
102	 * bit 0 == Secure Enable
103	 * bit 1 == Non-Secure Enable
104	 * The Non-Secure banked register has not changed
105	 * Because the ROM Code is based on the r1pX GIC, the CPU1
106	 * GIC restoration will cause a problem to CPU0 Non-Secure SW.
107	 * The workaround must be:
108	 * 1) Before doing the CPU1 wakeup, CPU0 must disable
109	 * the GIC distributor
110	 * 2) CPU1 must re-enable the GIC distributor on
111	 * it's wakeup path.
112	 */
113	ldr	r1, =OMAP44XX_GIC_DIST_BASE
114	ldr	r0, [r1]
115	orr	r0, #1
116	str	r0, [r1]
117
118	/*
119	 * we've been released from the wait loop,secondary_stack
120	 * should now contain the SVC stack for this core
121	 */
122	b	secondary_startup
123ENDPROC(omap4460_secondary_startup)
124