1 /* 2 * MSDI IP block reset 3 * 4 * Copyright (C) 2012 Texas Instruments, Inc. 5 * Paul Walmsley 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * version 2 as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 19 * 02110-1301 USA 20 * 21 * XXX What about pad muxing? 22 */ 23 24 #include <linux/kernel.h> 25 #include <linux/err.h> 26 27 #include <plat/omap_hwmod.h> 28 #include <plat/omap_device.h> 29 #include <plat/mmc.h> 30 31 #include "common.h" 32 #include "control.h" 33 #include "mux.h" 34 35 /* 36 * MSDI_CON_OFFSET: offset in bytes of the MSDI IP block's CON register 37 * from the IP block's base address 38 */ 39 #define MSDI_CON_OFFSET 0x0c 40 41 /* Register bitfields in the CON register */ 42 #define MSDI_CON_POW_MASK BIT(11) 43 #define MSDI_CON_CLKD_MASK (0x3f << 0) 44 #define MSDI_CON_CLKD_SHIFT 0 45 46 /* Maximum microseconds to wait for OMAP module to softreset */ 47 #define MAX_MODULE_SOFTRESET_WAIT 10000 48 49 /* MSDI_TARGET_RESET_CLKD: clock divisor to use throughout the reset */ 50 #define MSDI_TARGET_RESET_CLKD 0x3ff 51 52 /** 53 * omap_msdi_reset - reset the MSDI IP block 54 * @oh: struct omap_hwmod * 55 * 56 * The MSDI IP block on OMAP2420 has to have both the POW and CLKD 57 * fields set inside its CON register for a reset to complete 58 * successfully. This is not documented in the TRM. For CLKD, we use 59 * the value that results in the lowest possible clock rate, to attempt 60 * to avoid disturbing any cards. 61 */ 62 int omap_msdi_reset(struct omap_hwmod *oh) 63 { 64 u16 v = 0; 65 int c = 0; 66 67 /* Write to the SOFTRESET bit */ 68 omap_hwmod_softreset(oh); 69 70 /* Enable the MSDI core and internal clock */ 71 v |= MSDI_CON_POW_MASK; 72 v |= MSDI_TARGET_RESET_CLKD << MSDI_CON_CLKD_SHIFT; 73 omap_hwmod_write(v, oh, MSDI_CON_OFFSET); 74 75 /* Poll on RESETDONE bit */ 76 omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs) 77 & SYSS_RESETDONE_MASK), 78 MAX_MODULE_SOFTRESET_WAIT, c); 79 80 if (c == MAX_MODULE_SOFTRESET_WAIT) 81 pr_warning("%s: %s: softreset failed (waited %d usec)\n", 82 __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT); 83 else 84 pr_debug("%s: %s: softreset in %d usec\n", __func__, 85 oh->name, c); 86 87 /* Disable the MSDI internal clock */ 88 v &= ~MSDI_CON_CLKD_MASK; 89 omap_hwmod_write(v, oh, MSDI_CON_OFFSET); 90 91 return 0; 92 } 93 94 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) 95 96 static inline void omap242x_mmc_mux(struct omap_mmc_platform_data 97 *mmc_controller) 98 { 99 if ((mmc_controller->slots[0].switch_pin > 0) && \ 100 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES)) 101 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin, 102 OMAP_PIN_INPUT_PULLUP); 103 if ((mmc_controller->slots[0].gpio_wp > 0) && \ 104 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES)) 105 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp, 106 OMAP_PIN_INPUT_PULLUP); 107 108 omap_mux_init_signal("sdmmc_cmd", 0); 109 omap_mux_init_signal("sdmmc_clki", 0); 110 omap_mux_init_signal("sdmmc_clko", 0); 111 omap_mux_init_signal("sdmmc_dat0", 0); 112 omap_mux_init_signal("sdmmc_dat_dir0", 0); 113 omap_mux_init_signal("sdmmc_cmd_dir", 0); 114 if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) { 115 omap_mux_init_signal("sdmmc_dat1", 0); 116 omap_mux_init_signal("sdmmc_dat2", 0); 117 omap_mux_init_signal("sdmmc_dat3", 0); 118 omap_mux_init_signal("sdmmc_dat_dir1", 0); 119 omap_mux_init_signal("sdmmc_dat_dir2", 0); 120 omap_mux_init_signal("sdmmc_dat_dir3", 0); 121 } 122 123 /* 124 * Use internal loop-back in MMC/SDIO Module Input Clock 125 * selection 126 */ 127 if (mmc_controller->slots[0].internal_clock) { 128 u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); 129 v |= (1 << 24); 130 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); 131 } 132 } 133 134 void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data) 135 { 136 struct platform_device *pdev; 137 struct omap_hwmod *oh; 138 int id = 0; 139 char *oh_name = "msdi1"; 140 char *dev_name = "mmci-omap"; 141 142 if (!mmc_data[0]) { 143 pr_err("%s fails: Incomplete platform data\n", __func__); 144 return; 145 } 146 147 omap242x_mmc_mux(mmc_data[0]); 148 149 oh = omap_hwmod_lookup(oh_name); 150 if (!oh) { 151 pr_err("Could not look up %s\n", oh_name); 152 return; 153 } 154 pdev = omap_device_build(dev_name, id, oh, mmc_data[0], 155 sizeof(struct omap_mmc_platform_data), NULL, 0, 0); 156 if (IS_ERR(pdev)) 157 WARN(1, "Can'd build omap_device for %s:%s.\n", 158 dev_name, oh->name); 159 } 160 161 #endif 162