1 /* 2 * linux/arch/arm/mach-omap2/io.c 3 * 4 * OMAP2 I/O mapping code 5 * 6 * Copyright (C) 2005 Nokia Corporation 7 * Copyright (C) 2007-2009 Texas Instruments 8 * 9 * Author: 10 * Juha Yrjola <juha.yrjola@nokia.com> 11 * Syed Khasim <x0khasim@ti.com> 12 * 13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License version 2 as 17 * published by the Free Software Foundation. 18 */ 19 #include <linux/module.h> 20 #include <linux/kernel.h> 21 #include <linux/init.h> 22 #include <linux/io.h> 23 #include <linux/clk.h> 24 25 #include <asm/tlb.h> 26 #include <asm/mach/map.h> 27 28 #include <linux/omap-dma.h> 29 30 #include "omap_hwmod.h" 31 #include "soc.h" 32 #include "iomap.h" 33 #include "voltage.h" 34 #include "powerdomain.h" 35 #include "clockdomain.h" 36 #include "common.h" 37 #include "clock.h" 38 #include "clock2xxx.h" 39 #include "clock3xxx.h" 40 #include "clock44xx.h" 41 #include "omap-pm.h" 42 #include "sdrc.h" 43 #include "control.h" 44 #include "serial.h" 45 #include "sram.h" 46 #include "cm2xxx.h" 47 #include "cm3xxx.h" 48 #include "cm33xx.h" 49 #include "cm44xx.h" 50 #include "prm.h" 51 #include "cm.h" 52 #include "prcm_mpu44xx.h" 53 #include "prminst44xx.h" 54 #include "prm2xxx.h" 55 #include "prm3xxx.h" 56 #include "prm33xx.h" 57 #include "prm44xx.h" 58 #include "opp2xxx.h" 59 60 /* 61 * omap_clk_soc_init: points to a function that does the SoC-specific 62 * clock initializations 63 */ 64 static int (*omap_clk_soc_init)(void); 65 66 /* 67 * The machine specific code may provide the extra mapping besides the 68 * default mapping provided here. 69 */ 70 71 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430) 72 static struct map_desc omap24xx_io_desc[] __initdata = { 73 { 74 .virtual = L3_24XX_VIRT, 75 .pfn = __phys_to_pfn(L3_24XX_PHYS), 76 .length = L3_24XX_SIZE, 77 .type = MT_DEVICE 78 }, 79 { 80 .virtual = L4_24XX_VIRT, 81 .pfn = __phys_to_pfn(L4_24XX_PHYS), 82 .length = L4_24XX_SIZE, 83 .type = MT_DEVICE 84 }, 85 }; 86 87 #ifdef CONFIG_SOC_OMAP2420 88 static struct map_desc omap242x_io_desc[] __initdata = { 89 { 90 .virtual = DSP_MEM_2420_VIRT, 91 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS), 92 .length = DSP_MEM_2420_SIZE, 93 .type = MT_DEVICE 94 }, 95 { 96 .virtual = DSP_IPI_2420_VIRT, 97 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS), 98 .length = DSP_IPI_2420_SIZE, 99 .type = MT_DEVICE 100 }, 101 { 102 .virtual = DSP_MMU_2420_VIRT, 103 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS), 104 .length = DSP_MMU_2420_SIZE, 105 .type = MT_DEVICE 106 }, 107 }; 108 109 #endif 110 111 #ifdef CONFIG_SOC_OMAP2430 112 static struct map_desc omap243x_io_desc[] __initdata = { 113 { 114 .virtual = L4_WK_243X_VIRT, 115 .pfn = __phys_to_pfn(L4_WK_243X_PHYS), 116 .length = L4_WK_243X_SIZE, 117 .type = MT_DEVICE 118 }, 119 { 120 .virtual = OMAP243X_GPMC_VIRT, 121 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS), 122 .length = OMAP243X_GPMC_SIZE, 123 .type = MT_DEVICE 124 }, 125 { 126 .virtual = OMAP243X_SDRC_VIRT, 127 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS), 128 .length = OMAP243X_SDRC_SIZE, 129 .type = MT_DEVICE 130 }, 131 { 132 .virtual = OMAP243X_SMS_VIRT, 133 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS), 134 .length = OMAP243X_SMS_SIZE, 135 .type = MT_DEVICE 136 }, 137 }; 138 #endif 139 #endif 140 141 #ifdef CONFIG_ARCH_OMAP3 142 static struct map_desc omap34xx_io_desc[] __initdata = { 143 { 144 .virtual = L3_34XX_VIRT, 145 .pfn = __phys_to_pfn(L3_34XX_PHYS), 146 .length = L3_34XX_SIZE, 147 .type = MT_DEVICE 148 }, 149 { 150 .virtual = L4_34XX_VIRT, 151 .pfn = __phys_to_pfn(L4_34XX_PHYS), 152 .length = L4_34XX_SIZE, 153 .type = MT_DEVICE 154 }, 155 { 156 .virtual = OMAP34XX_GPMC_VIRT, 157 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS), 158 .length = OMAP34XX_GPMC_SIZE, 159 .type = MT_DEVICE 160 }, 161 { 162 .virtual = OMAP343X_SMS_VIRT, 163 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS), 164 .length = OMAP343X_SMS_SIZE, 165 .type = MT_DEVICE 166 }, 167 { 168 .virtual = OMAP343X_SDRC_VIRT, 169 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS), 170 .length = OMAP343X_SDRC_SIZE, 171 .type = MT_DEVICE 172 }, 173 { 174 .virtual = L4_PER_34XX_VIRT, 175 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS), 176 .length = L4_PER_34XX_SIZE, 177 .type = MT_DEVICE 178 }, 179 { 180 .virtual = L4_EMU_34XX_VIRT, 181 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS), 182 .length = L4_EMU_34XX_SIZE, 183 .type = MT_DEVICE 184 }, 185 }; 186 #endif 187 188 #ifdef CONFIG_SOC_TI81XX 189 static struct map_desc omapti81xx_io_desc[] __initdata = { 190 { 191 .virtual = L4_34XX_VIRT, 192 .pfn = __phys_to_pfn(L4_34XX_PHYS), 193 .length = L4_34XX_SIZE, 194 .type = MT_DEVICE 195 } 196 }; 197 #endif 198 199 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) 200 static struct map_desc omapam33xx_io_desc[] __initdata = { 201 { 202 .virtual = L4_34XX_VIRT, 203 .pfn = __phys_to_pfn(L4_34XX_PHYS), 204 .length = L4_34XX_SIZE, 205 .type = MT_DEVICE 206 }, 207 { 208 .virtual = L4_WK_AM33XX_VIRT, 209 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS), 210 .length = L4_WK_AM33XX_SIZE, 211 .type = MT_DEVICE 212 } 213 }; 214 #endif 215 216 #ifdef CONFIG_ARCH_OMAP4 217 static struct map_desc omap44xx_io_desc[] __initdata = { 218 { 219 .virtual = L3_44XX_VIRT, 220 .pfn = __phys_to_pfn(L3_44XX_PHYS), 221 .length = L3_44XX_SIZE, 222 .type = MT_DEVICE, 223 }, 224 { 225 .virtual = L4_44XX_VIRT, 226 .pfn = __phys_to_pfn(L4_44XX_PHYS), 227 .length = L4_44XX_SIZE, 228 .type = MT_DEVICE, 229 }, 230 { 231 .virtual = L4_PER_44XX_VIRT, 232 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS), 233 .length = L4_PER_44XX_SIZE, 234 .type = MT_DEVICE, 235 }, 236 }; 237 #endif 238 239 #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) 240 static struct map_desc omap54xx_io_desc[] __initdata = { 241 { 242 .virtual = L3_54XX_VIRT, 243 .pfn = __phys_to_pfn(L3_54XX_PHYS), 244 .length = L3_54XX_SIZE, 245 .type = MT_DEVICE, 246 }, 247 { 248 .virtual = L4_54XX_VIRT, 249 .pfn = __phys_to_pfn(L4_54XX_PHYS), 250 .length = L4_54XX_SIZE, 251 .type = MT_DEVICE, 252 }, 253 { 254 .virtual = L4_WK_54XX_VIRT, 255 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS), 256 .length = L4_WK_54XX_SIZE, 257 .type = MT_DEVICE, 258 }, 259 { 260 .virtual = L4_PER_54XX_VIRT, 261 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS), 262 .length = L4_PER_54XX_SIZE, 263 .type = MT_DEVICE, 264 }, 265 }; 266 #endif 267 268 #ifdef CONFIG_SOC_OMAP2420 269 void __init omap242x_map_io(void) 270 { 271 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); 272 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc)); 273 } 274 #endif 275 276 #ifdef CONFIG_SOC_OMAP2430 277 void __init omap243x_map_io(void) 278 { 279 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); 280 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc)); 281 } 282 #endif 283 284 #ifdef CONFIG_ARCH_OMAP3 285 void __init omap3_map_io(void) 286 { 287 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc)); 288 } 289 #endif 290 291 #ifdef CONFIG_SOC_TI81XX 292 void __init ti81xx_map_io(void) 293 { 294 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc)); 295 } 296 #endif 297 298 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) 299 void __init am33xx_map_io(void) 300 { 301 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc)); 302 } 303 #endif 304 305 #ifdef CONFIG_ARCH_OMAP4 306 void __init omap4_map_io(void) 307 { 308 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc)); 309 omap_barriers_init(); 310 } 311 #endif 312 313 #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) 314 void __init omap5_map_io(void) 315 { 316 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); 317 omap_barriers_init(); 318 } 319 #endif 320 /* 321 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters 322 * 323 * Sets the CORE DPLL3 M2 divider to the same value that it's at 324 * currently. This has the effect of setting the SDRC SDRAM AC timing 325 * registers to the values currently defined by the kernel. Currently 326 * only defined for OMAP3; will return 0 if called on OMAP2. Returns 327 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2, 328 * or passes along the return value of clk_set_rate(). 329 */ 330 static int __init _omap2_init_reprogram_sdrc(void) 331 { 332 struct clk *dpll3_m2_ck; 333 int v = -EINVAL; 334 long rate; 335 336 if (!cpu_is_omap34xx()) 337 return 0; 338 339 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck"); 340 if (IS_ERR(dpll3_m2_ck)) 341 return -EINVAL; 342 343 rate = clk_get_rate(dpll3_m2_ck); 344 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate); 345 v = clk_set_rate(dpll3_m2_ck, rate); 346 if (v) 347 pr_err("dpll3_m2_clk rate change failed: %d\n", v); 348 349 clk_put(dpll3_m2_ck); 350 351 return v; 352 } 353 354 static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data) 355 { 356 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data); 357 } 358 359 static void __init omap_hwmod_init_postsetup(void) 360 { 361 u8 postsetup_state; 362 363 /* Set the default postsetup state for all hwmods */ 364 #ifdef CONFIG_PM 365 postsetup_state = _HWMOD_STATE_IDLE; 366 #else 367 postsetup_state = _HWMOD_STATE_ENABLED; 368 #endif 369 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state); 370 371 omap_pm_if_early_init(); 372 } 373 374 static void __init __maybe_unused omap_common_late_init(void) 375 { 376 omap_mux_late_init(); 377 omap2_common_pm_late_init(); 378 omap_soc_device_init(); 379 } 380 381 #ifdef CONFIG_SOC_OMAP2420 382 void __init omap2420_init_early(void) 383 { 384 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000)); 385 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE), 386 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE)); 387 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE), 388 NULL); 389 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE)); 390 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL); 391 omap2xxx_check_revision(); 392 omap2xxx_prm_init(); 393 omap2xxx_cm_init(); 394 omap2xxx_voltagedomains_init(); 395 omap242x_powerdomains_init(); 396 omap242x_clockdomains_init(); 397 omap2420_hwmod_init(); 398 omap_hwmod_init_postsetup(); 399 omap_clk_soc_init = omap2420_dt_clk_init; 400 rate_table = omap2420_rate_table; 401 } 402 403 void __init omap2420_init_late(void) 404 { 405 omap_common_late_init(); 406 omap2_pm_init(); 407 omap2_clk_enable_autoidle_all(); 408 } 409 #endif 410 411 #ifdef CONFIG_SOC_OMAP2430 412 void __init omap2430_init_early(void) 413 { 414 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000)); 415 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE), 416 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE)); 417 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE), 418 NULL); 419 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE)); 420 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL); 421 omap2xxx_check_revision(); 422 omap2xxx_prm_init(); 423 omap2xxx_cm_init(); 424 omap2xxx_voltagedomains_init(); 425 omap243x_powerdomains_init(); 426 omap243x_clockdomains_init(); 427 omap2430_hwmod_init(); 428 omap_hwmod_init_postsetup(); 429 omap_clk_soc_init = omap2430_dt_clk_init; 430 rate_table = omap2430_rate_table; 431 } 432 433 void __init omap2430_init_late(void) 434 { 435 omap_common_late_init(); 436 omap2_pm_init(); 437 omap2_clk_enable_autoidle_all(); 438 } 439 #endif 440 441 /* 442 * Currently only board-omap3beagle.c should call this because of the 443 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT. 444 */ 445 #ifdef CONFIG_ARCH_OMAP3 446 void __init omap3_init_early(void) 447 { 448 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000)); 449 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE), 450 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE)); 451 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE), 452 NULL); 453 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE)); 454 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL); 455 omap3xxx_check_revision(); 456 omap3xxx_check_features(); 457 omap3xxx_prm_init(); 458 omap3xxx_cm_init(); 459 omap3xxx_voltagedomains_init(); 460 omap3xxx_powerdomains_init(); 461 omap3xxx_clockdomains_init(); 462 omap3xxx_hwmod_init(); 463 omap_hwmod_init_postsetup(); 464 omap_clk_soc_init = omap3xxx_clk_init; 465 } 466 467 void __init omap3430_init_early(void) 468 { 469 omap3_init_early(); 470 if (of_have_populated_dt()) 471 omap_clk_soc_init = omap3430_dt_clk_init; 472 } 473 474 void __init omap35xx_init_early(void) 475 { 476 omap3_init_early(); 477 if (of_have_populated_dt()) 478 omap_clk_soc_init = omap3430_dt_clk_init; 479 } 480 481 void __init omap3630_init_early(void) 482 { 483 omap3_init_early(); 484 if (of_have_populated_dt()) 485 omap_clk_soc_init = omap3630_dt_clk_init; 486 } 487 488 void __init am35xx_init_early(void) 489 { 490 omap3_init_early(); 491 if (of_have_populated_dt()) 492 omap_clk_soc_init = am35xx_dt_clk_init; 493 } 494 495 void __init ti81xx_init_early(void) 496 { 497 omap2_set_globals_tap(OMAP343X_CLASS, 498 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); 499 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE), 500 NULL); 501 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE)); 502 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL); 503 omap3xxx_check_revision(); 504 ti81xx_check_features(); 505 omap3xxx_voltagedomains_init(); 506 omap3xxx_powerdomains_init(); 507 omap3xxx_clockdomains_init(); 508 omap3xxx_hwmod_init(); 509 omap_hwmod_init_postsetup(); 510 if (of_have_populated_dt()) 511 omap_clk_soc_init = ti81xx_dt_clk_init; 512 else 513 omap_clk_soc_init = omap3xxx_clk_init; 514 } 515 516 void __init omap3_init_late(void) 517 { 518 omap_common_late_init(); 519 omap3_pm_init(); 520 omap2_clk_enable_autoidle_all(); 521 } 522 523 void __init omap3430_init_late(void) 524 { 525 omap_common_late_init(); 526 omap3_pm_init(); 527 omap2_clk_enable_autoidle_all(); 528 } 529 530 void __init omap35xx_init_late(void) 531 { 532 omap_common_late_init(); 533 omap3_pm_init(); 534 omap2_clk_enable_autoidle_all(); 535 } 536 537 void __init omap3630_init_late(void) 538 { 539 omap_common_late_init(); 540 omap3_pm_init(); 541 omap2_clk_enable_autoidle_all(); 542 } 543 544 void __init am35xx_init_late(void) 545 { 546 omap_common_late_init(); 547 omap3_pm_init(); 548 omap2_clk_enable_autoidle_all(); 549 } 550 551 void __init ti81xx_init_late(void) 552 { 553 omap_common_late_init(); 554 omap3_pm_init(); 555 omap2_clk_enable_autoidle_all(); 556 } 557 #endif 558 559 #ifdef CONFIG_SOC_AM33XX 560 void __init am33xx_init_early(void) 561 { 562 omap2_set_globals_tap(AM335X_CLASS, 563 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); 564 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE), 565 NULL); 566 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE)); 567 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL); 568 omap3xxx_check_revision(); 569 am33xx_check_features(); 570 am33xx_prm_init(); 571 am33xx_cm_init(); 572 am33xx_powerdomains_init(); 573 am33xx_clockdomains_init(); 574 am33xx_hwmod_init(); 575 omap_hwmod_init_postsetup(); 576 omap_clk_soc_init = am33xx_dt_clk_init; 577 } 578 579 void __init am33xx_init_late(void) 580 { 581 omap_common_late_init(); 582 } 583 #endif 584 585 #ifdef CONFIG_SOC_AM43XX 586 void __init am43xx_init_early(void) 587 { 588 omap2_set_globals_tap(AM335X_CLASS, 589 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); 590 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE), 591 NULL); 592 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE)); 593 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL); 594 omap_prm_base_init(); 595 omap_cm_base_init(); 596 omap3xxx_check_revision(); 597 am33xx_check_features(); 598 omap44xx_prm_init(); 599 omap4_cm_init(); 600 am43xx_powerdomains_init(); 601 am43xx_clockdomains_init(); 602 am43xx_hwmod_init(); 603 omap_hwmod_init_postsetup(); 604 omap_l2_cache_init(); 605 omap_clk_soc_init = am43xx_dt_clk_init; 606 } 607 608 void __init am43xx_init_late(void) 609 { 610 omap_common_late_init(); 611 } 612 #endif 613 614 #ifdef CONFIG_ARCH_OMAP4 615 void __init omap4430_init_early(void) 616 { 617 omap2_set_globals_tap(OMAP443X_CLASS, 618 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE)); 619 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE), 620 OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE)); 621 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE)); 622 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE), 623 OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE)); 624 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE)); 625 omap_prm_base_init(); 626 omap_cm_base_init(); 627 omap4xxx_check_revision(); 628 omap4xxx_check_features(); 629 omap4_cm_init(); 630 omap4_pm_init_early(); 631 omap44xx_prm_init(); 632 omap44xx_voltagedomains_init(); 633 omap44xx_powerdomains_init(); 634 omap44xx_clockdomains_init(); 635 omap44xx_hwmod_init(); 636 omap_hwmod_init_postsetup(); 637 omap_l2_cache_init(); 638 omap_clk_soc_init = omap4xxx_dt_clk_init; 639 } 640 641 void __init omap4430_init_late(void) 642 { 643 omap_common_late_init(); 644 omap4_pm_init(); 645 omap2_clk_enable_autoidle_all(); 646 } 647 #endif 648 649 #ifdef CONFIG_SOC_OMAP5 650 void __init omap5_init_early(void) 651 { 652 omap2_set_globals_tap(OMAP54XX_CLASS, 653 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE)); 654 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE), 655 OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE)); 656 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE)); 657 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE), 658 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE)); 659 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); 660 omap4_pm_init_early(); 661 omap_prm_base_init(); 662 omap_cm_base_init(); 663 omap44xx_prm_init(); 664 omap5xxx_check_revision(); 665 omap4_cm_init(); 666 omap54xx_voltagedomains_init(); 667 omap54xx_powerdomains_init(); 668 omap54xx_clockdomains_init(); 669 omap54xx_hwmod_init(); 670 omap_hwmod_init_postsetup(); 671 omap_clk_soc_init = omap5xxx_dt_clk_init; 672 } 673 674 void __init omap5_init_late(void) 675 { 676 omap_common_late_init(); 677 omap4_pm_init(); 678 omap2_clk_enable_autoidle_all(); 679 } 680 #endif 681 682 #ifdef CONFIG_SOC_DRA7XX 683 void __init dra7xx_init_early(void) 684 { 685 omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE)); 686 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE), 687 OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE)); 688 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE)); 689 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE), 690 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE)); 691 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); 692 omap4_pm_init_early(); 693 omap_prm_base_init(); 694 omap_cm_base_init(); 695 omap44xx_prm_init(); 696 dra7xxx_check_revision(); 697 omap4_cm_init(); 698 dra7xx_powerdomains_init(); 699 dra7xx_clockdomains_init(); 700 dra7xx_hwmod_init(); 701 omap_hwmod_init_postsetup(); 702 omap_clk_soc_init = dra7xx_dt_clk_init; 703 } 704 705 void __init dra7xx_init_late(void) 706 { 707 omap_common_late_init(); 708 omap4_pm_init(); 709 omap2_clk_enable_autoidle_all(); 710 } 711 #endif 712 713 714 void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, 715 struct omap_sdrc_params *sdrc_cs1) 716 { 717 omap_sram_init(); 718 719 if (cpu_is_omap24xx() || omap3_has_sdrc()) { 720 omap2_sdrc_init(sdrc_cs0, sdrc_cs1); 721 _omap2_init_reprogram_sdrc(); 722 } 723 } 724 725 int __init omap_clk_init(void) 726 { 727 int ret = 0; 728 729 if (!omap_clk_soc_init) 730 return 0; 731 732 ti_clk_init_features(); 733 734 ret = of_prcm_init(); 735 if (ret) 736 return ret; 737 738 of_clk_init(NULL); 739 740 ti_dt_clk_init_retry_clks(); 741 742 ti_dt_clockdomains_setup(); 743 744 ret = omap_clk_soc_init(); 745 746 return ret; 747 } 748