1 /* 2 * linux/arch/arm/mach-omap2/io.c 3 * 4 * OMAP2 I/O mapping code 5 * 6 * Copyright (C) 2005 Nokia Corporation 7 * Copyright (C) 2007-2009 Texas Instruments 8 * 9 * Author: 10 * Juha Yrjola <juha.yrjola@nokia.com> 11 * Syed Khasim <x0khasim@ti.com> 12 * 13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License version 2 as 17 * published by the Free Software Foundation. 18 */ 19 #include <linux/module.h> 20 #include <linux/kernel.h> 21 #include <linux/init.h> 22 #include <linux/io.h> 23 #include <linux/clk.h> 24 25 #include <asm/tlb.h> 26 #include <asm/mach/map.h> 27 28 #include <plat/sram.h> 29 #include <plat/sdrc.h> 30 #include <plat/serial.h> 31 #include <plat/omap-pm.h> 32 #include <plat/omap_hwmod.h> 33 #include <plat/multi.h> 34 #include <plat/dma.h> 35 36 #include "iomap.h" 37 #include "voltage.h" 38 #include "powerdomain.h" 39 #include "clockdomain.h" 40 #include "common.h" 41 #include "clock.h" 42 #include "clock2xxx.h" 43 #include "clock3xxx.h" 44 #include "clock44xx.h" 45 46 /* 47 * The machine specific code may provide the extra mapping besides the 48 * default mapping provided here. 49 */ 50 51 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430) 52 static struct map_desc omap24xx_io_desc[] __initdata = { 53 { 54 .virtual = L3_24XX_VIRT, 55 .pfn = __phys_to_pfn(L3_24XX_PHYS), 56 .length = L3_24XX_SIZE, 57 .type = MT_DEVICE 58 }, 59 { 60 .virtual = L4_24XX_VIRT, 61 .pfn = __phys_to_pfn(L4_24XX_PHYS), 62 .length = L4_24XX_SIZE, 63 .type = MT_DEVICE 64 }, 65 }; 66 67 #ifdef CONFIG_SOC_OMAP2420 68 static struct map_desc omap242x_io_desc[] __initdata = { 69 { 70 .virtual = DSP_MEM_2420_VIRT, 71 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS), 72 .length = DSP_MEM_2420_SIZE, 73 .type = MT_DEVICE 74 }, 75 { 76 .virtual = DSP_IPI_2420_VIRT, 77 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS), 78 .length = DSP_IPI_2420_SIZE, 79 .type = MT_DEVICE 80 }, 81 { 82 .virtual = DSP_MMU_2420_VIRT, 83 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS), 84 .length = DSP_MMU_2420_SIZE, 85 .type = MT_DEVICE 86 }, 87 }; 88 89 #endif 90 91 #ifdef CONFIG_SOC_OMAP2430 92 static struct map_desc omap243x_io_desc[] __initdata = { 93 { 94 .virtual = L4_WK_243X_VIRT, 95 .pfn = __phys_to_pfn(L4_WK_243X_PHYS), 96 .length = L4_WK_243X_SIZE, 97 .type = MT_DEVICE 98 }, 99 { 100 .virtual = OMAP243X_GPMC_VIRT, 101 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS), 102 .length = OMAP243X_GPMC_SIZE, 103 .type = MT_DEVICE 104 }, 105 { 106 .virtual = OMAP243X_SDRC_VIRT, 107 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS), 108 .length = OMAP243X_SDRC_SIZE, 109 .type = MT_DEVICE 110 }, 111 { 112 .virtual = OMAP243X_SMS_VIRT, 113 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS), 114 .length = OMAP243X_SMS_SIZE, 115 .type = MT_DEVICE 116 }, 117 }; 118 #endif 119 #endif 120 121 #ifdef CONFIG_ARCH_OMAP3 122 static struct map_desc omap34xx_io_desc[] __initdata = { 123 { 124 .virtual = L3_34XX_VIRT, 125 .pfn = __phys_to_pfn(L3_34XX_PHYS), 126 .length = L3_34XX_SIZE, 127 .type = MT_DEVICE 128 }, 129 { 130 .virtual = L4_34XX_VIRT, 131 .pfn = __phys_to_pfn(L4_34XX_PHYS), 132 .length = L4_34XX_SIZE, 133 .type = MT_DEVICE 134 }, 135 { 136 .virtual = OMAP34XX_GPMC_VIRT, 137 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS), 138 .length = OMAP34XX_GPMC_SIZE, 139 .type = MT_DEVICE 140 }, 141 { 142 .virtual = OMAP343X_SMS_VIRT, 143 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS), 144 .length = OMAP343X_SMS_SIZE, 145 .type = MT_DEVICE 146 }, 147 { 148 .virtual = OMAP343X_SDRC_VIRT, 149 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS), 150 .length = OMAP343X_SDRC_SIZE, 151 .type = MT_DEVICE 152 }, 153 { 154 .virtual = L4_PER_34XX_VIRT, 155 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS), 156 .length = L4_PER_34XX_SIZE, 157 .type = MT_DEVICE 158 }, 159 { 160 .virtual = L4_EMU_34XX_VIRT, 161 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS), 162 .length = L4_EMU_34XX_SIZE, 163 .type = MT_DEVICE 164 }, 165 #if defined(CONFIG_DEBUG_LL) && \ 166 (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3)) 167 { 168 .virtual = ZOOM_UART_VIRT, 169 .pfn = __phys_to_pfn(ZOOM_UART_BASE), 170 .length = SZ_1M, 171 .type = MT_DEVICE 172 }, 173 #endif 174 }; 175 #endif 176 177 #ifdef CONFIG_SOC_TI81XX 178 static struct map_desc omapti81xx_io_desc[] __initdata = { 179 { 180 .virtual = L4_34XX_VIRT, 181 .pfn = __phys_to_pfn(L4_34XX_PHYS), 182 .length = L4_34XX_SIZE, 183 .type = MT_DEVICE 184 } 185 }; 186 #endif 187 188 #ifdef CONFIG_SOC_AM33XX 189 static struct map_desc omapam33xx_io_desc[] __initdata = { 190 { 191 .virtual = L4_34XX_VIRT, 192 .pfn = __phys_to_pfn(L4_34XX_PHYS), 193 .length = L4_34XX_SIZE, 194 .type = MT_DEVICE 195 }, 196 { 197 .virtual = L4_WK_AM33XX_VIRT, 198 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS), 199 .length = L4_WK_AM33XX_SIZE, 200 .type = MT_DEVICE 201 } 202 }; 203 #endif 204 205 #ifdef CONFIG_ARCH_OMAP4 206 static struct map_desc omap44xx_io_desc[] __initdata = { 207 { 208 .virtual = L3_44XX_VIRT, 209 .pfn = __phys_to_pfn(L3_44XX_PHYS), 210 .length = L3_44XX_SIZE, 211 .type = MT_DEVICE, 212 }, 213 { 214 .virtual = L4_44XX_VIRT, 215 .pfn = __phys_to_pfn(L4_44XX_PHYS), 216 .length = L4_44XX_SIZE, 217 .type = MT_DEVICE, 218 }, 219 { 220 .virtual = L4_PER_44XX_VIRT, 221 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS), 222 .length = L4_PER_44XX_SIZE, 223 .type = MT_DEVICE, 224 }, 225 #ifdef CONFIG_OMAP4_ERRATA_I688 226 { 227 .virtual = OMAP4_SRAM_VA, 228 .pfn = __phys_to_pfn(OMAP4_SRAM_PA), 229 .length = PAGE_SIZE, 230 .type = MT_MEMORY_SO, 231 }, 232 #endif 233 234 }; 235 #endif 236 237 #ifdef CONFIG_SOC_OMAP5 238 static struct map_desc omap54xx_io_desc[] __initdata = { 239 { 240 .virtual = L3_54XX_VIRT, 241 .pfn = __phys_to_pfn(L3_54XX_PHYS), 242 .length = L3_54XX_SIZE, 243 .type = MT_DEVICE, 244 }, 245 { 246 .virtual = L4_54XX_VIRT, 247 .pfn = __phys_to_pfn(L4_54XX_PHYS), 248 .length = L4_54XX_SIZE, 249 .type = MT_DEVICE, 250 }, 251 { 252 .virtual = L4_WK_54XX_VIRT, 253 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS), 254 .length = L4_WK_54XX_SIZE, 255 .type = MT_DEVICE, 256 }, 257 { 258 .virtual = L4_PER_54XX_VIRT, 259 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS), 260 .length = L4_PER_54XX_SIZE, 261 .type = MT_DEVICE, 262 }, 263 }; 264 #endif 265 266 #ifdef CONFIG_SOC_OMAP2420 267 void __init omap242x_map_common_io(void) 268 { 269 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); 270 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc)); 271 } 272 #endif 273 274 #ifdef CONFIG_SOC_OMAP2430 275 void __init omap243x_map_common_io(void) 276 { 277 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); 278 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc)); 279 } 280 #endif 281 282 #ifdef CONFIG_ARCH_OMAP3 283 void __init omap34xx_map_common_io(void) 284 { 285 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc)); 286 } 287 #endif 288 289 #ifdef CONFIG_SOC_TI81XX 290 void __init omapti81xx_map_common_io(void) 291 { 292 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc)); 293 } 294 #endif 295 296 #ifdef CONFIG_SOC_AM33XX 297 void __init omapam33xx_map_common_io(void) 298 { 299 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc)); 300 } 301 #endif 302 303 #ifdef CONFIG_ARCH_OMAP4 304 void __init omap44xx_map_common_io(void) 305 { 306 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc)); 307 omap_barriers_init(); 308 } 309 #endif 310 311 #ifdef CONFIG_SOC_OMAP5 312 void __init omap5_map_common_io(void) 313 { 314 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); 315 } 316 #endif 317 /* 318 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters 319 * 320 * Sets the CORE DPLL3 M2 divider to the same value that it's at 321 * currently. This has the effect of setting the SDRC SDRAM AC timing 322 * registers to the values currently defined by the kernel. Currently 323 * only defined for OMAP3; will return 0 if called on OMAP2. Returns 324 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2, 325 * or passes along the return value of clk_set_rate(). 326 */ 327 static int __init _omap2_init_reprogram_sdrc(void) 328 { 329 struct clk *dpll3_m2_ck; 330 int v = -EINVAL; 331 long rate; 332 333 if (!cpu_is_omap34xx()) 334 return 0; 335 336 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck"); 337 if (IS_ERR(dpll3_m2_ck)) 338 return -EINVAL; 339 340 rate = clk_get_rate(dpll3_m2_ck); 341 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate); 342 v = clk_set_rate(dpll3_m2_ck, rate); 343 if (v) 344 pr_err("dpll3_m2_clk rate change failed: %d\n", v); 345 346 clk_put(dpll3_m2_ck); 347 348 return v; 349 } 350 351 static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data) 352 { 353 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data); 354 } 355 356 static void __init omap_common_init_early(void) 357 { 358 omap_init_consistent_dma_size(); 359 } 360 361 static void __init omap_hwmod_init_postsetup(void) 362 { 363 u8 postsetup_state; 364 365 /* Set the default postsetup state for all hwmods */ 366 #ifdef CONFIG_PM_RUNTIME 367 postsetup_state = _HWMOD_STATE_IDLE; 368 #else 369 postsetup_state = _HWMOD_STATE_ENABLED; 370 #endif 371 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state); 372 373 omap_pm_if_early_init(); 374 } 375 376 #ifdef CONFIG_SOC_OMAP2420 377 void __init omap2420_init_early(void) 378 { 379 omap2_set_globals_242x(); 380 omap2xxx_check_revision(); 381 omap_common_init_early(); 382 omap2xxx_voltagedomains_init(); 383 omap242x_powerdomains_init(); 384 omap242x_clockdomains_init(); 385 omap2420_hwmod_init(); 386 omap_hwmod_init_postsetup(); 387 omap2420_clk_init(); 388 } 389 390 void __init omap2420_init_late(void) 391 { 392 omap_mux_late_init(); 393 omap2_common_pm_late_init(); 394 omap2_pm_init(); 395 } 396 #endif 397 398 #ifdef CONFIG_SOC_OMAP2430 399 void __init omap2430_init_early(void) 400 { 401 omap2_set_globals_243x(); 402 omap2xxx_check_revision(); 403 omap_common_init_early(); 404 omap2xxx_voltagedomains_init(); 405 omap243x_powerdomains_init(); 406 omap243x_clockdomains_init(); 407 omap2430_hwmod_init(); 408 omap_hwmod_init_postsetup(); 409 omap2430_clk_init(); 410 } 411 412 void __init omap2430_init_late(void) 413 { 414 omap_mux_late_init(); 415 omap2_common_pm_late_init(); 416 omap2_pm_init(); 417 } 418 #endif 419 420 /* 421 * Currently only board-omap3beagle.c should call this because of the 422 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT. 423 */ 424 #ifdef CONFIG_ARCH_OMAP3 425 void __init omap3_init_early(void) 426 { 427 omap2_set_globals_3xxx(); 428 omap3xxx_check_revision(); 429 omap3xxx_check_features(); 430 omap_common_init_early(); 431 omap3xxx_voltagedomains_init(); 432 omap3xxx_powerdomains_init(); 433 omap3xxx_clockdomains_init(); 434 omap3xxx_hwmod_init(); 435 omap_hwmod_init_postsetup(); 436 omap3xxx_clk_init(); 437 } 438 439 void __init omap3430_init_early(void) 440 { 441 omap3_init_early(); 442 } 443 444 void __init omap35xx_init_early(void) 445 { 446 omap3_init_early(); 447 } 448 449 void __init omap3630_init_early(void) 450 { 451 omap3_init_early(); 452 } 453 454 void __init am35xx_init_early(void) 455 { 456 omap3_init_early(); 457 } 458 459 void __init ti81xx_init_early(void) 460 { 461 omap2_set_globals_ti81xx(); 462 omap3xxx_check_revision(); 463 ti81xx_check_features(); 464 omap_common_init_early(); 465 omap3xxx_voltagedomains_init(); 466 omap3xxx_powerdomains_init(); 467 omap3xxx_clockdomains_init(); 468 omap3xxx_hwmod_init(); 469 omap_hwmod_init_postsetup(); 470 omap3xxx_clk_init(); 471 } 472 473 void __init omap3_init_late(void) 474 { 475 omap_mux_late_init(); 476 omap2_common_pm_late_init(); 477 omap3_pm_init(); 478 } 479 480 void __init omap3430_init_late(void) 481 { 482 omap_mux_late_init(); 483 omap2_common_pm_late_init(); 484 omap3_pm_init(); 485 } 486 487 void __init omap35xx_init_late(void) 488 { 489 omap_mux_late_init(); 490 omap2_common_pm_late_init(); 491 omap3_pm_init(); 492 } 493 494 void __init omap3630_init_late(void) 495 { 496 omap_mux_late_init(); 497 omap2_common_pm_late_init(); 498 omap3_pm_init(); 499 } 500 501 void __init am35xx_init_late(void) 502 { 503 omap_mux_late_init(); 504 omap2_common_pm_late_init(); 505 omap3_pm_init(); 506 } 507 508 void __init ti81xx_init_late(void) 509 { 510 omap_mux_late_init(); 511 omap2_common_pm_late_init(); 512 omap3_pm_init(); 513 } 514 #endif 515 516 #ifdef CONFIG_SOC_AM33XX 517 void __init am33xx_init_early(void) 518 { 519 omap2_set_globals_am33xx(); 520 omap3xxx_check_revision(); 521 ti81xx_check_features(); 522 omap_common_init_early(); 523 am33xx_voltagedomains_init(); 524 am33xx_powerdomains_init(); 525 am33xx_clockdomains_init(); 526 am33xx_clk_init(); 527 } 528 #endif 529 530 #ifdef CONFIG_ARCH_OMAP4 531 void __init omap4430_init_early(void) 532 { 533 omap2_set_globals_443x(); 534 omap4xxx_check_revision(); 535 omap4xxx_check_features(); 536 omap_common_init_early(); 537 omap44xx_voltagedomains_init(); 538 omap44xx_powerdomains_init(); 539 omap44xx_clockdomains_init(); 540 omap44xx_hwmod_init(); 541 omap_hwmod_init_postsetup(); 542 omap4xxx_clk_init(); 543 } 544 545 void __init omap4430_init_late(void) 546 { 547 omap_mux_late_init(); 548 omap2_common_pm_late_init(); 549 omap4_pm_init(); 550 } 551 #endif 552 553 #ifdef CONFIG_SOC_OMAP5 554 void __init omap5_init_early(void) 555 { 556 omap2_set_globals_5xxx(); 557 omap5xxx_check_revision(); 558 omap_common_init_early(); 559 } 560 #endif 561 562 void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, 563 struct omap_sdrc_params *sdrc_cs1) 564 { 565 omap_sram_init(); 566 567 if (cpu_is_omap24xx() || omap3_has_sdrc()) { 568 omap2_sdrc_init(sdrc_cs0, sdrc_cs1); 569 _omap2_init_reprogram_sdrc(); 570 } 571 } 572