1 /* 2 * linux/arch/arm/mach-omap2/io.c 3 * 4 * OMAP2 I/O mapping code 5 * 6 * Copyright (C) 2005 Nokia Corporation 7 * Copyright (C) 2007-2009 Texas Instruments 8 * 9 * Author: 10 * Juha Yrjola <juha.yrjola@nokia.com> 11 * Syed Khasim <x0khasim@ti.com> 12 * 13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License version 2 as 17 * published by the Free Software Foundation. 18 */ 19 #include <linux/module.h> 20 #include <linux/kernel.h> 21 #include <linux/init.h> 22 #include <linux/io.h> 23 #include <linux/clk.h> 24 25 #include <asm/tlb.h> 26 #include <asm/mach/map.h> 27 28 #include <linux/omap-dma.h> 29 30 #include "omap_hwmod.h" 31 #include "soc.h" 32 #include "iomap.h" 33 #include "voltage.h" 34 #include "powerdomain.h" 35 #include "clockdomain.h" 36 #include "common.h" 37 #include "clock.h" 38 #include "clock2xxx.h" 39 #include "clock3xxx.h" 40 #include "clock44xx.h" 41 #include "omap-pm.h" 42 #include "sdrc.h" 43 #include "control.h" 44 #include "serial.h" 45 #include "sram.h" 46 #include "cm2xxx.h" 47 #include "cm3xxx.h" 48 #include "cm33xx.h" 49 #include "cm44xx.h" 50 #include "prm.h" 51 #include "cm.h" 52 #include "prcm_mpu44xx.h" 53 #include "prminst44xx.h" 54 #include "prm2xxx.h" 55 #include "prm3xxx.h" 56 #include "prm33xx.h" 57 #include "prm44xx.h" 58 #include "opp2xxx.h" 59 60 /* 61 * omap_clk_soc_init: points to a function that does the SoC-specific 62 * clock initializations 63 */ 64 static int (*omap_clk_soc_init)(void); 65 66 /* 67 * The machine specific code may provide the extra mapping besides the 68 * default mapping provided here. 69 */ 70 71 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430) 72 static struct map_desc omap24xx_io_desc[] __initdata = { 73 { 74 .virtual = L3_24XX_VIRT, 75 .pfn = __phys_to_pfn(L3_24XX_PHYS), 76 .length = L3_24XX_SIZE, 77 .type = MT_DEVICE 78 }, 79 { 80 .virtual = L4_24XX_VIRT, 81 .pfn = __phys_to_pfn(L4_24XX_PHYS), 82 .length = L4_24XX_SIZE, 83 .type = MT_DEVICE 84 }, 85 }; 86 87 #ifdef CONFIG_SOC_OMAP2420 88 static struct map_desc omap242x_io_desc[] __initdata = { 89 { 90 .virtual = DSP_MEM_2420_VIRT, 91 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS), 92 .length = DSP_MEM_2420_SIZE, 93 .type = MT_DEVICE 94 }, 95 { 96 .virtual = DSP_IPI_2420_VIRT, 97 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS), 98 .length = DSP_IPI_2420_SIZE, 99 .type = MT_DEVICE 100 }, 101 { 102 .virtual = DSP_MMU_2420_VIRT, 103 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS), 104 .length = DSP_MMU_2420_SIZE, 105 .type = MT_DEVICE 106 }, 107 }; 108 109 #endif 110 111 #ifdef CONFIG_SOC_OMAP2430 112 static struct map_desc omap243x_io_desc[] __initdata = { 113 { 114 .virtual = L4_WK_243X_VIRT, 115 .pfn = __phys_to_pfn(L4_WK_243X_PHYS), 116 .length = L4_WK_243X_SIZE, 117 .type = MT_DEVICE 118 }, 119 { 120 .virtual = OMAP243X_GPMC_VIRT, 121 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS), 122 .length = OMAP243X_GPMC_SIZE, 123 .type = MT_DEVICE 124 }, 125 { 126 .virtual = OMAP243X_SDRC_VIRT, 127 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS), 128 .length = OMAP243X_SDRC_SIZE, 129 .type = MT_DEVICE 130 }, 131 { 132 .virtual = OMAP243X_SMS_VIRT, 133 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS), 134 .length = OMAP243X_SMS_SIZE, 135 .type = MT_DEVICE 136 }, 137 }; 138 #endif 139 #endif 140 141 #ifdef CONFIG_ARCH_OMAP3 142 static struct map_desc omap34xx_io_desc[] __initdata = { 143 { 144 .virtual = L3_34XX_VIRT, 145 .pfn = __phys_to_pfn(L3_34XX_PHYS), 146 .length = L3_34XX_SIZE, 147 .type = MT_DEVICE 148 }, 149 { 150 .virtual = L4_34XX_VIRT, 151 .pfn = __phys_to_pfn(L4_34XX_PHYS), 152 .length = L4_34XX_SIZE, 153 .type = MT_DEVICE 154 }, 155 { 156 .virtual = OMAP34XX_GPMC_VIRT, 157 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS), 158 .length = OMAP34XX_GPMC_SIZE, 159 .type = MT_DEVICE 160 }, 161 { 162 .virtual = OMAP343X_SMS_VIRT, 163 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS), 164 .length = OMAP343X_SMS_SIZE, 165 .type = MT_DEVICE 166 }, 167 { 168 .virtual = OMAP343X_SDRC_VIRT, 169 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS), 170 .length = OMAP343X_SDRC_SIZE, 171 .type = MT_DEVICE 172 }, 173 { 174 .virtual = L4_PER_34XX_VIRT, 175 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS), 176 .length = L4_PER_34XX_SIZE, 177 .type = MT_DEVICE 178 }, 179 { 180 .virtual = L4_EMU_34XX_VIRT, 181 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS), 182 .length = L4_EMU_34XX_SIZE, 183 .type = MT_DEVICE 184 }, 185 }; 186 #endif 187 188 #ifdef CONFIG_SOC_TI81XX 189 static struct map_desc omapti81xx_io_desc[] __initdata = { 190 { 191 .virtual = L4_34XX_VIRT, 192 .pfn = __phys_to_pfn(L4_34XX_PHYS), 193 .length = L4_34XX_SIZE, 194 .type = MT_DEVICE 195 } 196 }; 197 #endif 198 199 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) 200 static struct map_desc omapam33xx_io_desc[] __initdata = { 201 { 202 .virtual = L4_34XX_VIRT, 203 .pfn = __phys_to_pfn(L4_34XX_PHYS), 204 .length = L4_34XX_SIZE, 205 .type = MT_DEVICE 206 }, 207 { 208 .virtual = L4_WK_AM33XX_VIRT, 209 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS), 210 .length = L4_WK_AM33XX_SIZE, 211 .type = MT_DEVICE 212 } 213 }; 214 #endif 215 216 #ifdef CONFIG_ARCH_OMAP4 217 static struct map_desc omap44xx_io_desc[] __initdata = { 218 { 219 .virtual = L3_44XX_VIRT, 220 .pfn = __phys_to_pfn(L3_44XX_PHYS), 221 .length = L3_44XX_SIZE, 222 .type = MT_DEVICE, 223 }, 224 { 225 .virtual = L4_44XX_VIRT, 226 .pfn = __phys_to_pfn(L4_44XX_PHYS), 227 .length = L4_44XX_SIZE, 228 .type = MT_DEVICE, 229 }, 230 { 231 .virtual = L4_PER_44XX_VIRT, 232 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS), 233 .length = L4_PER_44XX_SIZE, 234 .type = MT_DEVICE, 235 }, 236 }; 237 #endif 238 239 #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) 240 static struct map_desc omap54xx_io_desc[] __initdata = { 241 { 242 .virtual = L3_54XX_VIRT, 243 .pfn = __phys_to_pfn(L3_54XX_PHYS), 244 .length = L3_54XX_SIZE, 245 .type = MT_DEVICE, 246 }, 247 { 248 .virtual = L4_54XX_VIRT, 249 .pfn = __phys_to_pfn(L4_54XX_PHYS), 250 .length = L4_54XX_SIZE, 251 .type = MT_DEVICE, 252 }, 253 { 254 .virtual = L4_WK_54XX_VIRT, 255 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS), 256 .length = L4_WK_54XX_SIZE, 257 .type = MT_DEVICE, 258 }, 259 { 260 .virtual = L4_PER_54XX_VIRT, 261 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS), 262 .length = L4_PER_54XX_SIZE, 263 .type = MT_DEVICE, 264 }, 265 }; 266 #endif 267 268 #ifdef CONFIG_SOC_OMAP2420 269 void __init omap242x_map_io(void) 270 { 271 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); 272 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc)); 273 } 274 #endif 275 276 #ifdef CONFIG_SOC_OMAP2430 277 void __init omap243x_map_io(void) 278 { 279 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); 280 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc)); 281 } 282 #endif 283 284 #ifdef CONFIG_ARCH_OMAP3 285 void __init omap3_map_io(void) 286 { 287 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc)); 288 } 289 #endif 290 291 #ifdef CONFIG_SOC_TI81XX 292 void __init ti81xx_map_io(void) 293 { 294 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc)); 295 } 296 #endif 297 298 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) 299 void __init am33xx_map_io(void) 300 { 301 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc)); 302 } 303 #endif 304 305 #ifdef CONFIG_ARCH_OMAP4 306 void __init omap4_map_io(void) 307 { 308 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc)); 309 } 310 #endif 311 312 #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) 313 void __init omap5_map_io(void) 314 { 315 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); 316 } 317 #endif 318 /* 319 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters 320 * 321 * Sets the CORE DPLL3 M2 divider to the same value that it's at 322 * currently. This has the effect of setting the SDRC SDRAM AC timing 323 * registers to the values currently defined by the kernel. Currently 324 * only defined for OMAP3; will return 0 if called on OMAP2. Returns 325 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2, 326 * or passes along the return value of clk_set_rate(). 327 */ 328 static int __init _omap2_init_reprogram_sdrc(void) 329 { 330 struct clk *dpll3_m2_ck; 331 int v = -EINVAL; 332 long rate; 333 334 if (!cpu_is_omap34xx()) 335 return 0; 336 337 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck"); 338 if (IS_ERR(dpll3_m2_ck)) 339 return -EINVAL; 340 341 rate = clk_get_rate(dpll3_m2_ck); 342 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate); 343 v = clk_set_rate(dpll3_m2_ck, rate); 344 if (v) 345 pr_err("dpll3_m2_clk rate change failed: %d\n", v); 346 347 clk_put(dpll3_m2_ck); 348 349 return v; 350 } 351 352 static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data) 353 { 354 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data); 355 } 356 357 static void __init omap_hwmod_init_postsetup(void) 358 { 359 u8 postsetup_state; 360 361 /* Set the default postsetup state for all hwmods */ 362 #ifdef CONFIG_PM 363 postsetup_state = _HWMOD_STATE_IDLE; 364 #else 365 postsetup_state = _HWMOD_STATE_ENABLED; 366 #endif 367 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state); 368 369 omap_pm_if_early_init(); 370 } 371 372 static void __init __maybe_unused omap_common_late_init(void) 373 { 374 omap_mux_late_init(); 375 omap2_common_pm_late_init(); 376 omap_soc_device_init(); 377 } 378 379 #ifdef CONFIG_SOC_OMAP2420 380 void __init omap2420_init_early(void) 381 { 382 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000)); 383 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE), 384 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE)); 385 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE), 386 NULL); 387 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE)); 388 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL); 389 omap2xxx_check_revision(); 390 omap2xxx_prm_init(); 391 omap2xxx_cm_init(); 392 omap2xxx_voltagedomains_init(); 393 omap242x_powerdomains_init(); 394 omap242x_clockdomains_init(); 395 omap2420_hwmod_init(); 396 omap_hwmod_init_postsetup(); 397 omap_clk_soc_init = omap2420_dt_clk_init; 398 rate_table = omap2420_rate_table; 399 } 400 401 void __init omap2420_init_late(void) 402 { 403 omap_common_late_init(); 404 omap2_pm_init(); 405 omap2_clk_enable_autoidle_all(); 406 } 407 #endif 408 409 #ifdef CONFIG_SOC_OMAP2430 410 void __init omap2430_init_early(void) 411 { 412 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000)); 413 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE), 414 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE)); 415 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE), 416 NULL); 417 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE)); 418 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL); 419 omap2xxx_check_revision(); 420 omap2xxx_prm_init(); 421 omap2xxx_cm_init(); 422 omap2xxx_voltagedomains_init(); 423 omap243x_powerdomains_init(); 424 omap243x_clockdomains_init(); 425 omap2430_hwmod_init(); 426 omap_hwmod_init_postsetup(); 427 omap_clk_soc_init = omap2430_dt_clk_init; 428 rate_table = omap2430_rate_table; 429 } 430 431 void __init omap2430_init_late(void) 432 { 433 omap_common_late_init(); 434 omap2_pm_init(); 435 omap2_clk_enable_autoidle_all(); 436 } 437 #endif 438 439 /* 440 * Currently only board-omap3beagle.c should call this because of the 441 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT. 442 */ 443 #ifdef CONFIG_ARCH_OMAP3 444 void __init omap3_init_early(void) 445 { 446 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000)); 447 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE), 448 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE)); 449 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE), 450 NULL); 451 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE)); 452 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL); 453 omap3xxx_check_revision(); 454 omap3xxx_check_features(); 455 omap3xxx_prm_init(); 456 omap3xxx_cm_init(); 457 omap3xxx_voltagedomains_init(); 458 omap3xxx_powerdomains_init(); 459 omap3xxx_clockdomains_init(); 460 omap3xxx_hwmod_init(); 461 omap_hwmod_init_postsetup(); 462 if (!of_have_populated_dt()) { 463 omap3_prcm_legacy_iomaps_init(); 464 if (soc_is_am35xx()) 465 omap_clk_soc_init = am35xx_clk_legacy_init; 466 else if (cpu_is_omap3630()) 467 omap_clk_soc_init = omap36xx_clk_legacy_init; 468 else if (omap_rev() == OMAP3430_REV_ES1_0) 469 omap_clk_soc_init = omap3430es1_clk_legacy_init; 470 else 471 omap_clk_soc_init = omap3430_clk_legacy_init; 472 } 473 } 474 475 void __init omap3430_init_early(void) 476 { 477 omap3_init_early(); 478 if (of_have_populated_dt()) 479 omap_clk_soc_init = omap3430_dt_clk_init; 480 } 481 482 void __init omap35xx_init_early(void) 483 { 484 omap3_init_early(); 485 if (of_have_populated_dt()) 486 omap_clk_soc_init = omap3430_dt_clk_init; 487 } 488 489 void __init omap3630_init_early(void) 490 { 491 omap3_init_early(); 492 if (of_have_populated_dt()) 493 omap_clk_soc_init = omap3630_dt_clk_init; 494 } 495 496 void __init am35xx_init_early(void) 497 { 498 omap3_init_early(); 499 if (of_have_populated_dt()) 500 omap_clk_soc_init = am35xx_dt_clk_init; 501 } 502 503 void __init omap3_init_late(void) 504 { 505 omap_common_late_init(); 506 omap3_pm_init(); 507 omap2_clk_enable_autoidle_all(); 508 } 509 510 void __init omap3430_init_late(void) 511 { 512 omap_common_late_init(); 513 omap3_pm_init(); 514 omap2_clk_enable_autoidle_all(); 515 } 516 517 void __init omap35xx_init_late(void) 518 { 519 omap_common_late_init(); 520 omap3_pm_init(); 521 omap2_clk_enable_autoidle_all(); 522 } 523 524 void __init omap3630_init_late(void) 525 { 526 omap_common_late_init(); 527 omap3_pm_init(); 528 omap2_clk_enable_autoidle_all(); 529 } 530 531 void __init am35xx_init_late(void) 532 { 533 omap_common_late_init(); 534 omap3_pm_init(); 535 omap2_clk_enable_autoidle_all(); 536 } 537 538 void __init ti81xx_init_late(void) 539 { 540 omap_common_late_init(); 541 omap2_clk_enable_autoidle_all(); 542 } 543 #endif 544 545 #ifdef CONFIG_SOC_TI81XX 546 void __init ti814x_init_early(void) 547 { 548 omap2_set_globals_tap(TI814X_CLASS, 549 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); 550 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE), 551 NULL); 552 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE)); 553 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL); 554 omap3xxx_check_revision(); 555 ti81xx_check_features(); 556 am33xx_prm_init(); 557 am33xx_cm_init(); 558 omap3xxx_voltagedomains_init(); 559 omap3xxx_powerdomains_init(); 560 ti81xx_clockdomains_init(); 561 ti81xx_hwmod_init(); 562 omap_hwmod_init_postsetup(); 563 if (of_have_populated_dt()) 564 omap_clk_soc_init = ti81xx_dt_clk_init; 565 } 566 567 void __init ti816x_init_early(void) 568 { 569 omap2_set_globals_tap(TI816X_CLASS, 570 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); 571 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE), 572 NULL); 573 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE)); 574 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL); 575 omap3xxx_check_revision(); 576 ti81xx_check_features(); 577 am33xx_prm_init(); 578 am33xx_cm_init(); 579 omap3xxx_voltagedomains_init(); 580 omap3xxx_powerdomains_init(); 581 ti81xx_clockdomains_init(); 582 ti81xx_hwmod_init(); 583 omap_hwmod_init_postsetup(); 584 if (of_have_populated_dt()) 585 omap_clk_soc_init = ti81xx_dt_clk_init; 586 } 587 #endif 588 589 #ifdef CONFIG_SOC_AM33XX 590 void __init am33xx_init_early(void) 591 { 592 omap2_set_globals_tap(AM335X_CLASS, 593 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); 594 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE), 595 NULL); 596 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE)); 597 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL); 598 omap3xxx_check_revision(); 599 am33xx_check_features(); 600 am33xx_prm_init(); 601 am33xx_cm_init(); 602 am33xx_powerdomains_init(); 603 am33xx_clockdomains_init(); 604 am33xx_hwmod_init(); 605 omap_hwmod_init_postsetup(); 606 omap_clk_soc_init = am33xx_dt_clk_init; 607 } 608 609 void __init am33xx_init_late(void) 610 { 611 omap_common_late_init(); 612 } 613 #endif 614 615 #ifdef CONFIG_SOC_AM43XX 616 void __init am43xx_init_early(void) 617 { 618 omap2_set_globals_tap(AM335X_CLASS, 619 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); 620 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE), 621 NULL); 622 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE)); 623 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL); 624 omap_prm_base_init(); 625 omap_cm_base_init(); 626 omap3xxx_check_revision(); 627 am33xx_check_features(); 628 omap44xx_prm_init(); 629 omap4_cm_init(); 630 am43xx_powerdomains_init(); 631 am43xx_clockdomains_init(); 632 am43xx_hwmod_init(); 633 omap_hwmod_init_postsetup(); 634 omap_l2_cache_init(); 635 omap_clk_soc_init = am43xx_dt_clk_init; 636 } 637 638 void __init am43xx_init_late(void) 639 { 640 omap_common_late_init(); 641 } 642 #endif 643 644 #ifdef CONFIG_ARCH_OMAP4 645 void __init omap4430_init_early(void) 646 { 647 omap2_set_globals_tap(OMAP443X_CLASS, 648 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE)); 649 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE), 650 OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE)); 651 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE)); 652 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE), 653 OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE)); 654 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE)); 655 omap_prm_base_init(); 656 omap_cm_base_init(); 657 omap4xxx_check_revision(); 658 omap4xxx_check_features(); 659 omap4_cm_init(); 660 omap4_pm_init_early(); 661 omap44xx_prm_init(); 662 omap44xx_voltagedomains_init(); 663 omap44xx_powerdomains_init(); 664 omap44xx_clockdomains_init(); 665 omap44xx_hwmod_init(); 666 omap_hwmod_init_postsetup(); 667 omap_l2_cache_init(); 668 omap_clk_soc_init = omap4xxx_dt_clk_init; 669 } 670 671 void __init omap4430_init_late(void) 672 { 673 omap_common_late_init(); 674 omap4_pm_init(); 675 omap2_clk_enable_autoidle_all(); 676 } 677 #endif 678 679 #ifdef CONFIG_SOC_OMAP5 680 void __init omap5_init_early(void) 681 { 682 omap2_set_globals_tap(OMAP54XX_CLASS, 683 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE)); 684 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE), 685 OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE)); 686 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE)); 687 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE), 688 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE)); 689 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); 690 omap4_pm_init_early(); 691 omap_prm_base_init(); 692 omap_cm_base_init(); 693 omap44xx_prm_init(); 694 omap5xxx_check_revision(); 695 omap4_cm_init(); 696 omap54xx_voltagedomains_init(); 697 omap54xx_powerdomains_init(); 698 omap54xx_clockdomains_init(); 699 omap54xx_hwmod_init(); 700 omap_hwmod_init_postsetup(); 701 omap_clk_soc_init = omap5xxx_dt_clk_init; 702 } 703 704 void __init omap5_init_late(void) 705 { 706 omap_common_late_init(); 707 omap4_pm_init(); 708 omap2_clk_enable_autoidle_all(); 709 } 710 #endif 711 712 #ifdef CONFIG_SOC_DRA7XX 713 void __init dra7xx_init_early(void) 714 { 715 omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE)); 716 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE), 717 OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE)); 718 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE)); 719 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE), 720 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE)); 721 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); 722 omap4_pm_init_early(); 723 omap_prm_base_init(); 724 omap_cm_base_init(); 725 omap44xx_prm_init(); 726 dra7xxx_check_revision(); 727 omap4_cm_init(); 728 dra7xx_powerdomains_init(); 729 dra7xx_clockdomains_init(); 730 dra7xx_hwmod_init(); 731 omap_hwmod_init_postsetup(); 732 omap_clk_soc_init = dra7xx_dt_clk_init; 733 } 734 735 void __init dra7xx_init_late(void) 736 { 737 omap_common_late_init(); 738 omap4_pm_init(); 739 omap2_clk_enable_autoidle_all(); 740 } 741 #endif 742 743 744 void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, 745 struct omap_sdrc_params *sdrc_cs1) 746 { 747 omap_sram_init(); 748 749 if (cpu_is_omap24xx() || omap3_has_sdrc()) { 750 omap2_sdrc_init(sdrc_cs0, sdrc_cs1); 751 _omap2_init_reprogram_sdrc(); 752 } 753 } 754 755 int __init omap_clk_init(void) 756 { 757 int ret = 0; 758 759 if (!omap_clk_soc_init) 760 return 0; 761 762 ti_clk_init_features(); 763 764 if (of_have_populated_dt()) { 765 ret = of_prcm_init(); 766 if (ret) 767 return ret; 768 769 of_clk_init(NULL); 770 771 ti_dt_clk_init_retry_clks(); 772 773 ti_dt_clockdomains_setup(); 774 } 775 776 ret = omap_clk_soc_init(); 777 778 return ret; 779 } 780