1 /* 2 * linux/arch/arm/mach-omap2/io.c 3 * 4 * OMAP2 I/O mapping code 5 * 6 * Copyright (C) 2005 Nokia Corporation 7 * Copyright (C) 2007-2009 Texas Instruments 8 * 9 * Author: 10 * Juha Yrjola <juha.yrjola@nokia.com> 11 * Syed Khasim <x0khasim@ti.com> 12 * 13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License version 2 as 17 * published by the Free Software Foundation. 18 */ 19 #include <linux/module.h> 20 #include <linux/kernel.h> 21 #include <linux/init.h> 22 #include <linux/io.h> 23 #include <linux/clk.h> 24 25 #include <asm/tlb.h> 26 #include <asm/mach/map.h> 27 28 #include <linux/omap-dma.h> 29 30 #include "omap_hwmod.h" 31 #include "soc.h" 32 #include "iomap.h" 33 #include "voltage.h" 34 #include "powerdomain.h" 35 #include "clockdomain.h" 36 #include "common.h" 37 #include "clock.h" 38 #include "clock2xxx.h" 39 #include "clock3xxx.h" 40 #include "sdrc.h" 41 #include "control.h" 42 #include "serial.h" 43 #include "sram.h" 44 #include "cm2xxx.h" 45 #include "cm3xxx.h" 46 #include "cm33xx.h" 47 #include "cm44xx.h" 48 #include "prm.h" 49 #include "cm.h" 50 #include "prcm_mpu44xx.h" 51 #include "prminst44xx.h" 52 #include "prm2xxx.h" 53 #include "prm3xxx.h" 54 #include "prm33xx.h" 55 #include "prm44xx.h" 56 #include "opp2xxx.h" 57 58 /* 59 * omap_clk_soc_init: points to a function that does the SoC-specific 60 * clock initializations 61 */ 62 static int (*omap_clk_soc_init)(void); 63 64 /* 65 * The machine specific code may provide the extra mapping besides the 66 * default mapping provided here. 67 */ 68 69 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430) 70 static struct map_desc omap24xx_io_desc[] __initdata = { 71 { 72 .virtual = L3_24XX_VIRT, 73 .pfn = __phys_to_pfn(L3_24XX_PHYS), 74 .length = L3_24XX_SIZE, 75 .type = MT_DEVICE 76 }, 77 { 78 .virtual = L4_24XX_VIRT, 79 .pfn = __phys_to_pfn(L4_24XX_PHYS), 80 .length = L4_24XX_SIZE, 81 .type = MT_DEVICE 82 }, 83 }; 84 85 #ifdef CONFIG_SOC_OMAP2420 86 static struct map_desc omap242x_io_desc[] __initdata = { 87 { 88 .virtual = DSP_MEM_2420_VIRT, 89 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS), 90 .length = DSP_MEM_2420_SIZE, 91 .type = MT_DEVICE 92 }, 93 { 94 .virtual = DSP_IPI_2420_VIRT, 95 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS), 96 .length = DSP_IPI_2420_SIZE, 97 .type = MT_DEVICE 98 }, 99 { 100 .virtual = DSP_MMU_2420_VIRT, 101 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS), 102 .length = DSP_MMU_2420_SIZE, 103 .type = MT_DEVICE 104 }, 105 }; 106 107 #endif 108 109 #ifdef CONFIG_SOC_OMAP2430 110 static struct map_desc omap243x_io_desc[] __initdata = { 111 { 112 .virtual = L4_WK_243X_VIRT, 113 .pfn = __phys_to_pfn(L4_WK_243X_PHYS), 114 .length = L4_WK_243X_SIZE, 115 .type = MT_DEVICE 116 }, 117 { 118 .virtual = OMAP243X_GPMC_VIRT, 119 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS), 120 .length = OMAP243X_GPMC_SIZE, 121 .type = MT_DEVICE 122 }, 123 { 124 .virtual = OMAP243X_SDRC_VIRT, 125 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS), 126 .length = OMAP243X_SDRC_SIZE, 127 .type = MT_DEVICE 128 }, 129 { 130 .virtual = OMAP243X_SMS_VIRT, 131 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS), 132 .length = OMAP243X_SMS_SIZE, 133 .type = MT_DEVICE 134 }, 135 }; 136 #endif 137 #endif 138 139 #ifdef CONFIG_ARCH_OMAP3 140 static struct map_desc omap34xx_io_desc[] __initdata = { 141 { 142 .virtual = L3_34XX_VIRT, 143 .pfn = __phys_to_pfn(L3_34XX_PHYS), 144 .length = L3_34XX_SIZE, 145 .type = MT_DEVICE 146 }, 147 { 148 .virtual = L4_34XX_VIRT, 149 .pfn = __phys_to_pfn(L4_34XX_PHYS), 150 .length = L4_34XX_SIZE, 151 .type = MT_DEVICE 152 }, 153 { 154 .virtual = OMAP34XX_GPMC_VIRT, 155 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS), 156 .length = OMAP34XX_GPMC_SIZE, 157 .type = MT_DEVICE 158 }, 159 { 160 .virtual = OMAP343X_SMS_VIRT, 161 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS), 162 .length = OMAP343X_SMS_SIZE, 163 .type = MT_DEVICE 164 }, 165 { 166 .virtual = OMAP343X_SDRC_VIRT, 167 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS), 168 .length = OMAP343X_SDRC_SIZE, 169 .type = MT_DEVICE 170 }, 171 { 172 .virtual = L4_PER_34XX_VIRT, 173 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS), 174 .length = L4_PER_34XX_SIZE, 175 .type = MT_DEVICE 176 }, 177 { 178 .virtual = L4_EMU_34XX_VIRT, 179 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS), 180 .length = L4_EMU_34XX_SIZE, 181 .type = MT_DEVICE 182 }, 183 }; 184 #endif 185 186 #ifdef CONFIG_SOC_TI81XX 187 static struct map_desc omapti81xx_io_desc[] __initdata = { 188 { 189 .virtual = L4_34XX_VIRT, 190 .pfn = __phys_to_pfn(L4_34XX_PHYS), 191 .length = L4_34XX_SIZE, 192 .type = MT_DEVICE 193 } 194 }; 195 #endif 196 197 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) 198 static struct map_desc omapam33xx_io_desc[] __initdata = { 199 { 200 .virtual = L4_34XX_VIRT, 201 .pfn = __phys_to_pfn(L4_34XX_PHYS), 202 .length = L4_34XX_SIZE, 203 .type = MT_DEVICE 204 }, 205 { 206 .virtual = L4_WK_AM33XX_VIRT, 207 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS), 208 .length = L4_WK_AM33XX_SIZE, 209 .type = MT_DEVICE 210 } 211 }; 212 #endif 213 214 #ifdef CONFIG_ARCH_OMAP4 215 static struct map_desc omap44xx_io_desc[] __initdata = { 216 { 217 .virtual = L3_44XX_VIRT, 218 .pfn = __phys_to_pfn(L3_44XX_PHYS), 219 .length = L3_44XX_SIZE, 220 .type = MT_DEVICE, 221 }, 222 { 223 .virtual = L4_44XX_VIRT, 224 .pfn = __phys_to_pfn(L4_44XX_PHYS), 225 .length = L4_44XX_SIZE, 226 .type = MT_DEVICE, 227 }, 228 { 229 .virtual = L4_PER_44XX_VIRT, 230 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS), 231 .length = L4_PER_44XX_SIZE, 232 .type = MT_DEVICE, 233 }, 234 }; 235 #endif 236 237 #ifdef CONFIG_SOC_OMAP5 238 static struct map_desc omap54xx_io_desc[] __initdata = { 239 { 240 .virtual = L3_54XX_VIRT, 241 .pfn = __phys_to_pfn(L3_54XX_PHYS), 242 .length = L3_54XX_SIZE, 243 .type = MT_DEVICE, 244 }, 245 { 246 .virtual = L4_54XX_VIRT, 247 .pfn = __phys_to_pfn(L4_54XX_PHYS), 248 .length = L4_54XX_SIZE, 249 .type = MT_DEVICE, 250 }, 251 { 252 .virtual = L4_WK_54XX_VIRT, 253 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS), 254 .length = L4_WK_54XX_SIZE, 255 .type = MT_DEVICE, 256 }, 257 { 258 .virtual = L4_PER_54XX_VIRT, 259 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS), 260 .length = L4_PER_54XX_SIZE, 261 .type = MT_DEVICE, 262 }, 263 }; 264 #endif 265 266 #ifdef CONFIG_SOC_DRA7XX 267 static struct map_desc dra7xx_io_desc[] __initdata = { 268 { 269 .virtual = L4_CFG_MPU_DRA7XX_VIRT, 270 .pfn = __phys_to_pfn(L4_CFG_MPU_DRA7XX_PHYS), 271 .length = L4_CFG_MPU_DRA7XX_SIZE, 272 .type = MT_DEVICE, 273 }, 274 { 275 .virtual = L3_MAIN_SN_DRA7XX_VIRT, 276 .pfn = __phys_to_pfn(L3_MAIN_SN_DRA7XX_PHYS), 277 .length = L3_MAIN_SN_DRA7XX_SIZE, 278 .type = MT_DEVICE, 279 }, 280 { 281 .virtual = L4_PER1_DRA7XX_VIRT, 282 .pfn = __phys_to_pfn(L4_PER1_DRA7XX_PHYS), 283 .length = L4_PER1_DRA7XX_SIZE, 284 .type = MT_DEVICE, 285 }, 286 { 287 .virtual = L4_PER2_DRA7XX_VIRT, 288 .pfn = __phys_to_pfn(L4_PER2_DRA7XX_PHYS), 289 .length = L4_PER2_DRA7XX_SIZE, 290 .type = MT_DEVICE, 291 }, 292 { 293 .virtual = L4_PER3_DRA7XX_VIRT, 294 .pfn = __phys_to_pfn(L4_PER3_DRA7XX_PHYS), 295 .length = L4_PER3_DRA7XX_SIZE, 296 .type = MT_DEVICE, 297 }, 298 { 299 .virtual = L4_CFG_DRA7XX_VIRT, 300 .pfn = __phys_to_pfn(L4_CFG_DRA7XX_PHYS), 301 .length = L4_CFG_DRA7XX_SIZE, 302 .type = MT_DEVICE, 303 }, 304 { 305 .virtual = L4_WKUP_DRA7XX_VIRT, 306 .pfn = __phys_to_pfn(L4_WKUP_DRA7XX_PHYS), 307 .length = L4_WKUP_DRA7XX_SIZE, 308 .type = MT_DEVICE, 309 }, 310 }; 311 #endif 312 313 #ifdef CONFIG_SOC_OMAP2420 314 void __init omap242x_map_io(void) 315 { 316 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); 317 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc)); 318 } 319 #endif 320 321 #ifdef CONFIG_SOC_OMAP2430 322 void __init omap243x_map_io(void) 323 { 324 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); 325 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc)); 326 } 327 #endif 328 329 #ifdef CONFIG_ARCH_OMAP3 330 void __init omap3_map_io(void) 331 { 332 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc)); 333 } 334 #endif 335 336 #ifdef CONFIG_SOC_TI81XX 337 void __init ti81xx_map_io(void) 338 { 339 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc)); 340 } 341 #endif 342 343 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) 344 void __init am33xx_map_io(void) 345 { 346 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc)); 347 } 348 #endif 349 350 #ifdef CONFIG_ARCH_OMAP4 351 void __init omap4_map_io(void) 352 { 353 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc)); 354 omap_barriers_init(); 355 } 356 #endif 357 358 #ifdef CONFIG_SOC_OMAP5 359 void __init omap5_map_io(void) 360 { 361 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); 362 omap_barriers_init(); 363 } 364 #endif 365 366 #ifdef CONFIG_SOC_DRA7XX 367 void __init dra7xx_map_io(void) 368 { 369 iotable_init(dra7xx_io_desc, ARRAY_SIZE(dra7xx_io_desc)); 370 omap_barriers_init(); 371 } 372 #endif 373 /* 374 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters 375 * 376 * Sets the CORE DPLL3 M2 divider to the same value that it's at 377 * currently. This has the effect of setting the SDRC SDRAM AC timing 378 * registers to the values currently defined by the kernel. Currently 379 * only defined for OMAP3; will return 0 if called on OMAP2. Returns 380 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2, 381 * or passes along the return value of clk_set_rate(). 382 */ 383 static int __init _omap2_init_reprogram_sdrc(void) 384 { 385 struct clk *dpll3_m2_ck; 386 int v = -EINVAL; 387 long rate; 388 389 if (!cpu_is_omap34xx()) 390 return 0; 391 392 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck"); 393 if (IS_ERR(dpll3_m2_ck)) 394 return -EINVAL; 395 396 rate = clk_get_rate(dpll3_m2_ck); 397 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate); 398 v = clk_set_rate(dpll3_m2_ck, rate); 399 if (v) 400 pr_err("dpll3_m2_clk rate change failed: %d\n", v); 401 402 clk_put(dpll3_m2_ck); 403 404 return v; 405 } 406 407 static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data) 408 { 409 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data); 410 } 411 412 static void __init __maybe_unused omap_hwmod_init_postsetup(void) 413 { 414 u8 postsetup_state = _HWMOD_STATE_DEFAULT; 415 416 /* Set the default postsetup state for all hwmods */ 417 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state); 418 } 419 420 #ifdef CONFIG_SOC_OMAP2420 421 void __init omap2420_init_early(void) 422 { 423 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000)); 424 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE), 425 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE)); 426 omap2_control_base_init(); 427 omap2xxx_check_revision(); 428 omap2_prcm_base_init(); 429 omap2xxx_voltagedomains_init(); 430 omap242x_powerdomains_init(); 431 omap242x_clockdomains_init(); 432 omap2420_hwmod_init(); 433 omap_hwmod_init_postsetup(); 434 omap_clk_soc_init = omap2420_dt_clk_init; 435 rate_table = omap2420_rate_table; 436 } 437 438 void __init omap2420_init_late(void) 439 { 440 omap_pm_soc_init = omap2_pm_init; 441 } 442 #endif 443 444 #ifdef CONFIG_SOC_OMAP2430 445 void __init omap2430_init_early(void) 446 { 447 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000)); 448 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE), 449 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE)); 450 omap2_control_base_init(); 451 omap2xxx_check_revision(); 452 omap2_prcm_base_init(); 453 omap2xxx_voltagedomains_init(); 454 omap243x_powerdomains_init(); 455 omap243x_clockdomains_init(); 456 omap2430_hwmod_init(); 457 omap_hwmod_init_postsetup(); 458 omap_clk_soc_init = omap2430_dt_clk_init; 459 rate_table = omap2430_rate_table; 460 } 461 462 void __init omap2430_init_late(void) 463 { 464 omap_pm_soc_init = omap2_pm_init; 465 } 466 #endif 467 468 /* 469 * Currently only board-omap3beagle.c should call this because of the 470 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT. 471 */ 472 #ifdef CONFIG_ARCH_OMAP3 473 void __init omap3_init_early(void) 474 { 475 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000)); 476 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE), 477 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE)); 478 omap2_control_base_init(); 479 omap3xxx_check_revision(); 480 omap3xxx_check_features(); 481 omap2_prcm_base_init(); 482 omap3xxx_voltagedomains_init(); 483 omap3xxx_powerdomains_init(); 484 omap3xxx_clockdomains_init(); 485 omap3xxx_hwmod_init(); 486 omap_hwmod_init_postsetup(); 487 } 488 489 void __init omap3430_init_early(void) 490 { 491 omap3_init_early(); 492 omap_clk_soc_init = omap3430_dt_clk_init; 493 } 494 495 void __init omap35xx_init_early(void) 496 { 497 omap3_init_early(); 498 omap_clk_soc_init = omap3430_dt_clk_init; 499 } 500 501 void __init omap3630_init_early(void) 502 { 503 omap3_init_early(); 504 omap_clk_soc_init = omap3630_dt_clk_init; 505 } 506 507 void __init am35xx_init_early(void) 508 { 509 omap3_init_early(); 510 omap_clk_soc_init = am35xx_dt_clk_init; 511 } 512 513 void __init omap3_init_late(void) 514 { 515 omap_pm_soc_init = omap3_pm_init; 516 } 517 518 void __init ti81xx_init_late(void) 519 { 520 omap_pm_soc_init = omap_pm_nop_init; 521 } 522 #endif 523 524 #ifdef CONFIG_SOC_TI81XX 525 void __init ti814x_init_early(void) 526 { 527 omap2_set_globals_tap(TI814X_CLASS, 528 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); 529 omap2_control_base_init(); 530 omap3xxx_check_revision(); 531 ti81xx_check_features(); 532 omap2_prcm_base_init(); 533 omap3xxx_voltagedomains_init(); 534 omap3xxx_powerdomains_init(); 535 ti814x_clockdomains_init(); 536 dm814x_hwmod_init(); 537 omap_hwmod_init_postsetup(); 538 omap_clk_soc_init = dm814x_dt_clk_init; 539 } 540 541 void __init ti816x_init_early(void) 542 { 543 omap2_set_globals_tap(TI816X_CLASS, 544 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); 545 omap2_control_base_init(); 546 omap3xxx_check_revision(); 547 ti81xx_check_features(); 548 omap2_prcm_base_init(); 549 omap3xxx_voltagedomains_init(); 550 omap3xxx_powerdomains_init(); 551 ti816x_clockdomains_init(); 552 dm816x_hwmod_init(); 553 omap_hwmod_init_postsetup(); 554 omap_clk_soc_init = dm816x_dt_clk_init; 555 } 556 #endif 557 558 #ifdef CONFIG_SOC_AM33XX 559 void __init am33xx_init_early(void) 560 { 561 omap2_set_globals_tap(AM335X_CLASS, 562 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); 563 omap2_control_base_init(); 564 omap3xxx_check_revision(); 565 am33xx_check_features(); 566 omap2_prcm_base_init(); 567 am33xx_powerdomains_init(); 568 am33xx_clockdomains_init(); 569 am33xx_hwmod_init(); 570 omap_hwmod_init_postsetup(); 571 omap_clk_soc_init = am33xx_dt_clk_init; 572 } 573 574 void __init am33xx_init_late(void) 575 { 576 omap_pm_soc_init = amx3_common_pm_init; 577 } 578 #endif 579 580 #ifdef CONFIG_SOC_AM43XX 581 void __init am43xx_init_early(void) 582 { 583 omap2_set_globals_tap(AM335X_CLASS, 584 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); 585 omap2_control_base_init(); 586 omap3xxx_check_revision(); 587 am33xx_check_features(); 588 omap2_prcm_base_init(); 589 am43xx_powerdomains_init(); 590 am43xx_clockdomains_init(); 591 am43xx_hwmod_init(); 592 omap_hwmod_init_postsetup(); 593 omap_l2_cache_init(); 594 omap_clk_soc_init = am43xx_dt_clk_init; 595 } 596 597 void __init am43xx_init_late(void) 598 { 599 omap_pm_soc_init = amx3_common_pm_init; 600 } 601 #endif 602 603 #ifdef CONFIG_ARCH_OMAP4 604 void __init omap4430_init_early(void) 605 { 606 omap2_set_globals_tap(OMAP443X_CLASS, 607 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE)); 608 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE)); 609 omap2_control_base_init(); 610 omap4xxx_check_revision(); 611 omap4xxx_check_features(); 612 omap2_prcm_base_init(); 613 omap4_sar_ram_init(); 614 omap4_mpuss_early_init(); 615 omap4_pm_init_early(); 616 omap44xx_voltagedomains_init(); 617 omap44xx_powerdomains_init(); 618 omap44xx_clockdomains_init(); 619 omap44xx_hwmod_init(); 620 omap_hwmod_init_postsetup(); 621 omap_l2_cache_init(); 622 omap_clk_soc_init = omap4xxx_dt_clk_init; 623 } 624 625 void __init omap4430_init_late(void) 626 { 627 omap_pm_soc_init = omap4_pm_init; 628 } 629 #endif 630 631 #ifdef CONFIG_SOC_OMAP5 632 void __init omap5_init_early(void) 633 { 634 omap2_set_globals_tap(OMAP54XX_CLASS, 635 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE)); 636 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); 637 omap2_control_base_init(); 638 omap2_prcm_base_init(); 639 omap5xxx_check_revision(); 640 omap4_sar_ram_init(); 641 omap4_mpuss_early_init(); 642 omap4_pm_init_early(); 643 omap54xx_voltagedomains_init(); 644 omap54xx_powerdomains_init(); 645 omap54xx_clockdomains_init(); 646 omap54xx_hwmod_init(); 647 omap_hwmod_init_postsetup(); 648 omap_clk_soc_init = omap5xxx_dt_clk_init; 649 } 650 651 void __init omap5_init_late(void) 652 { 653 omap_pm_soc_init = omap4_pm_init; 654 } 655 #endif 656 657 #ifdef CONFIG_SOC_DRA7XX 658 void __init dra7xx_init_early(void) 659 { 660 omap2_set_globals_tap(DRA7XX_CLASS, 661 OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE)); 662 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); 663 omap2_control_base_init(); 664 omap4_pm_init_early(); 665 omap2_prcm_base_init(); 666 dra7xxx_check_revision(); 667 dra7xx_powerdomains_init(); 668 dra7xx_clockdomains_init(); 669 dra7xx_hwmod_init(); 670 omap_hwmod_init_postsetup(); 671 omap_clk_soc_init = dra7xx_dt_clk_init; 672 } 673 674 void __init dra7xx_init_late(void) 675 { 676 omap_pm_soc_init = omap4_pm_init; 677 } 678 #endif 679 680 681 void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, 682 struct omap_sdrc_params *sdrc_cs1) 683 { 684 omap_sram_init(); 685 686 if (cpu_is_omap24xx() || omap3_has_sdrc()) { 687 omap2_sdrc_init(sdrc_cs0, sdrc_cs1); 688 _omap2_init_reprogram_sdrc(); 689 } 690 } 691 692 int __init omap_clk_init(void) 693 { 694 int ret = 0; 695 696 if (!omap_clk_soc_init) 697 return 0; 698 699 ti_clk_init_features(); 700 701 omap2_clk_setup_ll_ops(); 702 703 ret = omap_control_init(); 704 if (ret) 705 return ret; 706 707 ret = omap_prcm_init(); 708 if (ret) 709 return ret; 710 711 of_clk_init(NULL); 712 713 ti_dt_clk_init_retry_clks(); 714 715 ti_dt_clockdomains_setup(); 716 717 ret = omap_clk_soc_init(); 718 719 return ret; 720 } 721