1 /* 2 * linux/arch/arm/mach-omap2/id.c 3 * 4 * OMAP2 CPU identification code 5 * 6 * Copyright (C) 2005 Nokia Corporation 7 * Written by Tony Lindgren <tony@atomide.com> 8 * 9 * Copyright (C) 2009 Texas Instruments 10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License version 2 as 14 * published by the Free Software Foundation. 15 */ 16 17 #include <linux/module.h> 18 #include <linux/kernel.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 22 #include <asm/cputype.h> 23 24 #include <plat/common.h> 25 #include <plat/cpu.h> 26 27 #include <mach/id.h> 28 29 #include "control.h" 30 31 static struct omap_chip_id omap_chip; 32 static unsigned int omap_revision; 33 34 u32 omap3_features; 35 36 unsigned int omap_rev(void) 37 { 38 return omap_revision; 39 } 40 EXPORT_SYMBOL(omap_rev); 41 42 /** 43 * omap_chip_is - test whether currently running OMAP matches a chip type 44 * @oc: omap_chip_t to test against 45 * 46 * Test whether the currently-running OMAP chip matches the supplied 47 * chip type 'oc'. Returns 1 upon a match; 0 upon failure. 48 */ 49 int omap_chip_is(struct omap_chip_id oci) 50 { 51 return (oci.oc & omap_chip.oc) ? 1 : 0; 52 } 53 EXPORT_SYMBOL(omap_chip_is); 54 55 int omap_type(void) 56 { 57 u32 val = 0; 58 59 if (cpu_is_omap24xx()) { 60 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); 61 } else if (cpu_is_omap34xx()) { 62 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); 63 } else if (cpu_is_omap44xx()) { 64 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS); 65 } else { 66 pr_err("Cannot detect omap type!\n"); 67 goto out; 68 } 69 70 val &= OMAP2_DEVICETYPE_MASK; 71 val >>= 8; 72 73 out: 74 return val; 75 } 76 EXPORT_SYMBOL(omap_type); 77 78 79 /*----------------------------------------------------------------------------*/ 80 81 #define OMAP_TAP_IDCODE 0x0204 82 #define OMAP_TAP_DIE_ID_0 0x0218 83 #define OMAP_TAP_DIE_ID_1 0x021C 84 #define OMAP_TAP_DIE_ID_2 0x0220 85 #define OMAP_TAP_DIE_ID_3 0x0224 86 87 #define read_tap_reg(reg) __raw_readl(tap_base + (reg)) 88 89 struct omap_id { 90 u16 hawkeye; /* Silicon type (Hawkeye id) */ 91 u8 dev; /* Device type from production_id reg */ 92 u32 type; /* Combined type id copied to omap_revision */ 93 }; 94 95 /* Register values to detect the OMAP version */ 96 static struct omap_id omap_ids[] __initdata = { 97 { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 }, 98 { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 }, 99 { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 }, 100 { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 }, 101 { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 }, 102 { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 }, 103 }; 104 105 static void __iomem *tap_base; 106 static u16 tap_prod_id; 107 108 void omap_get_die_id(struct omap_die_id *odi) 109 { 110 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0); 111 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1); 112 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2); 113 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3); 114 } 115 116 static void __init omap24xx_check_revision(void) 117 { 118 int i, j; 119 u32 idcode, prod_id; 120 u16 hawkeye; 121 u8 dev_type, rev; 122 struct omap_die_id odi; 123 124 idcode = read_tap_reg(OMAP_TAP_IDCODE); 125 prod_id = read_tap_reg(tap_prod_id); 126 hawkeye = (idcode >> 12) & 0xffff; 127 rev = (idcode >> 28) & 0x0f; 128 dev_type = (prod_id >> 16) & 0x0f; 129 omap_get_die_id(&odi); 130 131 pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n", 132 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff); 133 pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0); 134 pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n", 135 odi.id_1, (odi.id_1 >> 28) & 0xf); 136 pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2); 137 pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3); 138 pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n", 139 prod_id, dev_type); 140 141 /* Check hawkeye ids */ 142 for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { 143 if (hawkeye == omap_ids[i].hawkeye) 144 break; 145 } 146 147 if (i == ARRAY_SIZE(omap_ids)) { 148 printk(KERN_ERR "Unknown OMAP CPU id\n"); 149 return; 150 } 151 152 for (j = i; j < ARRAY_SIZE(omap_ids); j++) { 153 if (dev_type == omap_ids[j].dev) 154 break; 155 } 156 157 if (j == ARRAY_SIZE(omap_ids)) { 158 printk(KERN_ERR "Unknown OMAP device type. " 159 "Handling it as OMAP%04x\n", 160 omap_ids[i].type >> 16); 161 j = i; 162 } 163 164 pr_info("OMAP%04x", omap_rev() >> 16); 165 if ((omap_rev() >> 8) & 0x0f) 166 pr_info("ES%x", (omap_rev() >> 12) & 0xf); 167 pr_info("\n"); 168 } 169 170 #define OMAP3_CHECK_FEATURE(status,feat) \ 171 if (((status & OMAP3_ ##feat## _MASK) \ 172 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \ 173 omap3_features |= OMAP3_HAS_ ##feat; \ 174 } 175 176 static void __init omap3_check_features(void) 177 { 178 u32 status; 179 180 omap3_features = 0; 181 182 status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS); 183 184 OMAP3_CHECK_FEATURE(status, L2CACHE); 185 OMAP3_CHECK_FEATURE(status, IVA); 186 OMAP3_CHECK_FEATURE(status, SGX); 187 OMAP3_CHECK_FEATURE(status, NEON); 188 OMAP3_CHECK_FEATURE(status, ISP); 189 if (cpu_is_omap3630()) 190 omap3_features |= OMAP3_HAS_192MHZ_CLK; 191 if (!cpu_is_omap3505() && !cpu_is_omap3517()) 192 omap3_features |= OMAP3_HAS_IO_WAKEUP; 193 194 /* 195 * TODO: Get additional info (where applicable) 196 * e.g. Size of L2 cache. 197 */ 198 } 199 200 static void __init omap3_check_revision(void) 201 { 202 u32 cpuid, idcode; 203 u16 hawkeye; 204 u8 rev; 205 206 omap_chip.oc = CHIP_IS_OMAP3430; 207 208 /* 209 * We cannot access revision registers on ES1.0. 210 * If the processor type is Cortex-A8 and the revision is 0x0 211 * it means its Cortex r0p0 which is 3430 ES1.0. 212 */ 213 cpuid = read_cpuid(CPUID_ID); 214 if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) { 215 omap_revision = OMAP3430_REV_ES1_0; 216 omap_chip.oc |= CHIP_IS_OMAP3430ES1; 217 return; 218 } 219 220 /* 221 * Detection for 34xx ES2.0 and above can be done with just 222 * hawkeye and rev. See TRM 1.5.2 Device Identification. 223 * Note that rev does not map directly to our defined processor 224 * revision numbers as ES1.0 uses value 0. 225 */ 226 idcode = read_tap_reg(OMAP_TAP_IDCODE); 227 hawkeye = (idcode >> 12) & 0xffff; 228 rev = (idcode >> 28) & 0xff; 229 230 switch (hawkeye) { 231 case 0xb7ae: 232 /* Handle 34xx/35xx devices */ 233 switch (rev) { 234 case 0: /* Take care of early samples */ 235 case 1: 236 omap_revision = OMAP3430_REV_ES2_0; 237 omap_chip.oc |= CHIP_IS_OMAP3430ES2; 238 break; 239 case 2: 240 omap_revision = OMAP3430_REV_ES2_1; 241 omap_chip.oc |= CHIP_IS_OMAP3430ES2; 242 break; 243 case 3: 244 omap_revision = OMAP3430_REV_ES3_0; 245 omap_chip.oc |= CHIP_IS_OMAP3430ES3_0; 246 break; 247 case 4: 248 omap_revision = OMAP3430_REV_ES3_1; 249 omap_chip.oc |= CHIP_IS_OMAP3430ES3_1; 250 break; 251 case 7: 252 /* FALLTHROUGH */ 253 default: 254 /* Use the latest known revision as default */ 255 omap_revision = OMAP3430_REV_ES3_1_2; 256 257 /* REVISIT: Add CHIP_IS_OMAP3430ES3_1_2? */ 258 omap_chip.oc |= CHIP_IS_OMAP3430ES3_1; 259 } 260 break; 261 case 0xb868: 262 /* Handle OMAP35xx/AM35xx devices 263 * 264 * Set the device to be OMAP3505 here. Actual device 265 * is identified later based on the features. 266 * 267 * REVISIT: AM3505/AM3517 should have their own CHIP_IS 268 */ 269 omap_revision = OMAP3505_REV(rev); 270 omap_chip.oc |= CHIP_IS_OMAP3430ES3_1; 271 break; 272 case 0xb891: 273 /* Handle 36xx devices */ 274 omap_chip.oc |= CHIP_IS_OMAP3630ES1; 275 276 switch(rev) { 277 case 0: /* Take care of early samples */ 278 omap_revision = OMAP3630_REV_ES1_0; 279 break; 280 case 1: 281 omap_revision = OMAP3630_REV_ES1_1; 282 omap_chip.oc |= CHIP_IS_OMAP3630ES1_1; 283 break; 284 case 2: 285 default: 286 omap_revision = OMAP3630_REV_ES1_2; 287 omap_chip.oc |= CHIP_IS_OMAP3630ES1_2; 288 } 289 break; 290 default: 291 /* Unknown default to latest silicon rev as default*/ 292 omap_revision = OMAP3630_REV_ES1_2; 293 omap_chip.oc |= CHIP_IS_OMAP3630ES1_2; 294 } 295 } 296 297 static void __init omap4_check_revision(void) 298 { 299 u32 idcode; 300 u16 hawkeye; 301 u8 rev; 302 303 /* 304 * The IC rev detection is done with hawkeye and rev. 305 * Note that rev does not map directly to defined processor 306 * revision numbers as ES1.0 uses value 0. 307 */ 308 idcode = read_tap_reg(OMAP_TAP_IDCODE); 309 hawkeye = (idcode >> 12) & 0xffff; 310 rev = (idcode >> 28) & 0xff; 311 312 /* 313 * Few initial ES2.0 samples IDCODE is same as ES1.0 314 * Use ARM register to detect the correct ES version 315 */ 316 if (!rev) { 317 idcode = read_cpuid(CPUID_ID); 318 rev = (idcode & 0xf) - 1; 319 } 320 321 switch (hawkeye) { 322 case 0xb852: 323 switch (rev) { 324 case 0: 325 omap_revision = OMAP4430_REV_ES1_0; 326 omap_chip.oc |= CHIP_IS_OMAP4430ES1; 327 break; 328 case 1: 329 omap_revision = OMAP4430_REV_ES2_0; 330 omap_chip.oc |= CHIP_IS_OMAP4430ES2; 331 break; 332 default: 333 omap_revision = OMAP4430_REV_ES2_0; 334 omap_chip.oc |= CHIP_IS_OMAP4430ES2; 335 } 336 break; 337 default: 338 /* Unknown default to latest silicon rev as default*/ 339 omap_revision = OMAP4430_REV_ES2_0; 340 omap_chip.oc |= CHIP_IS_OMAP4430ES2; 341 } 342 343 pr_info("OMAP%04x ES%d.0\n", 344 omap_rev() >> 16, ((omap_rev() >> 12) & 0xf) + 1); 345 } 346 347 #define OMAP3_SHOW_FEATURE(feat) \ 348 if (omap3_has_ ##feat()) \ 349 printk(#feat" "); 350 351 static void __init omap3_cpuinfo(void) 352 { 353 u8 rev = GET_OMAP_REVISION(); 354 char cpu_name[16], cpu_rev[16]; 355 356 /* OMAP3430 and OMAP3530 are assumed to be same. 357 * 358 * OMAP3525, OMAP3515 and OMAP3503 can be detected only based 359 * on available features. Upon detection, update the CPU id 360 * and CPU class bits. 361 */ 362 if (cpu_is_omap3630()) { 363 strcpy(cpu_name, "OMAP3630"); 364 } else if (cpu_is_omap3505()) { 365 /* 366 * AM35xx devices 367 */ 368 if (omap3_has_sgx()) { 369 omap_revision = OMAP3517_REV(rev); 370 strcpy(cpu_name, "AM3517"); 371 } else { 372 /* Already set in omap3_check_revision() */ 373 strcpy(cpu_name, "AM3505"); 374 } 375 } else if (omap3_has_iva() && omap3_has_sgx()) { 376 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */ 377 strcpy(cpu_name, "OMAP3430/3530"); 378 } else if (omap3_has_iva()) { 379 omap_revision = OMAP3525_REV(rev); 380 strcpy(cpu_name, "OMAP3525"); 381 } else if (omap3_has_sgx()) { 382 omap_revision = OMAP3515_REV(rev); 383 strcpy(cpu_name, "OMAP3515"); 384 } else { 385 omap_revision = OMAP3503_REV(rev); 386 strcpy(cpu_name, "OMAP3503"); 387 } 388 389 if (cpu_is_omap3630()) { 390 switch (rev) { 391 case OMAP_REVBITS_00: 392 strcpy(cpu_rev, "1.0"); 393 break; 394 case OMAP_REVBITS_01: 395 strcpy(cpu_rev, "1.1"); 396 break; 397 case OMAP_REVBITS_02: 398 /* FALLTHROUGH */ 399 default: 400 /* Use the latest known revision as default */ 401 strcpy(cpu_rev, "1.2"); 402 } 403 } else if (cpu_is_omap3505() || cpu_is_omap3517()) { 404 switch (rev) { 405 case OMAP_REVBITS_00: 406 strcpy(cpu_rev, "1.0"); 407 break; 408 case OMAP_REVBITS_01: 409 /* FALLTHROUGH */ 410 default: 411 /* Use the latest known revision as default */ 412 strcpy(cpu_rev, "1.1"); 413 } 414 } else { 415 switch (rev) { 416 case OMAP_REVBITS_00: 417 strcpy(cpu_rev, "1.0"); 418 break; 419 case OMAP_REVBITS_01: 420 strcpy(cpu_rev, "2.0"); 421 break; 422 case OMAP_REVBITS_02: 423 strcpy(cpu_rev, "2.1"); 424 break; 425 case OMAP_REVBITS_03: 426 strcpy(cpu_rev, "3.0"); 427 break; 428 case OMAP_REVBITS_04: 429 strcpy(cpu_rev, "3.1"); 430 break; 431 case OMAP_REVBITS_05: 432 /* FALLTHROUGH */ 433 default: 434 /* Use the latest known revision as default */ 435 strcpy(cpu_rev, "3.1.2"); 436 } 437 } 438 439 /* Print verbose information */ 440 pr_info("%s ES%s (", cpu_name, cpu_rev); 441 442 OMAP3_SHOW_FEATURE(l2cache); 443 OMAP3_SHOW_FEATURE(iva); 444 OMAP3_SHOW_FEATURE(sgx); 445 OMAP3_SHOW_FEATURE(neon); 446 OMAP3_SHOW_FEATURE(isp); 447 OMAP3_SHOW_FEATURE(192mhz_clk); 448 449 printk(")\n"); 450 } 451 452 /* 453 * Try to detect the exact revision of the omap we're running on 454 */ 455 void __init omap2_check_revision(void) 456 { 457 /* 458 * At this point we have an idea about the processor revision set 459 * earlier with omap2_set_globals_tap(). 460 */ 461 if (cpu_is_omap24xx()) { 462 omap24xx_check_revision(); 463 } else if (cpu_is_omap34xx()) { 464 omap3_check_revision(); 465 omap3_check_features(); 466 omap3_cpuinfo(); 467 return; 468 } else if (cpu_is_omap44xx()) { 469 omap4_check_revision(); 470 return; 471 } else { 472 pr_err("OMAP revision unknown, please fix!\n"); 473 } 474 475 /* 476 * OK, now we know the exact revision. Initialize omap_chip bits 477 * for powerdowmain and clockdomain code. 478 */ 479 if (cpu_is_omap243x()) { 480 /* Currently only supports 2430ES2.1 and 2430-all */ 481 omap_chip.oc |= CHIP_IS_OMAP2430; 482 return; 483 } else if (cpu_is_omap242x()) { 484 /* Currently only supports 2420ES2.1.1 and 2420-all */ 485 omap_chip.oc |= CHIP_IS_OMAP2420; 486 return; 487 } 488 489 pr_err("Uninitialized omap_chip, please fix!\n"); 490 } 491 492 /* 493 * Set up things for map_io and processor detection later on. Gets called 494 * pretty much first thing from board init. For multi-omap, this gets 495 * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to 496 * detect the exact revision later on in omap2_detect_revision() once map_io 497 * is done. 498 */ 499 void __init omap2_set_globals_tap(struct omap_globals *omap2_globals) 500 { 501 omap_revision = omap2_globals->class; 502 tap_base = omap2_globals->tap; 503 504 if (cpu_is_omap34xx()) 505 tap_prod_id = 0x0210; 506 else 507 tap_prod_id = 0x0208; 508 } 509