1 /* 2 * linux/arch/arm/mach-omap2/id.c 3 * 4 * OMAP2 CPU identification code 5 * 6 * Copyright (C) 2005 Nokia Corporation 7 * Written by Tony Lindgren <tony@atomide.com> 8 * 9 * Copyright (C) 2009-11 Texas Instruments 10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License version 2 as 14 * published by the Free Software Foundation. 15 */ 16 17 #include <linux/module.h> 18 #include <linux/kernel.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 #include <linux/random.h> 22 #include <linux/slab.h> 23 24 #ifdef CONFIG_SOC_BUS 25 #include <linux/sys_soc.h> 26 #endif 27 28 #include <asm/cputype.h> 29 30 #include "common.h" 31 32 #include "id.h" 33 34 #include "soc.h" 35 #include "control.h" 36 37 #define OMAP4_SILICON_TYPE_STANDARD 0x01 38 #define OMAP4_SILICON_TYPE_PERFORMANCE 0x02 39 40 #define OMAP_SOC_MAX_NAME_LENGTH 16 41 42 static unsigned int omap_revision; 43 static char soc_name[OMAP_SOC_MAX_NAME_LENGTH]; 44 static char soc_rev[OMAP_SOC_MAX_NAME_LENGTH]; 45 u32 omap_features; 46 47 unsigned int omap_rev(void) 48 { 49 return omap_revision; 50 } 51 EXPORT_SYMBOL(omap_rev); 52 53 int omap_type(void) 54 { 55 u32 val = 0; 56 57 if (cpu_is_omap24xx()) { 58 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); 59 } else if (cpu_is_ti81xx()) { 60 val = omap_ctrl_readl(TI81XX_CONTROL_STATUS); 61 } else if (soc_is_am33xx() || soc_is_am43xx()) { 62 val = omap_ctrl_readl(AM33XX_CONTROL_STATUS); 63 } else if (cpu_is_omap34xx()) { 64 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); 65 } else if (cpu_is_omap44xx()) { 66 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS); 67 } else if (soc_is_omap54xx() || soc_is_dra7xx()) { 68 val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS); 69 val &= OMAP5_DEVICETYPE_MASK; 70 val >>= 6; 71 goto out; 72 } else { 73 pr_err("Cannot detect omap type!\n"); 74 goto out; 75 } 76 77 val &= OMAP2_DEVICETYPE_MASK; 78 val >>= 8; 79 80 out: 81 return val; 82 } 83 EXPORT_SYMBOL(omap_type); 84 85 86 /*----------------------------------------------------------------------------*/ 87 88 #define OMAP_TAP_IDCODE 0x0204 89 #define OMAP_TAP_DIE_ID_0 0x0218 90 #define OMAP_TAP_DIE_ID_1 0x021C 91 #define OMAP_TAP_DIE_ID_2 0x0220 92 #define OMAP_TAP_DIE_ID_3 0x0224 93 94 #define OMAP_TAP_DIE_ID_44XX_0 0x0200 95 #define OMAP_TAP_DIE_ID_44XX_1 0x0208 96 #define OMAP_TAP_DIE_ID_44XX_2 0x020c 97 #define OMAP_TAP_DIE_ID_44XX_3 0x0210 98 99 #define read_tap_reg(reg) readl_relaxed(tap_base + (reg)) 100 101 struct omap_id { 102 u16 hawkeye; /* Silicon type (Hawkeye id) */ 103 u8 dev; /* Device type from production_id reg */ 104 u32 type; /* Combined type id copied to omap_revision */ 105 }; 106 107 /* Register values to detect the OMAP version */ 108 static struct omap_id omap_ids[] __initdata = { 109 { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 }, 110 { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 }, 111 { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 }, 112 { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 }, 113 { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 }, 114 { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 }, 115 }; 116 117 static void __iomem *tap_base; 118 static u16 tap_prod_id; 119 120 void omap_get_die_id(struct omap_die_id *odi) 121 { 122 if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) { 123 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0); 124 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1); 125 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2); 126 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3); 127 128 return; 129 } 130 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0); 131 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1); 132 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2); 133 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3); 134 } 135 136 static int __init omap_feed_randpool(void) 137 { 138 struct omap_die_id odi; 139 140 /* Throw the die ID into the entropy pool at boot */ 141 omap_get_die_id(&odi); 142 add_device_randomness(&odi, sizeof(odi)); 143 return 0; 144 } 145 omap_device_initcall(omap_feed_randpool); 146 147 void __init omap2xxx_check_revision(void) 148 { 149 int i, j; 150 u32 idcode, prod_id; 151 u16 hawkeye; 152 u8 dev_type, rev; 153 struct omap_die_id odi; 154 155 idcode = read_tap_reg(OMAP_TAP_IDCODE); 156 prod_id = read_tap_reg(tap_prod_id); 157 hawkeye = (idcode >> 12) & 0xffff; 158 rev = (idcode >> 28) & 0x0f; 159 dev_type = (prod_id >> 16) & 0x0f; 160 omap_get_die_id(&odi); 161 162 pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n", 163 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff); 164 pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0); 165 pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n", 166 odi.id_1, (odi.id_1 >> 28) & 0xf); 167 pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2); 168 pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3); 169 pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n", 170 prod_id, dev_type); 171 172 /* Check hawkeye ids */ 173 for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { 174 if (hawkeye == omap_ids[i].hawkeye) 175 break; 176 } 177 178 if (i == ARRAY_SIZE(omap_ids)) { 179 printk(KERN_ERR "Unknown OMAP CPU id\n"); 180 return; 181 } 182 183 for (j = i; j < ARRAY_SIZE(omap_ids); j++) { 184 if (dev_type == omap_ids[j].dev) 185 break; 186 } 187 188 if (j == ARRAY_SIZE(omap_ids)) { 189 pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n", 190 omap_ids[i].type >> 16); 191 j = i; 192 } 193 194 sprintf(soc_name, "OMAP%04x", omap_rev() >> 16); 195 sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf); 196 197 pr_info("%s", soc_name); 198 if ((omap_rev() >> 8) & 0x0f) 199 pr_info("%s", soc_rev); 200 pr_info("\n"); 201 } 202 203 #define OMAP3_SHOW_FEATURE(feat) \ 204 if (omap3_has_ ##feat()) \ 205 printk(#feat" "); 206 207 static void __init omap3_cpuinfo(void) 208 { 209 const char *cpu_name; 210 211 /* 212 * OMAP3430 and OMAP3530 are assumed to be same. 213 * 214 * OMAP3525, OMAP3515 and OMAP3503 can be detected only based 215 * on available features. Upon detection, update the CPU id 216 * and CPU class bits. 217 */ 218 if (cpu_is_omap3630()) { 219 cpu_name = "OMAP3630"; 220 } else if (soc_is_am35xx()) { 221 cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505"; 222 } else if (cpu_is_ti816x()) { 223 cpu_name = "TI816X"; 224 } else if (soc_is_am335x()) { 225 cpu_name = "AM335X"; 226 } else if (soc_is_am437x()) { 227 cpu_name = "AM437x"; 228 } else if (cpu_is_ti814x()) { 229 cpu_name = "TI814X"; 230 } else if (omap3_has_iva() && omap3_has_sgx()) { 231 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */ 232 cpu_name = "OMAP3430/3530"; 233 } else if (omap3_has_iva()) { 234 cpu_name = "OMAP3525"; 235 } else if (omap3_has_sgx()) { 236 cpu_name = "OMAP3515"; 237 } else { 238 cpu_name = "OMAP3503"; 239 } 240 241 sprintf(soc_name, "%s", cpu_name); 242 243 /* Print verbose information */ 244 pr_info("%s %s (", soc_name, soc_rev); 245 246 OMAP3_SHOW_FEATURE(l2cache); 247 OMAP3_SHOW_FEATURE(iva); 248 OMAP3_SHOW_FEATURE(sgx); 249 OMAP3_SHOW_FEATURE(neon); 250 OMAP3_SHOW_FEATURE(isp); 251 OMAP3_SHOW_FEATURE(192mhz_clk); 252 253 printk(")\n"); 254 } 255 256 #define OMAP3_CHECK_FEATURE(status,feat) \ 257 if (((status & OMAP3_ ##feat## _MASK) \ 258 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \ 259 omap_features |= OMAP3_HAS_ ##feat; \ 260 } 261 262 void __init omap3xxx_check_features(void) 263 { 264 u32 status; 265 266 omap_features = 0; 267 268 status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS); 269 270 OMAP3_CHECK_FEATURE(status, L2CACHE); 271 OMAP3_CHECK_FEATURE(status, IVA); 272 OMAP3_CHECK_FEATURE(status, SGX); 273 OMAP3_CHECK_FEATURE(status, NEON); 274 OMAP3_CHECK_FEATURE(status, ISP); 275 if (cpu_is_omap3630()) 276 omap_features |= OMAP3_HAS_192MHZ_CLK; 277 if (cpu_is_omap3430() || cpu_is_omap3630()) 278 omap_features |= OMAP3_HAS_IO_WAKEUP; 279 if (cpu_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 || 280 omap_rev() == OMAP3430_REV_ES3_1_2) 281 omap_features |= OMAP3_HAS_IO_CHAIN_CTRL; 282 283 omap_features |= OMAP3_HAS_SDRC; 284 285 /* 286 * am35x fixups: 287 * - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as 288 * reserved and therefore return 0 when read. Unfortunately, 289 * OMAP3_CHECK_FEATURE() will interpret some of those zeroes to 290 * mean that a feature is present even though it isn't so clear 291 * the incorrectly set feature bits. 292 */ 293 if (soc_is_am35xx()) 294 omap_features &= ~(OMAP3_HAS_IVA | OMAP3_HAS_ISP); 295 296 /* 297 * TODO: Get additional info (where applicable) 298 * e.g. Size of L2 cache. 299 */ 300 301 omap3_cpuinfo(); 302 } 303 304 void __init omap4xxx_check_features(void) 305 { 306 u32 si_type; 307 308 si_type = 309 (read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1) >> 16) & 0x03; 310 311 if (si_type == OMAP4_SILICON_TYPE_PERFORMANCE) 312 omap_features = OMAP4_HAS_PERF_SILICON; 313 } 314 315 void __init ti81xx_check_features(void) 316 { 317 omap_features = OMAP3_HAS_NEON; 318 omap3_cpuinfo(); 319 } 320 321 void __init am33xx_check_features(void) 322 { 323 u32 status; 324 325 omap_features = OMAP3_HAS_NEON; 326 327 status = omap_ctrl_readl(AM33XX_DEV_FEATURE); 328 if (status & AM33XX_SGX_MASK) 329 omap_features |= OMAP3_HAS_SGX; 330 331 omap3_cpuinfo(); 332 } 333 334 void __init omap3xxx_check_revision(void) 335 { 336 const char *cpu_rev; 337 u32 cpuid, idcode; 338 u16 hawkeye; 339 u8 rev; 340 341 /* 342 * We cannot access revision registers on ES1.0. 343 * If the processor type is Cortex-A8 and the revision is 0x0 344 * it means its Cortex r0p0 which is 3430 ES1.0. 345 */ 346 cpuid = read_cpuid_id(); 347 if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) { 348 omap_revision = OMAP3430_REV_ES1_0; 349 cpu_rev = "1.0"; 350 return; 351 } 352 353 /* 354 * Detection for 34xx ES2.0 and above can be done with just 355 * hawkeye and rev. See TRM 1.5.2 Device Identification. 356 * Note that rev does not map directly to our defined processor 357 * revision numbers as ES1.0 uses value 0. 358 */ 359 idcode = read_tap_reg(OMAP_TAP_IDCODE); 360 hawkeye = (idcode >> 12) & 0xffff; 361 rev = (idcode >> 28) & 0xff; 362 363 switch (hawkeye) { 364 case 0xb7ae: 365 /* Handle 34xx/35xx devices */ 366 switch (rev) { 367 case 0: /* Take care of early samples */ 368 case 1: 369 omap_revision = OMAP3430_REV_ES2_0; 370 cpu_rev = "2.0"; 371 break; 372 case 2: 373 omap_revision = OMAP3430_REV_ES2_1; 374 cpu_rev = "2.1"; 375 break; 376 case 3: 377 omap_revision = OMAP3430_REV_ES3_0; 378 cpu_rev = "3.0"; 379 break; 380 case 4: 381 omap_revision = OMAP3430_REV_ES3_1; 382 cpu_rev = "3.1"; 383 break; 384 case 7: 385 /* FALLTHROUGH */ 386 default: 387 /* Use the latest known revision as default */ 388 omap_revision = OMAP3430_REV_ES3_1_2; 389 cpu_rev = "3.1.2"; 390 } 391 break; 392 case 0xb868: 393 /* 394 * Handle OMAP/AM 3505/3517 devices 395 * 396 * Set the device to be OMAP3517 here. Actual device 397 * is identified later based on the features. 398 */ 399 switch (rev) { 400 case 0: 401 omap_revision = AM35XX_REV_ES1_0; 402 cpu_rev = "1.0"; 403 break; 404 case 1: 405 /* FALLTHROUGH */ 406 default: 407 omap_revision = AM35XX_REV_ES1_1; 408 cpu_rev = "1.1"; 409 } 410 break; 411 case 0xb891: 412 /* Handle 36xx devices */ 413 414 switch(rev) { 415 case 0: /* Take care of early samples */ 416 omap_revision = OMAP3630_REV_ES1_0; 417 cpu_rev = "1.0"; 418 break; 419 case 1: 420 omap_revision = OMAP3630_REV_ES1_1; 421 cpu_rev = "1.1"; 422 break; 423 case 2: 424 /* FALLTHROUGH */ 425 default: 426 omap_revision = OMAP3630_REV_ES1_2; 427 cpu_rev = "1.2"; 428 } 429 break; 430 case 0xb81e: 431 switch (rev) { 432 case 0: 433 omap_revision = TI8168_REV_ES1_0; 434 cpu_rev = "1.0"; 435 break; 436 case 1: 437 omap_revision = TI8168_REV_ES1_1; 438 cpu_rev = "1.1"; 439 break; 440 case 2: 441 omap_revision = TI8168_REV_ES2_0; 442 cpu_rev = "2.0"; 443 break; 444 case 3: 445 /* FALLTHROUGH */ 446 default: 447 omap_revision = TI8168_REV_ES2_1; 448 cpu_rev = "2.1"; 449 } 450 break; 451 case 0xb944: 452 switch (rev) { 453 case 0: 454 omap_revision = AM335X_REV_ES1_0; 455 cpu_rev = "1.0"; 456 break; 457 case 1: 458 omap_revision = AM335X_REV_ES2_0; 459 cpu_rev = "2.0"; 460 break; 461 case 2: 462 /* FALLTHROUGH */ 463 default: 464 omap_revision = AM335X_REV_ES2_1; 465 cpu_rev = "2.1"; 466 break; 467 } 468 break; 469 case 0xb98c: 470 switch (rev) { 471 case 0: 472 omap_revision = AM437X_REV_ES1_0; 473 cpu_rev = "1.0"; 474 break; 475 case 1: 476 omap_revision = AM437X_REV_ES1_1; 477 cpu_rev = "1.1"; 478 break; 479 case 2: 480 /* FALLTHROUGH */ 481 default: 482 omap_revision = AM437X_REV_ES1_2; 483 cpu_rev = "1.2"; 484 break; 485 } 486 break; 487 case 0xb8f2: 488 switch (rev) { 489 case 0: 490 /* FALLTHROUGH */ 491 case 1: 492 omap_revision = TI8148_REV_ES1_0; 493 cpu_rev = "1.0"; 494 break; 495 case 2: 496 omap_revision = TI8148_REV_ES2_0; 497 cpu_rev = "2.0"; 498 break; 499 case 3: 500 /* FALLTHROUGH */ 501 default: 502 omap_revision = TI8148_REV_ES2_1; 503 cpu_rev = "2.1"; 504 break; 505 } 506 break; 507 default: 508 /* Unknown default to latest silicon rev as default */ 509 omap_revision = OMAP3630_REV_ES1_2; 510 cpu_rev = "1.2"; 511 pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n"); 512 } 513 sprintf(soc_rev, "ES%s", cpu_rev); 514 } 515 516 void __init omap4xxx_check_revision(void) 517 { 518 u32 idcode; 519 u16 hawkeye; 520 u8 rev; 521 522 /* 523 * The IC rev detection is done with hawkeye and rev. 524 * Note that rev does not map directly to defined processor 525 * revision numbers as ES1.0 uses value 0. 526 */ 527 idcode = read_tap_reg(OMAP_TAP_IDCODE); 528 hawkeye = (idcode >> 12) & 0xffff; 529 rev = (idcode >> 28) & 0xf; 530 531 /* 532 * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0 533 * Use ARM register to detect the correct ES version 534 */ 535 if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) { 536 idcode = read_cpuid_id(); 537 rev = (idcode & 0xf) - 1; 538 } 539 540 switch (hawkeye) { 541 case 0xb852: 542 switch (rev) { 543 case 0: 544 omap_revision = OMAP4430_REV_ES1_0; 545 break; 546 case 1: 547 default: 548 omap_revision = OMAP4430_REV_ES2_0; 549 } 550 break; 551 case 0xb95c: 552 switch (rev) { 553 case 3: 554 omap_revision = OMAP4430_REV_ES2_1; 555 break; 556 case 4: 557 omap_revision = OMAP4430_REV_ES2_2; 558 break; 559 case 6: 560 default: 561 omap_revision = OMAP4430_REV_ES2_3; 562 } 563 break; 564 case 0xb94e: 565 switch (rev) { 566 case 0: 567 omap_revision = OMAP4460_REV_ES1_0; 568 break; 569 case 2: 570 default: 571 omap_revision = OMAP4460_REV_ES1_1; 572 break; 573 } 574 break; 575 case 0xb975: 576 switch (rev) { 577 case 0: 578 default: 579 omap_revision = OMAP4470_REV_ES1_0; 580 break; 581 } 582 break; 583 default: 584 /* Unknown default to latest silicon rev as default */ 585 omap_revision = OMAP4430_REV_ES2_3; 586 } 587 588 sprintf(soc_name, "OMAP%04x", omap_rev() >> 16); 589 sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf, 590 (omap_rev() >> 8) & 0xf); 591 pr_info("%s %s\n", soc_name, soc_rev); 592 } 593 594 void __init omap5xxx_check_revision(void) 595 { 596 u32 idcode; 597 u16 hawkeye; 598 u8 rev; 599 600 idcode = read_tap_reg(OMAP_TAP_IDCODE); 601 hawkeye = (idcode >> 12) & 0xffff; 602 rev = (idcode >> 28) & 0xff; 603 switch (hawkeye) { 604 case 0xb942: 605 switch (rev) { 606 case 0: 607 /* No support for ES1.0 Test chip */ 608 BUG(); 609 case 1: 610 default: 611 omap_revision = OMAP5430_REV_ES2_0; 612 } 613 break; 614 615 case 0xb998: 616 switch (rev) { 617 case 0: 618 /* No support for ES1.0 Test chip */ 619 BUG(); 620 case 1: 621 default: 622 omap_revision = OMAP5432_REV_ES2_0; 623 } 624 break; 625 626 default: 627 /* Unknown default to latest silicon rev as default*/ 628 omap_revision = OMAP5430_REV_ES2_0; 629 } 630 631 sprintf(soc_name, "OMAP%04x", omap_rev() >> 16); 632 sprintf(soc_rev, "ES%d.0", (omap_rev() >> 12) & 0xf); 633 634 pr_info("%s %s\n", soc_name, soc_rev); 635 } 636 637 void __init dra7xxx_check_revision(void) 638 { 639 u32 idcode; 640 u16 hawkeye; 641 u8 rev; 642 643 idcode = read_tap_reg(OMAP_TAP_IDCODE); 644 hawkeye = (idcode >> 12) & 0xffff; 645 rev = (idcode >> 28) & 0xff; 646 switch (hawkeye) { 647 case 0xb990: 648 switch (rev) { 649 case 0: 650 omap_revision = DRA752_REV_ES1_0; 651 break; 652 case 1: 653 default: 654 omap_revision = DRA752_REV_ES1_1; 655 } 656 break; 657 658 case 0xb9bc: 659 switch (rev) { 660 case 0: 661 omap_revision = DRA722_REV_ES1_0; 662 break; 663 default: 664 /* If we have no new revisions */ 665 omap_revision = DRA722_REV_ES1_0; 666 break; 667 } 668 break; 669 670 default: 671 /* Unknown default to latest silicon rev as default*/ 672 pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%x)\n", 673 __func__, idcode, hawkeye, rev); 674 omap_revision = DRA752_REV_ES1_1; 675 } 676 677 sprintf(soc_name, "DRA%03x", omap_rev() >> 16); 678 sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf, 679 (omap_rev() >> 8) & 0xf); 680 681 pr_info("%s %s\n", soc_name, soc_rev); 682 } 683 684 /* 685 * Set up things for map_io and processor detection later on. Gets called 686 * pretty much first thing from board init. For multi-omap, this gets 687 * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to 688 * detect the exact revision later on in omap2_detect_revision() once map_io 689 * is done. 690 */ 691 void __init omap2_set_globals_tap(u32 class, void __iomem *tap) 692 { 693 omap_revision = class; 694 tap_base = tap; 695 696 /* XXX What is this intended to do? */ 697 if (cpu_is_omap34xx()) 698 tap_prod_id = 0x0210; 699 else 700 tap_prod_id = 0x0208; 701 } 702 703 #ifdef CONFIG_SOC_BUS 704 705 static const char * const omap_types[] = { 706 [OMAP2_DEVICE_TYPE_TEST] = "TST", 707 [OMAP2_DEVICE_TYPE_EMU] = "EMU", 708 [OMAP2_DEVICE_TYPE_SEC] = "HS", 709 [OMAP2_DEVICE_TYPE_GP] = "GP", 710 [OMAP2_DEVICE_TYPE_BAD] = "BAD", 711 }; 712 713 static const char * __init omap_get_family(void) 714 { 715 if (cpu_is_omap24xx()) 716 return kasprintf(GFP_KERNEL, "OMAP2"); 717 else if (cpu_is_omap34xx()) 718 return kasprintf(GFP_KERNEL, "OMAP3"); 719 else if (cpu_is_omap44xx()) 720 return kasprintf(GFP_KERNEL, "OMAP4"); 721 else if (soc_is_omap54xx()) 722 return kasprintf(GFP_KERNEL, "OMAP5"); 723 else if (soc_is_am43xx()) 724 return kasprintf(GFP_KERNEL, "AM43xx"); 725 else if (soc_is_dra7xx()) 726 return kasprintf(GFP_KERNEL, "DRA7"); 727 else 728 return kasprintf(GFP_KERNEL, "Unknown"); 729 } 730 731 static ssize_t omap_get_type(struct device *dev, 732 struct device_attribute *attr, 733 char *buf) 734 { 735 return sprintf(buf, "%s\n", omap_types[omap_type()]); 736 } 737 738 static struct device_attribute omap_soc_attr = 739 __ATTR(type, S_IRUGO, omap_get_type, NULL); 740 741 void __init omap_soc_device_init(void) 742 { 743 struct device *parent; 744 struct soc_device *soc_dev; 745 struct soc_device_attribute *soc_dev_attr; 746 747 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); 748 if (!soc_dev_attr) 749 return; 750 751 soc_dev_attr->machine = soc_name; 752 soc_dev_attr->family = omap_get_family(); 753 soc_dev_attr->revision = soc_rev; 754 755 soc_dev = soc_device_register(soc_dev_attr); 756 if (IS_ERR(soc_dev)) { 757 kfree(soc_dev_attr); 758 return; 759 } 760 761 parent = soc_device_to_device(soc_dev); 762 device_create_file(parent, &omap_soc_attr); 763 } 764 #endif /* CONFIG_SOC_BUS */ 765