1 /* 2 * linux/arch/arm/mach-omap2/id.c 3 * 4 * OMAP2 CPU identification code 5 * 6 * Copyright (C) 2005 Nokia Corporation 7 * Written by Tony Lindgren <tony@atomide.com> 8 * 9 * Copyright (C) 2009 Texas Instruments 10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License version 2 as 14 * published by the Free Software Foundation. 15 */ 16 17 #include <linux/module.h> 18 #include <linux/kernel.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 22 #include <asm/cputype.h> 23 24 #include <plat/common.h> 25 #include <plat/control.h> 26 #include <plat/cpu.h> 27 28 static struct omap_chip_id omap_chip; 29 static unsigned int omap_revision; 30 31 u32 omap3_features; 32 33 unsigned int omap_rev(void) 34 { 35 return omap_revision; 36 } 37 EXPORT_SYMBOL(omap_rev); 38 39 /** 40 * omap_chip_is - test whether currently running OMAP matches a chip type 41 * @oc: omap_chip_t to test against 42 * 43 * Test whether the currently-running OMAP chip matches the supplied 44 * chip type 'oc'. Returns 1 upon a match; 0 upon failure. 45 */ 46 int omap_chip_is(struct omap_chip_id oci) 47 { 48 return (oci.oc & omap_chip.oc) ? 1 : 0; 49 } 50 EXPORT_SYMBOL(omap_chip_is); 51 52 int omap_type(void) 53 { 54 u32 val = 0; 55 56 if (cpu_is_omap24xx()) { 57 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); 58 } else if (cpu_is_omap34xx()) { 59 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); 60 } else { 61 pr_err("Cannot detect omap type!\n"); 62 goto out; 63 } 64 65 val &= OMAP2_DEVICETYPE_MASK; 66 val >>= 8; 67 68 out: 69 return val; 70 } 71 EXPORT_SYMBOL(omap_type); 72 73 74 /*----------------------------------------------------------------------------*/ 75 76 #define OMAP_TAP_IDCODE 0x0204 77 #define OMAP_TAP_DIE_ID_0 0x0218 78 #define OMAP_TAP_DIE_ID_1 0x021C 79 #define OMAP_TAP_DIE_ID_2 0x0220 80 #define OMAP_TAP_DIE_ID_3 0x0224 81 82 #define read_tap_reg(reg) __raw_readl(tap_base + (reg)) 83 84 struct omap_id { 85 u16 hawkeye; /* Silicon type (Hawkeye id) */ 86 u8 dev; /* Device type from production_id reg */ 87 u32 type; /* Combined type id copied to omap_revision */ 88 }; 89 90 /* Register values to detect the OMAP version */ 91 static struct omap_id omap_ids[] __initdata = { 92 { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 }, 93 { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 }, 94 { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 }, 95 { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 }, 96 { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 }, 97 { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 }, 98 }; 99 100 static void __iomem *tap_base; 101 static u16 tap_prod_id; 102 103 void __init omap24xx_check_revision(void) 104 { 105 int i, j; 106 u32 idcode, prod_id; 107 u16 hawkeye; 108 u8 dev_type, rev; 109 110 idcode = read_tap_reg(OMAP_TAP_IDCODE); 111 prod_id = read_tap_reg(tap_prod_id); 112 hawkeye = (idcode >> 12) & 0xffff; 113 rev = (idcode >> 28) & 0x0f; 114 dev_type = (prod_id >> 16) & 0x0f; 115 116 pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n", 117 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff); 118 pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", 119 read_tap_reg(OMAP_TAP_DIE_ID_0)); 120 pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n", 121 read_tap_reg(OMAP_TAP_DIE_ID_1), 122 (read_tap_reg(OMAP_TAP_DIE_ID_1) >> 28) & 0xf); 123 pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", 124 read_tap_reg(OMAP_TAP_DIE_ID_2)); 125 pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", 126 read_tap_reg(OMAP_TAP_DIE_ID_3)); 127 pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n", 128 prod_id, dev_type); 129 130 /* Check hawkeye ids */ 131 for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { 132 if (hawkeye == omap_ids[i].hawkeye) 133 break; 134 } 135 136 if (i == ARRAY_SIZE(omap_ids)) { 137 printk(KERN_ERR "Unknown OMAP CPU id\n"); 138 return; 139 } 140 141 for (j = i; j < ARRAY_SIZE(omap_ids); j++) { 142 if (dev_type == omap_ids[j].dev) 143 break; 144 } 145 146 if (j == ARRAY_SIZE(omap_ids)) { 147 printk(KERN_ERR "Unknown OMAP device type. " 148 "Handling it as OMAP%04x\n", 149 omap_ids[i].type >> 16); 150 j = i; 151 } 152 153 pr_info("OMAP%04x", omap_rev() >> 16); 154 if ((omap_rev() >> 8) & 0x0f) 155 pr_info("ES%x", (omap_rev() >> 12) & 0xf); 156 pr_info("\n"); 157 } 158 159 #define OMAP3_CHECK_FEATURE(status,feat) \ 160 if (((status & OMAP3_ ##feat## _MASK) \ 161 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \ 162 omap3_features |= OMAP3_HAS_ ##feat; \ 163 } 164 165 void __init omap3_check_features(void) 166 { 167 u32 status; 168 169 omap3_features = 0; 170 171 status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS); 172 173 OMAP3_CHECK_FEATURE(status, L2CACHE); 174 OMAP3_CHECK_FEATURE(status, IVA); 175 OMAP3_CHECK_FEATURE(status, SGX); 176 OMAP3_CHECK_FEATURE(status, NEON); 177 OMAP3_CHECK_FEATURE(status, ISP); 178 179 /* 180 * TODO: Get additional info (where applicable) 181 * e.g. Size of L2 cache. 182 */ 183 } 184 185 void __init omap3_check_revision(void) 186 { 187 u32 cpuid, idcode; 188 u16 hawkeye; 189 u8 rev; 190 191 /* 192 * We cannot access revision registers on ES1.0. 193 * If the processor type is Cortex-A8 and the revision is 0x0 194 * it means its Cortex r0p0 which is 3430 ES1.0. 195 */ 196 cpuid = read_cpuid(CPUID_ID); 197 if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) { 198 omap_revision = OMAP3430_REV_ES1_0; 199 return; 200 } 201 202 /* 203 * Detection for 34xx ES2.0 and above can be done with just 204 * hawkeye and rev. See TRM 1.5.2 Device Identification. 205 * Note that rev does not map directly to our defined processor 206 * revision numbers as ES1.0 uses value 0. 207 */ 208 idcode = read_tap_reg(OMAP_TAP_IDCODE); 209 hawkeye = (idcode >> 12) & 0xffff; 210 rev = (idcode >> 28) & 0xff; 211 212 switch (hawkeye) { 213 case 0xb7ae: 214 /* Handle 34xx/35xx devices */ 215 switch (rev) { 216 case 0: /* Take care of early samples */ 217 case 1: 218 omap_revision = OMAP3430_REV_ES2_0; 219 break; 220 case 2: 221 omap_revision = OMAP3430_REV_ES2_1; 222 break; 223 case 3: 224 omap_revision = OMAP3430_REV_ES3_0; 225 break; 226 case 4: 227 /* FALLTHROUGH */ 228 default: 229 /* Use the latest known revision as default */ 230 omap_revision = OMAP3430_REV_ES3_1; 231 } 232 break; 233 case 0xb868: 234 /* Handle OMAP35xx/AM35xx devices 235 * 236 * Set the device to be OMAP3505 here. Actual device 237 * is identified later based on the features. 238 */ 239 omap_revision = OMAP3505_REV(rev); 240 break; 241 case 0xb891: 242 /* FALLTHROUGH */ 243 default: 244 /* Unknown default to latest silicon rev as default*/ 245 omap_revision = OMAP3630_REV_ES1_0; 246 } 247 } 248 249 void __init omap4_check_revision(void) 250 { 251 u32 idcode; 252 u16 hawkeye; 253 u8 rev; 254 char *rev_name = "ES1.0"; 255 256 /* 257 * The IC rev detection is done with hawkeye and rev. 258 * Note that rev does not map directly to defined processor 259 * revision numbers as ES1.0 uses value 0. 260 */ 261 idcode = read_tap_reg(OMAP_TAP_IDCODE); 262 hawkeye = (idcode >> 12) & 0xffff; 263 rev = (idcode >> 28) & 0xff; 264 265 if ((hawkeye == 0xb852) && (rev == 0x0)) { 266 omap_revision = OMAP4430_REV_ES1_0; 267 pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name); 268 return; 269 } 270 271 pr_err("Unknown OMAP4 CPU id\n"); 272 } 273 274 #define OMAP3_SHOW_FEATURE(feat) \ 275 if (omap3_has_ ##feat()) \ 276 printk(#feat" "); 277 278 void __init omap3_cpuinfo(void) 279 { 280 u8 rev = GET_OMAP_REVISION(); 281 char cpu_name[16], cpu_rev[16]; 282 283 /* OMAP3430 and OMAP3530 are assumed to be same. 284 * 285 * OMAP3525, OMAP3515 and OMAP3503 can be detected only based 286 * on available features. Upon detection, update the CPU id 287 * and CPU class bits. 288 */ 289 if (cpu_is_omap3630()) { 290 strcpy(cpu_name, "OMAP3630"); 291 } else if (cpu_is_omap3505()) { 292 /* 293 * AM35xx devices 294 */ 295 if (omap3_has_sgx()) { 296 omap_revision = OMAP3517_REV(rev); 297 strcpy(cpu_name, "AM3517"); 298 } else { 299 /* Already set in omap3_check_revision() */ 300 strcpy(cpu_name, "AM3505"); 301 } 302 } else if (omap3_has_iva() && omap3_has_sgx()) { 303 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */ 304 strcpy(cpu_name, "OMAP3430/3530"); 305 } else if (omap3_has_iva()) { 306 omap_revision = OMAP3525_REV(rev); 307 strcpy(cpu_name, "OMAP3525"); 308 } else if (omap3_has_sgx()) { 309 omap_revision = OMAP3515_REV(rev); 310 strcpy(cpu_name, "OMAP3515"); 311 } else { 312 omap_revision = OMAP3503_REV(rev); 313 strcpy(cpu_name, "OMAP3503"); 314 } 315 316 switch (rev) { 317 case OMAP_REVBITS_00: 318 strcpy(cpu_rev, "1.0"); 319 break; 320 case OMAP_REVBITS_10: 321 strcpy(cpu_rev, "2.0"); 322 break; 323 case OMAP_REVBITS_20: 324 strcpy(cpu_rev, "2.1"); 325 break; 326 case OMAP_REVBITS_30: 327 strcpy(cpu_rev, "3.0"); 328 break; 329 case OMAP_REVBITS_40: 330 /* FALLTHROUGH */ 331 default: 332 /* Use the latest known revision as default */ 333 strcpy(cpu_rev, "3.1"); 334 } 335 336 /* Print verbose information */ 337 pr_info("%s ES%s (", cpu_name, cpu_rev); 338 339 OMAP3_SHOW_FEATURE(l2cache); 340 OMAP3_SHOW_FEATURE(iva); 341 OMAP3_SHOW_FEATURE(sgx); 342 OMAP3_SHOW_FEATURE(neon); 343 OMAP3_SHOW_FEATURE(isp); 344 345 printk(")\n"); 346 } 347 348 /* 349 * Try to detect the exact revision of the omap we're running on 350 */ 351 void __init omap2_check_revision(void) 352 { 353 /* 354 * At this point we have an idea about the processor revision set 355 * earlier with omap2_set_globals_tap(). 356 */ 357 if (cpu_is_omap24xx()) { 358 omap24xx_check_revision(); 359 } else if (cpu_is_omap34xx()) { 360 omap3_check_revision(); 361 omap3_check_features(); 362 omap3_cpuinfo(); 363 } else if (cpu_is_omap44xx()) { 364 omap4_check_revision(); 365 return; 366 } else { 367 pr_err("OMAP revision unknown, please fix!\n"); 368 } 369 370 /* 371 * OK, now we know the exact revision. Initialize omap_chip bits 372 * for powerdowmain and clockdomain code. 373 */ 374 if (cpu_is_omap243x()) { 375 /* Currently only supports 2430ES2.1 and 2430-all */ 376 omap_chip.oc |= CHIP_IS_OMAP2430; 377 } else if (cpu_is_omap242x()) { 378 /* Currently only supports 2420ES2.1.1 and 2420-all */ 379 omap_chip.oc |= CHIP_IS_OMAP2420; 380 } else if (cpu_is_omap3505() || cpu_is_omap3517()) { 381 omap_chip.oc = CHIP_IS_OMAP3430 | CHIP_IS_OMAP3430ES3_1; 382 } else if (cpu_is_omap343x()) { 383 omap_chip.oc = CHIP_IS_OMAP3430; 384 if (omap_rev() == OMAP3430_REV_ES1_0) 385 omap_chip.oc |= CHIP_IS_OMAP3430ES1; 386 else if (omap_rev() >= OMAP3430_REV_ES2_0 && 387 omap_rev() <= OMAP3430_REV_ES2_1) 388 omap_chip.oc |= CHIP_IS_OMAP3430ES2; 389 else if (omap_rev() == OMAP3430_REV_ES3_0) 390 omap_chip.oc |= CHIP_IS_OMAP3430ES3_0; 391 else if (omap_rev() == OMAP3430_REV_ES3_1) 392 omap_chip.oc |= CHIP_IS_OMAP3430ES3_1; 393 else if (omap_rev() == OMAP3630_REV_ES1_0) 394 omap_chip.oc |= CHIP_IS_OMAP3630ES1; 395 } else { 396 pr_err("Uninitialized omap_chip, please fix!\n"); 397 } 398 } 399 400 /* 401 * Set up things for map_io and processor detection later on. Gets called 402 * pretty much first thing from board init. For multi-omap, this gets 403 * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to 404 * detect the exact revision later on in omap2_detect_revision() once map_io 405 * is done. 406 */ 407 void __init omap2_set_globals_tap(struct omap_globals *omap2_globals) 408 { 409 omap_revision = omap2_globals->class; 410 tap_base = omap2_globals->tap; 411 412 if (cpu_is_omap34xx()) 413 tap_prod_id = 0x0210; 414 else 415 tap_prod_id = 0x0208; 416 } 417