1 /* 2 * linux/arch/arm/mach-omap2/id.c 3 * 4 * OMAP2 CPU identification code 5 * 6 * Copyright (C) 2005 Nokia Corporation 7 * Written by Tony Lindgren <tony@atomide.com> 8 * 9 * Copyright (C) 2009-11 Texas Instruments 10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License version 2 as 14 * published by the Free Software Foundation. 15 */ 16 17 #include <linux/module.h> 18 #include <linux/kernel.h> 19 #include <linux/init.h> 20 #include <linux/io.h> 21 22 #include <asm/cputype.h> 23 24 #include <plat/common.h> 25 #include <plat/cpu.h> 26 27 #include <mach/id.h> 28 29 #include "control.h" 30 31 static struct omap_chip_id omap_chip; 32 static unsigned int omap_revision; 33 34 u32 omap3_features; 35 36 unsigned int omap_rev(void) 37 { 38 return omap_revision; 39 } 40 EXPORT_SYMBOL(omap_rev); 41 42 /** 43 * omap_chip_is - test whether currently running OMAP matches a chip type 44 * @oc: omap_chip_t to test against 45 * 46 * Test whether the currently-running OMAP chip matches the supplied 47 * chip type 'oc'. Returns 1 upon a match; 0 upon failure. 48 */ 49 int omap_chip_is(struct omap_chip_id oci) 50 { 51 return (oci.oc & omap_chip.oc) ? 1 : 0; 52 } 53 EXPORT_SYMBOL(omap_chip_is); 54 55 int omap_type(void) 56 { 57 u32 val = 0; 58 59 if (cpu_is_omap24xx()) { 60 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); 61 } else if (cpu_is_omap34xx()) { 62 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); 63 } else if (cpu_is_omap44xx()) { 64 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS); 65 } else { 66 pr_err("Cannot detect omap type!\n"); 67 goto out; 68 } 69 70 val &= OMAP2_DEVICETYPE_MASK; 71 val >>= 8; 72 73 out: 74 return val; 75 } 76 EXPORT_SYMBOL(omap_type); 77 78 79 /*----------------------------------------------------------------------------*/ 80 81 #define OMAP_TAP_IDCODE 0x0204 82 #define OMAP_TAP_DIE_ID_0 0x0218 83 #define OMAP_TAP_DIE_ID_1 0x021C 84 #define OMAP_TAP_DIE_ID_2 0x0220 85 #define OMAP_TAP_DIE_ID_3 0x0224 86 87 #define OMAP_TAP_DIE_ID_44XX_0 0x0200 88 #define OMAP_TAP_DIE_ID_44XX_1 0x0208 89 #define OMAP_TAP_DIE_ID_44XX_2 0x020c 90 #define OMAP_TAP_DIE_ID_44XX_3 0x0210 91 92 #define read_tap_reg(reg) __raw_readl(tap_base + (reg)) 93 94 struct omap_id { 95 u16 hawkeye; /* Silicon type (Hawkeye id) */ 96 u8 dev; /* Device type from production_id reg */ 97 u32 type; /* Combined type id copied to omap_revision */ 98 }; 99 100 /* Register values to detect the OMAP version */ 101 static struct omap_id omap_ids[] __initdata = { 102 { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 }, 103 { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 }, 104 { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 }, 105 { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 }, 106 { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 }, 107 { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 }, 108 }; 109 110 static void __iomem *tap_base; 111 static u16 tap_prod_id; 112 113 void omap_get_die_id(struct omap_die_id *odi) 114 { 115 if (cpu_is_omap44xx()) { 116 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0); 117 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1); 118 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2); 119 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3); 120 121 return; 122 } 123 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0); 124 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1); 125 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2); 126 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3); 127 } 128 129 static void __init omap24xx_check_revision(void) 130 { 131 int i, j; 132 u32 idcode, prod_id; 133 u16 hawkeye; 134 u8 dev_type, rev; 135 struct omap_die_id odi; 136 137 idcode = read_tap_reg(OMAP_TAP_IDCODE); 138 prod_id = read_tap_reg(tap_prod_id); 139 hawkeye = (idcode >> 12) & 0xffff; 140 rev = (idcode >> 28) & 0x0f; 141 dev_type = (prod_id >> 16) & 0x0f; 142 omap_get_die_id(&odi); 143 144 pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n", 145 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff); 146 pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0); 147 pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n", 148 odi.id_1, (odi.id_1 >> 28) & 0xf); 149 pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2); 150 pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3); 151 pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n", 152 prod_id, dev_type); 153 154 /* Check hawkeye ids */ 155 for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { 156 if (hawkeye == omap_ids[i].hawkeye) 157 break; 158 } 159 160 if (i == ARRAY_SIZE(omap_ids)) { 161 printk(KERN_ERR "Unknown OMAP CPU id\n"); 162 return; 163 } 164 165 for (j = i; j < ARRAY_SIZE(omap_ids); j++) { 166 if (dev_type == omap_ids[j].dev) 167 break; 168 } 169 170 if (j == ARRAY_SIZE(omap_ids)) { 171 printk(KERN_ERR "Unknown OMAP device type. " 172 "Handling it as OMAP%04x\n", 173 omap_ids[i].type >> 16); 174 j = i; 175 } 176 177 pr_info("OMAP%04x", omap_rev() >> 16); 178 if ((omap_rev() >> 8) & 0x0f) 179 pr_info("ES%x", (omap_rev() >> 12) & 0xf); 180 pr_info("\n"); 181 } 182 183 #define OMAP3_CHECK_FEATURE(status,feat) \ 184 if (((status & OMAP3_ ##feat## _MASK) \ 185 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \ 186 omap3_features |= OMAP3_HAS_ ##feat; \ 187 } 188 189 static void __init omap3_check_features(void) 190 { 191 u32 status; 192 193 omap3_features = 0; 194 195 status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS); 196 197 OMAP3_CHECK_FEATURE(status, L2CACHE); 198 OMAP3_CHECK_FEATURE(status, IVA); 199 OMAP3_CHECK_FEATURE(status, SGX); 200 OMAP3_CHECK_FEATURE(status, NEON); 201 OMAP3_CHECK_FEATURE(status, ISP); 202 if (cpu_is_omap3630()) 203 omap3_features |= OMAP3_HAS_192MHZ_CLK; 204 if (!cpu_is_omap3505() && !cpu_is_omap3517()) 205 omap3_features |= OMAP3_HAS_IO_WAKEUP; 206 207 omap3_features |= OMAP3_HAS_SDRC; 208 209 /* 210 * TODO: Get additional info (where applicable) 211 * e.g. Size of L2 cache. 212 */ 213 } 214 215 static void __init ti816x_check_features(void) 216 { 217 omap3_features = OMAP3_HAS_NEON; 218 } 219 220 static void __init omap3_check_revision(void) 221 { 222 u32 cpuid, idcode; 223 u16 hawkeye; 224 u8 rev; 225 226 omap_chip.oc = CHIP_IS_OMAP3430; 227 228 /* 229 * We cannot access revision registers on ES1.0. 230 * If the processor type is Cortex-A8 and the revision is 0x0 231 * it means its Cortex r0p0 which is 3430 ES1.0. 232 */ 233 cpuid = read_cpuid(CPUID_ID); 234 if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) { 235 omap_revision = OMAP3430_REV_ES1_0; 236 omap_chip.oc |= CHIP_IS_OMAP3430ES1; 237 return; 238 } 239 240 /* 241 * Detection for 34xx ES2.0 and above can be done with just 242 * hawkeye and rev. See TRM 1.5.2 Device Identification. 243 * Note that rev does not map directly to our defined processor 244 * revision numbers as ES1.0 uses value 0. 245 */ 246 idcode = read_tap_reg(OMAP_TAP_IDCODE); 247 hawkeye = (idcode >> 12) & 0xffff; 248 rev = (idcode >> 28) & 0xff; 249 250 switch (hawkeye) { 251 case 0xb7ae: 252 /* Handle 34xx/35xx devices */ 253 switch (rev) { 254 case 0: /* Take care of early samples */ 255 case 1: 256 omap_revision = OMAP3430_REV_ES2_0; 257 omap_chip.oc |= CHIP_IS_OMAP3430ES2; 258 break; 259 case 2: 260 omap_revision = OMAP3430_REV_ES2_1; 261 omap_chip.oc |= CHIP_IS_OMAP3430ES2; 262 break; 263 case 3: 264 omap_revision = OMAP3430_REV_ES3_0; 265 omap_chip.oc |= CHIP_IS_OMAP3430ES3_0; 266 break; 267 case 4: 268 omap_revision = OMAP3430_REV_ES3_1; 269 omap_chip.oc |= CHIP_IS_OMAP3430ES3_1; 270 break; 271 case 7: 272 /* FALLTHROUGH */ 273 default: 274 /* Use the latest known revision as default */ 275 omap_revision = OMAP3430_REV_ES3_1_2; 276 277 /* REVISIT: Add CHIP_IS_OMAP3430ES3_1_2? */ 278 omap_chip.oc |= CHIP_IS_OMAP3430ES3_1; 279 } 280 break; 281 case 0xb868: 282 /* Handle OMAP35xx/AM35xx devices 283 * 284 * Set the device to be OMAP3505 here. Actual device 285 * is identified later based on the features. 286 * 287 * REVISIT: AM3505/AM3517 should have their own CHIP_IS 288 */ 289 omap_revision = OMAP3505_REV(rev); 290 omap_chip.oc |= CHIP_IS_OMAP3430ES3_1; 291 break; 292 case 0xb891: 293 /* Handle 36xx devices */ 294 omap_chip.oc |= CHIP_IS_OMAP3630ES1; 295 296 switch(rev) { 297 case 0: /* Take care of early samples */ 298 omap_revision = OMAP3630_REV_ES1_0; 299 break; 300 case 1: 301 omap_revision = OMAP3630_REV_ES1_1; 302 omap_chip.oc |= CHIP_IS_OMAP3630ES1_1; 303 break; 304 case 2: 305 default: 306 omap_revision = OMAP3630_REV_ES1_2; 307 omap_chip.oc |= CHIP_IS_OMAP3630ES1_2; 308 } 309 break; 310 case 0xb81e: 311 omap_chip.oc = CHIP_IS_TI816X; 312 313 switch (rev) { 314 case 0: 315 omap_revision = TI8168_REV_ES1_0; 316 break; 317 case 1: 318 omap_revision = TI8168_REV_ES1_1; 319 break; 320 default: 321 omap_revision = TI8168_REV_ES1_1; 322 } 323 break; 324 default: 325 /* Unknown default to latest silicon rev as default*/ 326 omap_revision = OMAP3630_REV_ES1_2; 327 omap_chip.oc |= CHIP_IS_OMAP3630ES1_2; 328 } 329 } 330 331 static void __init omap4_check_revision(void) 332 { 333 u32 idcode; 334 u16 hawkeye; 335 u8 rev; 336 337 /* 338 * The IC rev detection is done with hawkeye and rev. 339 * Note that rev does not map directly to defined processor 340 * revision numbers as ES1.0 uses value 0. 341 */ 342 idcode = read_tap_reg(OMAP_TAP_IDCODE); 343 hawkeye = (idcode >> 12) & 0xffff; 344 rev = (idcode >> 28) & 0xf; 345 346 /* 347 * Few initial ES2.0 samples IDCODE is same as ES1.0 348 * Use ARM register to detect the correct ES version 349 */ 350 if (!rev) { 351 idcode = read_cpuid(CPUID_ID); 352 rev = (idcode & 0xf) - 1; 353 } 354 355 switch (hawkeye) { 356 case 0xb852: 357 switch (rev) { 358 case 0: 359 omap_revision = OMAP4430_REV_ES1_0; 360 omap_chip.oc |= CHIP_IS_OMAP4430ES1; 361 break; 362 case 1: 363 default: 364 omap_revision = OMAP4430_REV_ES2_0; 365 omap_chip.oc |= CHIP_IS_OMAP4430ES2; 366 } 367 break; 368 case 0xb95c: 369 switch (rev) { 370 case 3: 371 omap_revision = OMAP4430_REV_ES2_1; 372 omap_chip.oc |= CHIP_IS_OMAP4430ES2_1; 373 break; 374 case 4: 375 default: 376 omap_revision = OMAP4430_REV_ES2_2; 377 omap_chip.oc |= CHIP_IS_OMAP4430ES2_2; 378 } 379 break; 380 default: 381 /* Unknown default to latest silicon rev as default */ 382 omap_revision = OMAP4430_REV_ES2_2; 383 omap_chip.oc |= CHIP_IS_OMAP4430ES2_2; 384 } 385 386 pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16, 387 ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf)); 388 } 389 390 #define OMAP3_SHOW_FEATURE(feat) \ 391 if (omap3_has_ ##feat()) \ 392 printk(#feat" "); 393 394 static void __init omap3_cpuinfo(void) 395 { 396 u8 rev = GET_OMAP_REVISION(); 397 char cpu_name[16], cpu_rev[16]; 398 399 /* OMAP3430 and OMAP3530 are assumed to be same. 400 * 401 * OMAP3525, OMAP3515 and OMAP3503 can be detected only based 402 * on available features. Upon detection, update the CPU id 403 * and CPU class bits. 404 */ 405 if (cpu_is_omap3630()) { 406 strcpy(cpu_name, "OMAP3630"); 407 } else if (cpu_is_omap3505()) { 408 /* 409 * AM35xx devices 410 */ 411 if (omap3_has_sgx()) { 412 omap_revision = OMAP3517_REV(rev); 413 strcpy(cpu_name, "AM3517"); 414 } else { 415 /* Already set in omap3_check_revision() */ 416 strcpy(cpu_name, "AM3505"); 417 } 418 } else if (cpu_is_ti816x()) { 419 strcpy(cpu_name, "TI816X"); 420 } else if (omap3_has_iva() && omap3_has_sgx()) { 421 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */ 422 strcpy(cpu_name, "OMAP3430/3530"); 423 } else if (omap3_has_iva()) { 424 omap_revision = OMAP3525_REV(rev); 425 strcpy(cpu_name, "OMAP3525"); 426 } else if (omap3_has_sgx()) { 427 omap_revision = OMAP3515_REV(rev); 428 strcpy(cpu_name, "OMAP3515"); 429 } else { 430 omap_revision = OMAP3503_REV(rev); 431 strcpy(cpu_name, "OMAP3503"); 432 } 433 434 if (cpu_is_omap3630() || cpu_is_ti816x()) { 435 switch (rev) { 436 case OMAP_REVBITS_00: 437 strcpy(cpu_rev, "1.0"); 438 break; 439 case OMAP_REVBITS_01: 440 strcpy(cpu_rev, "1.1"); 441 break; 442 case OMAP_REVBITS_02: 443 /* FALLTHROUGH */ 444 default: 445 /* Use the latest known revision as default */ 446 strcpy(cpu_rev, "1.2"); 447 } 448 } else if (cpu_is_omap3505() || cpu_is_omap3517()) { 449 switch (rev) { 450 case OMAP_REVBITS_00: 451 strcpy(cpu_rev, "1.0"); 452 break; 453 case OMAP_REVBITS_01: 454 /* FALLTHROUGH */ 455 default: 456 /* Use the latest known revision as default */ 457 strcpy(cpu_rev, "1.1"); 458 } 459 } else { 460 switch (rev) { 461 case OMAP_REVBITS_00: 462 strcpy(cpu_rev, "1.0"); 463 break; 464 case OMAP_REVBITS_01: 465 strcpy(cpu_rev, "2.0"); 466 break; 467 case OMAP_REVBITS_02: 468 strcpy(cpu_rev, "2.1"); 469 break; 470 case OMAP_REVBITS_03: 471 strcpy(cpu_rev, "3.0"); 472 break; 473 case OMAP_REVBITS_04: 474 strcpy(cpu_rev, "3.1"); 475 break; 476 case OMAP_REVBITS_05: 477 /* FALLTHROUGH */ 478 default: 479 /* Use the latest known revision as default */ 480 strcpy(cpu_rev, "3.1.2"); 481 } 482 } 483 484 /* Print verbose information */ 485 pr_info("%s ES%s (", cpu_name, cpu_rev); 486 487 OMAP3_SHOW_FEATURE(l2cache); 488 OMAP3_SHOW_FEATURE(iva); 489 OMAP3_SHOW_FEATURE(sgx); 490 OMAP3_SHOW_FEATURE(neon); 491 OMAP3_SHOW_FEATURE(isp); 492 OMAP3_SHOW_FEATURE(192mhz_clk); 493 494 printk(")\n"); 495 } 496 497 /* 498 * Try to detect the exact revision of the omap we're running on 499 */ 500 void __init omap2_check_revision(void) 501 { 502 /* 503 * At this point we have an idea about the processor revision set 504 * earlier with omap2_set_globals_tap(). 505 */ 506 if (cpu_is_omap24xx()) { 507 omap24xx_check_revision(); 508 } else if (cpu_is_omap34xx()) { 509 omap3_check_revision(); 510 511 /* TI816X doesn't have feature register */ 512 if (!cpu_is_ti816x()) 513 omap3_check_features(); 514 else 515 ti816x_check_features(); 516 517 omap3_cpuinfo(); 518 return; 519 } else if (cpu_is_omap44xx()) { 520 omap4_check_revision(); 521 return; 522 } else { 523 pr_err("OMAP revision unknown, please fix!\n"); 524 } 525 526 /* 527 * OK, now we know the exact revision. Initialize omap_chip bits 528 * for powerdowmain and clockdomain code. 529 */ 530 if (cpu_is_omap243x()) { 531 /* Currently only supports 2430ES2.1 and 2430-all */ 532 omap_chip.oc |= CHIP_IS_OMAP2430; 533 return; 534 } else if (cpu_is_omap242x()) { 535 /* Currently only supports 2420ES2.1.1 and 2420-all */ 536 omap_chip.oc |= CHIP_IS_OMAP2420; 537 return; 538 } 539 540 pr_err("Uninitialized omap_chip, please fix!\n"); 541 } 542 543 /* 544 * Set up things for map_io and processor detection later on. Gets called 545 * pretty much first thing from board init. For multi-omap, this gets 546 * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to 547 * detect the exact revision later on in omap2_detect_revision() once map_io 548 * is done. 549 */ 550 void __init omap2_set_globals_tap(struct omap_globals *omap2_globals) 551 { 552 omap_revision = omap2_globals->class; 553 tap_base = omap2_globals->tap; 554 555 if (cpu_is_omap34xx()) 556 tap_prod_id = 0x0210; 557 else 558 tap_prod_id = 0x0208; 559 } 560