xref: /openbmc/linux/arch/arm/mach-omap2/i2c.c (revision 6d99a79c)
1 /*
2  * Helper module for board specific I2C bus registration
3  *
4  * Copyright (C) 2009 Nokia Corporation.
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License
8  * version 2 as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful, but
11  * WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
13  * General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18  * 02110-1301 USA
19  *
20  */
21 
22 #include "soc.h"
23 #include "omap_hwmod.h"
24 #include "omap_device.h"
25 
26 #include "prm.h"
27 #include "common.h"
28 #include "i2c.h"
29 
30 /* In register I2C_CON, Bit 15 is the I2C enable bit */
31 #define I2C_EN					BIT(15)
32 #define OMAP2_I2C_CON_OFFSET			0x24
33 #define OMAP4_I2C_CON_OFFSET			0xA4
34 
35 #define MAX_OMAP_I2C_HWMOD_NAME_LEN	16
36 
37 /**
38  * omap_i2c_reset - reset the omap i2c module.
39  * @oh: struct omap_hwmod *
40  *
41  * The i2c moudle in omap2, omap3 had a special sequence to reset. The
42  * sequence is:
43  * - Disable the I2C.
44  * - Write to SOFTRESET bit.
45  * - Enable the I2C.
46  * - Poll on the RESETDONE bit.
47  * The sequence is implemented in below function. This is called for 2420,
48  * 2430 and omap3.
49  */
50 int omap_i2c_reset(struct omap_hwmod *oh)
51 {
52 	u32 v;
53 	u16 i2c_con;
54 	int c = 0;
55 
56 	if (oh->class->rev == OMAP_I2C_IP_VERSION_2) {
57 		i2c_con = OMAP4_I2C_CON_OFFSET;
58 	} else if (oh->class->rev == OMAP_I2C_IP_VERSION_1) {
59 		i2c_con = OMAP2_I2C_CON_OFFSET;
60 	} else {
61 		WARN(1, "Cannot reset I2C block %s: unsupported revision\n",
62 		     oh->name);
63 		return -EINVAL;
64 	}
65 
66 	/* Disable I2C */
67 	v = omap_hwmod_read(oh, i2c_con);
68 	v &= ~I2C_EN;
69 	omap_hwmod_write(v, oh, i2c_con);
70 
71 	/* Write to the SOFTRESET bit */
72 	omap_hwmod_softreset(oh);
73 
74 	/* Enable I2C */
75 	v = omap_hwmod_read(oh, i2c_con);
76 	v |= I2C_EN;
77 	omap_hwmod_write(v, oh, i2c_con);
78 
79 	/* Poll on RESETDONE bit */
80 	omap_test_timeout((omap_hwmod_read(oh,
81 				oh->class->sysc->syss_offs)
82 				& SYSS_RESETDONE_MASK),
83 				MAX_MODULE_SOFTRESET_WAIT, c);
84 
85 	if (c == MAX_MODULE_SOFTRESET_WAIT)
86 		pr_warn("%s: %s: softreset failed (waited %d usec)\n",
87 			__func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
88 	else
89 		pr_debug("%s: %s: softreset in %d usec\n", __func__,
90 			oh->name, c);
91 
92 	return 0;
93 }
94