1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * IP block integration code for the HDQ1W/1-wire IP block 4 * 5 * Copyright (C) 2012 Texas Instruments, Inc. 6 * Paul Walmsley 7 * 8 * Based on the I2C reset code in arch/arm/mach-omap2/i2c.c by 9 * Avinash.H.M <avinashhm@ti.com> 10 */ 11 12 #include <linux/kernel.h> 13 #include <linux/init.h> 14 #include <linux/err.h> 15 #include <linux/platform_device.h> 16 17 #include "soc.h" 18 #include "omap_hwmod.h" 19 #include "omap_device.h" 20 #include "hdq1w.h" 21 22 #include "prm.h" 23 #include "common.h" 24 25 /** 26 * omap_hdq1w_reset - reset the OMAP HDQ1W module 27 * @oh: struct omap_hwmod * 28 * 29 * OCP soft reset the HDQ1W IP block. Section 20.6.1.4 "HDQ1W/1-Wire 30 * Software Reset" of the OMAP34xx Technical Reference Manual Revision 31 * ZR (SWPU223R) does not include the rather important fact that, for 32 * the reset to succeed, the HDQ1W module's internal clock gate must be 33 * programmed to allow the clock to propagate to the rest of the 34 * module. In this sense, it's rather similar to the I2C custom reset 35 * function. Returns 0. 36 */ 37 int omap_hdq1w_reset(struct omap_hwmod *oh) 38 { 39 u32 v; 40 int c = 0; 41 42 /* Write to the SOFTRESET bit */ 43 omap_hwmod_softreset(oh); 44 45 /* Enable the module's internal clocks */ 46 v = omap_hwmod_read(oh, HDQ_CTRL_STATUS_OFFSET); 47 v |= 1 << HDQ_CTRL_STATUS_CLOCKENABLE_SHIFT; 48 omap_hwmod_write(v, oh, HDQ_CTRL_STATUS_OFFSET); 49 50 /* Poll on RESETDONE bit */ 51 omap_test_timeout((omap_hwmod_read(oh, 52 oh->class->sysc->syss_offs) 53 & SYSS_RESETDONE_MASK), 54 MAX_MODULE_SOFTRESET_WAIT, c); 55 56 if (c == MAX_MODULE_SOFTRESET_WAIT) 57 pr_warn("%s: %s: softreset failed (waited %d usec)\n", 58 __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT); 59 else 60 pr_debug("%s: %s: softreset in %d usec\n", __func__, 61 oh->name, c); 62 63 return 0; 64 } 65