1 /* 2 * IP block integration code for the HDQ1W/1-wire IP block 3 * 4 * Copyright (C) 2012 Texas Instruments, Inc. 5 * Paul Walmsley 6 * 7 * Based on the I2C reset code in arch/arm/mach-omap2/i2c.c by 8 * Avinash.H.M <avinashhm@ti.com> 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License 12 * version 2 as published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but 15 * WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 22 * 02110-1301 USA 23 */ 24 25 #include <linux/kernel.h> 26 #include <linux/init.h> 27 #include <linux/err.h> 28 #include <linux/platform_device.h> 29 30 #include <plat/omap_hwmod.h> 31 #include <plat/omap_device.h> 32 #include "hdq1w.h" 33 34 #include "common.h" 35 36 /* Maximum microseconds to wait for OMAP module to softreset */ 37 #define MAX_MODULE_SOFTRESET_WAIT 10000 38 39 /** 40 * omap_hdq1w_reset - reset the OMAP HDQ1W module 41 * @oh: struct omap_hwmod * 42 * 43 * OCP soft reset the HDQ1W IP block. Section 20.6.1.4 "HDQ1W/1-Wire 44 * Software Reset" of the OMAP34xx Technical Reference Manual Revision 45 * ZR (SWPU223R) does not include the rather important fact that, for 46 * the reset to succeed, the HDQ1W module's internal clock gate must be 47 * programmed to allow the clock to propagate to the rest of the 48 * module. In this sense, it's rather similar to the I2C custom reset 49 * function. Returns 0. 50 */ 51 int omap_hdq1w_reset(struct omap_hwmod *oh) 52 { 53 u32 v; 54 int c = 0; 55 56 /* Write to the SOFTRESET bit */ 57 omap_hwmod_softreset(oh); 58 59 /* Enable the module's internal clocks */ 60 v = omap_hwmod_read(oh, HDQ_CTRL_STATUS_OFFSET); 61 v |= 1 << HDQ_CTRL_STATUS_CLOCKENABLE_SHIFT; 62 omap_hwmod_write(v, oh, HDQ_CTRL_STATUS_OFFSET); 63 64 /* Poll on RESETDONE bit */ 65 omap_test_timeout((omap_hwmod_read(oh, 66 oh->class->sysc->syss_offs) 67 & SYSS_RESETDONE_MASK), 68 MAX_MODULE_SOFTRESET_WAIT, c); 69 70 if (c == MAX_MODULE_SOFTRESET_WAIT) 71 pr_warning("%s: %s: softreset failed (waited %d usec)\n", 72 __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT); 73 else 74 pr_debug("%s: %s: softreset in %d usec\n", __func__, 75 oh->name, c); 76 77 return 0; 78 } 79 80 static int __init omap_init_hdq(void) 81 { 82 int id = -1; 83 struct platform_device *pdev; 84 struct omap_hwmod *oh; 85 char *oh_name = "hdq1w"; 86 char *devname = "omap_hdq"; 87 88 oh = omap_hwmod_lookup(oh_name); 89 if (!oh) 90 return 0; 91 92 pdev = omap_device_build(devname, id, oh, NULL, 0, NULL, 0, 0); 93 WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n", 94 devname, oh->name); 95 96 return 0; 97 } 98 arch_initcall(omap_init_hdq); 99