1 /* 2 * General-Purpose Memory Controller for OMAP2 3 * 4 * Copyright (C) 2005-2006 Nokia Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef __OMAP2_GPMC_H 12 #define __OMAP2_GPMC_H 13 14 #include <linux/platform_data/mtd-nand-omap2.h> 15 16 /* Maximum Number of Chip Selects */ 17 #define GPMC_CS_NUM 8 18 19 #define GPMC_CS_CONFIG1 0x00 20 #define GPMC_CS_CONFIG2 0x04 21 #define GPMC_CS_CONFIG3 0x08 22 #define GPMC_CS_CONFIG4 0x0c 23 #define GPMC_CS_CONFIG5 0x10 24 #define GPMC_CS_CONFIG6 0x14 25 #define GPMC_CS_CONFIG7 0x18 26 #define GPMC_CS_NAND_COMMAND 0x1c 27 #define GPMC_CS_NAND_ADDRESS 0x20 28 #define GPMC_CS_NAND_DATA 0x24 29 30 /* Control Commands */ 31 #define GPMC_CONFIG_RDY_BSY 0x00000001 32 #define GPMC_CONFIG_DEV_SIZE 0x00000002 33 #define GPMC_CONFIG_DEV_TYPE 0x00000003 34 #define GPMC_SET_IRQ_STATUS 0x00000004 35 #define GPMC_CONFIG_WP 0x00000005 36 37 #define GPMC_ENABLE_IRQ 0x0000000d 38 39 /* ECC commands */ 40 #define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */ 41 #define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */ 42 #define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */ 43 44 #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31) 45 #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30) 46 #define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29) 47 #define GPMC_CONFIG1_READTYPE_SYNC (1 << 29) 48 #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28) 49 #define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27) 50 #define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27) 51 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25) 52 #define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23) 53 #define GPMC_CONFIG1_WAIT_READ_MON (1 << 22) 54 #define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21) 55 #define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18) 56 #define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16) 57 #define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12) 58 #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1) 59 #define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10) 60 #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0) 61 #define GPMC_CONFIG1_MUXTYPE(val) ((val & 3) << 8) 62 #define GPMC_CONFIG1_MUXNONMUX GPMC_CONFIG1_MUXTYPE(0) 63 #define GPMC_CONFIG1_MUXAAD GPMC_CONFIG1_MUXTYPE(1) 64 #define GPMC_CONFIG1_MUXADDDATA GPMC_CONFIG1_MUXTYPE(2) 65 #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4) 66 #define GPMC_CONFIG1_FCLK_DIV(val) (val & 3) 67 #define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1)) 68 #define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2)) 69 #define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3)) 70 #define GPMC_CONFIG7_CSVALID (1 << 6) 71 72 #define GPMC_DEVICETYPE_NOR 0 73 #define GPMC_DEVICETYPE_NAND 2 74 #define GPMC_CONFIG_WRITEPROTECT 0x00000010 75 #define WR_RD_PIN_MONITORING 0x00600000 76 #define GPMC_IRQ_FIFOEVENTENABLE 0x01 77 #define GPMC_IRQ_COUNT_EVENT 0x02 78 79 80 /* bool type time settings */ 81 struct gpmc_bool_timings { 82 bool cycle2cyclediffcsen; 83 bool cycle2cyclesamecsen; 84 bool we_extra_delay; 85 bool oe_extra_delay; 86 bool adv_extra_delay; 87 bool cs_extra_delay; 88 bool time_para_granularity; 89 }; 90 91 /* 92 * Note that all values in this struct are in nanoseconds except sync_clk 93 * (which is in picoseconds), while the register values are in gpmc_fck cycles. 94 */ 95 struct gpmc_timings { 96 /* Minimum clock period for synchronous mode (in picoseconds) */ 97 u32 sync_clk; 98 99 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */ 100 u32 cs_on; /* Assertion time */ 101 u32 cs_rd_off; /* Read deassertion time */ 102 u32 cs_wr_off; /* Write deassertion time */ 103 104 /* ADV signal timings corresponding to GPMC_CONFIG3 */ 105 u32 adv_on; /* Assertion time */ 106 u32 adv_rd_off; /* Read deassertion time */ 107 u32 adv_wr_off; /* Write deassertion time */ 108 109 /* WE signals timings corresponding to GPMC_CONFIG4 */ 110 u32 we_on; /* WE assertion time */ 111 u32 we_off; /* WE deassertion time */ 112 113 /* OE signals timings corresponding to GPMC_CONFIG4 */ 114 u32 oe_on; /* OE assertion time */ 115 u32 oe_off; /* OE deassertion time */ 116 117 /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */ 118 u32 page_burst_access; /* Multiple access word delay */ 119 u32 access; /* Start-cycle to first data valid delay */ 120 u32 rd_cycle; /* Total read cycle time */ 121 u32 wr_cycle; /* Total write cycle time */ 122 123 u32 bus_turnaround; 124 u32 cycle2cycle_delay; 125 126 u32 wait_monitoring; 127 u32 clk_activation; 128 129 /* The following are only on OMAP3430 */ 130 u32 wr_access; /* WRACCESSTIME */ 131 u32 wr_data_mux_bus; /* WRDATAONADMUXBUS */ 132 133 struct gpmc_bool_timings bool_timings; 134 }; 135 136 /* Device timings in picoseconds */ 137 struct gpmc_device_timings { 138 u32 t_ceasu; /* address setup to CS valid */ 139 u32 t_avdasu; /* address setup to ADV valid */ 140 /* XXX: try to combine t_avdp_r & t_avdp_w. Issue is 141 * of tusb using these timings even for sync whilst 142 * ideally for adv_rd/(wr)_off it should have considered 143 * t_avdh instead. This indirectly necessitates r/w 144 * variations of t_avdp as it is possible to have one 145 * sync & other async 146 */ 147 u32 t_avdp_r; /* ADV low time (what about t_cer ?) */ 148 u32 t_avdp_w; 149 u32 t_aavdh; /* address hold time */ 150 u32 t_oeasu; /* address setup to OE valid */ 151 u32 t_aa; /* access time from ADV assertion */ 152 u32 t_iaa; /* initial access time */ 153 u32 t_oe; /* access time from OE assertion */ 154 u32 t_ce; /* access time from CS asertion */ 155 u32 t_rd_cycle; /* read cycle time */ 156 u32 t_cez_r; /* read CS deassertion to high Z */ 157 u32 t_cez_w; /* write CS deassertion to high Z */ 158 u32 t_oez; /* OE deassertion to high Z */ 159 u32 t_weasu; /* address setup to WE valid */ 160 u32 t_wpl; /* write assertion time */ 161 u32 t_wph; /* write deassertion time */ 162 u32 t_wr_cycle; /* write cycle time */ 163 164 u32 clk; 165 u32 t_bacc; /* burst access valid clock to output delay */ 166 u32 t_ces; /* CS setup time to clk */ 167 u32 t_avds; /* ADV setup time to clk */ 168 u32 t_avdh; /* ADV hold time from clk */ 169 u32 t_ach; /* address hold time from clk */ 170 u32 t_rdyo; /* clk to ready valid */ 171 172 u32 t_ce_rdyz; /* XXX: description ?, or use t_cez instead */ 173 u32 t_ce_avd; /* CS on to ADV on delay */ 174 175 /* XXX: check the possibility of combining 176 * cyc_aavhd_oe & cyc_aavdh_we 177 */ 178 u8 cyc_aavdh_oe;/* read address hold time in cycles */ 179 u8 cyc_aavdh_we;/* write address hold time in cycles */ 180 u8 cyc_oe; /* access time from OE assertion in cycles */ 181 u8 cyc_wpl; /* write deassertion time in cycles */ 182 u32 cyc_iaa; /* initial access time in cycles */ 183 184 bool mux; /* address & data muxed */ 185 bool sync_write;/* synchronous write */ 186 bool sync_read; /* synchronous read */ 187 188 /* extra delays */ 189 bool ce_xdelay; 190 bool avd_xdelay; 191 bool oe_xdelay; 192 bool we_xdelay; 193 }; 194 195 extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t, 196 struct gpmc_device_timings *dev_t); 197 198 extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs); 199 extern int gpmc_get_client_irq(unsigned irq_config); 200 201 extern unsigned int gpmc_ticks_to_ns(unsigned int ticks); 202 203 extern void gpmc_cs_write_reg(int cs, int idx, u32 val); 204 extern int gpmc_calc_divider(unsigned int sync_clk); 205 extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t); 206 extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base); 207 extern void gpmc_cs_free(int cs); 208 extern void omap3_gpmc_save_context(void); 209 extern void omap3_gpmc_restore_context(void); 210 extern int gpmc_cs_configure(int cs, int cmd, int wval); 211 212 #endif 213