13ef5d007SAfzal Mohammed /* 23ef5d007SAfzal Mohammed * General-Purpose Memory Controller for OMAP2 33ef5d007SAfzal Mohammed * 43ef5d007SAfzal Mohammed * Copyright (C) 2005-2006 Nokia Corporation 53ef5d007SAfzal Mohammed * 63ef5d007SAfzal Mohammed * This program is free software; you can redistribute it and/or modify 73ef5d007SAfzal Mohammed * it under the terms of the GNU General Public License version 2 as 83ef5d007SAfzal Mohammed * published by the Free Software Foundation. 93ef5d007SAfzal Mohammed */ 103ef5d007SAfzal Mohammed 113ef5d007SAfzal Mohammed #ifndef __OMAP2_GPMC_H 123ef5d007SAfzal Mohammed #define __OMAP2_GPMC_H 133ef5d007SAfzal Mohammed 143ef5d007SAfzal Mohammed #include <linux/platform_data/mtd-nand-omap2.h> 153ef5d007SAfzal Mohammed 163ef5d007SAfzal Mohammed /* Maximum Number of Chip Selects */ 173ef5d007SAfzal Mohammed #define GPMC_CS_NUM 8 183ef5d007SAfzal Mohammed 193ef5d007SAfzal Mohammed #define GPMC_CS_CONFIG1 0x00 203ef5d007SAfzal Mohammed #define GPMC_CS_CONFIG2 0x04 213ef5d007SAfzal Mohammed #define GPMC_CS_CONFIG3 0x08 223ef5d007SAfzal Mohammed #define GPMC_CS_CONFIG4 0x0c 233ef5d007SAfzal Mohammed #define GPMC_CS_CONFIG5 0x10 243ef5d007SAfzal Mohammed #define GPMC_CS_CONFIG6 0x14 253ef5d007SAfzal Mohammed #define GPMC_CS_CONFIG7 0x18 263ef5d007SAfzal Mohammed #define GPMC_CS_NAND_COMMAND 0x1c 273ef5d007SAfzal Mohammed #define GPMC_CS_NAND_ADDRESS 0x20 283ef5d007SAfzal Mohammed #define GPMC_CS_NAND_DATA 0x24 293ef5d007SAfzal Mohammed 303ef5d007SAfzal Mohammed /* Control Commands */ 313ef5d007SAfzal Mohammed #define GPMC_CONFIG_RDY_BSY 0x00000001 323ef5d007SAfzal Mohammed #define GPMC_CONFIG_DEV_SIZE 0x00000002 333ef5d007SAfzal Mohammed #define GPMC_CONFIG_DEV_TYPE 0x00000003 343ef5d007SAfzal Mohammed #define GPMC_SET_IRQ_STATUS 0x00000004 353ef5d007SAfzal Mohammed #define GPMC_CONFIG_WP 0x00000005 363ef5d007SAfzal Mohammed 373ef5d007SAfzal Mohammed #define GPMC_ENABLE_IRQ 0x0000000d 383ef5d007SAfzal Mohammed 393ef5d007SAfzal Mohammed /* ECC commands */ 403ef5d007SAfzal Mohammed #define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */ 413ef5d007SAfzal Mohammed #define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */ 423ef5d007SAfzal Mohammed #define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */ 433ef5d007SAfzal Mohammed 443ef5d007SAfzal Mohammed #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31) 453ef5d007SAfzal Mohammed #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30) 463ef5d007SAfzal Mohammed #define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29) 473ef5d007SAfzal Mohammed #define GPMC_CONFIG1_READTYPE_SYNC (1 << 29) 483ef5d007SAfzal Mohammed #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28) 493ef5d007SAfzal Mohammed #define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27) 503ef5d007SAfzal Mohammed #define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27) 513ef5d007SAfzal Mohammed #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25) 523ef5d007SAfzal Mohammed #define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23) 533ef5d007SAfzal Mohammed #define GPMC_CONFIG1_WAIT_READ_MON (1 << 22) 543ef5d007SAfzal Mohammed #define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21) 553ef5d007SAfzal Mohammed #define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18) 563ef5d007SAfzal Mohammed #define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16) 573ef5d007SAfzal Mohammed #define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12) 583ef5d007SAfzal Mohammed #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1) 593ef5d007SAfzal Mohammed #define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10) 603ef5d007SAfzal Mohammed #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0) 613ef5d007SAfzal Mohammed #define GPMC_CONFIG1_MUXADDDATA (1 << 9) 623ef5d007SAfzal Mohammed #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4) 633ef5d007SAfzal Mohammed #define GPMC_CONFIG1_FCLK_DIV(val) (val & 3) 643ef5d007SAfzal Mohammed #define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1)) 653ef5d007SAfzal Mohammed #define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2)) 663ef5d007SAfzal Mohammed #define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3)) 673ef5d007SAfzal Mohammed #define GPMC_CONFIG7_CSVALID (1 << 6) 683ef5d007SAfzal Mohammed 693ef5d007SAfzal Mohammed #define GPMC_DEVICETYPE_NOR 0 703ef5d007SAfzal Mohammed #define GPMC_DEVICETYPE_NAND 2 713ef5d007SAfzal Mohammed #define GPMC_CONFIG_WRITEPROTECT 0x00000010 723ef5d007SAfzal Mohammed #define WR_RD_PIN_MONITORING 0x00600000 733ef5d007SAfzal Mohammed #define GPMC_IRQ_FIFOEVENTENABLE 0x01 743ef5d007SAfzal Mohammed #define GPMC_IRQ_COUNT_EVENT 0x02 753ef5d007SAfzal Mohammed 763ef5d007SAfzal Mohammed 773ef5d007SAfzal Mohammed /* 783ef5d007SAfzal Mohammed * Note that all values in this struct are in nanoseconds except sync_clk 793ef5d007SAfzal Mohammed * (which is in picoseconds), while the register values are in gpmc_fck cycles. 803ef5d007SAfzal Mohammed */ 813ef5d007SAfzal Mohammed struct gpmc_timings { 823ef5d007SAfzal Mohammed /* Minimum clock period for synchronous mode (in picoseconds) */ 833ef5d007SAfzal Mohammed u32 sync_clk; 843ef5d007SAfzal Mohammed 853ef5d007SAfzal Mohammed /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */ 863ef5d007SAfzal Mohammed u16 cs_on; /* Assertion time */ 873ef5d007SAfzal Mohammed u16 cs_rd_off; /* Read deassertion time */ 883ef5d007SAfzal Mohammed u16 cs_wr_off; /* Write deassertion time */ 893ef5d007SAfzal Mohammed 903ef5d007SAfzal Mohammed /* ADV signal timings corresponding to GPMC_CONFIG3 */ 913ef5d007SAfzal Mohammed u16 adv_on; /* Assertion time */ 923ef5d007SAfzal Mohammed u16 adv_rd_off; /* Read deassertion time */ 933ef5d007SAfzal Mohammed u16 adv_wr_off; /* Write deassertion time */ 943ef5d007SAfzal Mohammed 953ef5d007SAfzal Mohammed /* WE signals timings corresponding to GPMC_CONFIG4 */ 963ef5d007SAfzal Mohammed u16 we_on; /* WE assertion time */ 973ef5d007SAfzal Mohammed u16 we_off; /* WE deassertion time */ 983ef5d007SAfzal Mohammed 993ef5d007SAfzal Mohammed /* OE signals timings corresponding to GPMC_CONFIG4 */ 1003ef5d007SAfzal Mohammed u16 oe_on; /* OE assertion time */ 1013ef5d007SAfzal Mohammed u16 oe_off; /* OE deassertion time */ 1023ef5d007SAfzal Mohammed 1033ef5d007SAfzal Mohammed /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */ 1043ef5d007SAfzal Mohammed u16 page_burst_access; /* Multiple access word delay */ 1053ef5d007SAfzal Mohammed u16 access; /* Start-cycle to first data valid delay */ 1063ef5d007SAfzal Mohammed u16 rd_cycle; /* Total read cycle time */ 1073ef5d007SAfzal Mohammed u16 wr_cycle; /* Total write cycle time */ 1083ef5d007SAfzal Mohammed 1093ef5d007SAfzal Mohammed /* The following are only on OMAP3430 */ 1103ef5d007SAfzal Mohammed u16 wr_access; /* WRACCESSTIME */ 1113ef5d007SAfzal Mohammed u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */ 1123ef5d007SAfzal Mohammed }; 1133ef5d007SAfzal Mohammed 1143ef5d007SAfzal Mohammed extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs); 1153ef5d007SAfzal Mohammed extern int gpmc_get_client_irq(unsigned irq_config); 1163ef5d007SAfzal Mohammed 1173ef5d007SAfzal Mohammed extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns); 1183ef5d007SAfzal Mohammed extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps); 1193ef5d007SAfzal Mohammed extern unsigned int gpmc_ticks_to_ns(unsigned int ticks); 1203ef5d007SAfzal Mohammed extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns); 1213ef5d007SAfzal Mohammed extern unsigned long gpmc_get_fclk_period(void); 1223ef5d007SAfzal Mohammed 1233ef5d007SAfzal Mohammed extern void gpmc_cs_write_reg(int cs, int idx, u32 val); 1243ef5d007SAfzal Mohammed extern u32 gpmc_cs_read_reg(int cs, int idx); 1253ef5d007SAfzal Mohammed extern int gpmc_calc_divider(unsigned int sync_clk); 1263ef5d007SAfzal Mohammed extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t); 1273ef5d007SAfzal Mohammed extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base); 1283ef5d007SAfzal Mohammed extern void gpmc_cs_free(int cs); 1293ef5d007SAfzal Mohammed extern int gpmc_cs_set_reserved(int cs, int reserved); 1303ef5d007SAfzal Mohammed extern int gpmc_cs_reserved(int cs); 1313ef5d007SAfzal Mohammed extern void omap3_gpmc_save_context(void); 1323ef5d007SAfzal Mohammed extern void omap3_gpmc_restore_context(void); 1333ef5d007SAfzal Mohammed extern int gpmc_cs_configure(int cs, int cmd, int wval); 1343ef5d007SAfzal Mohammed 1353ef5d007SAfzal Mohammed #endif 136