1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * OMAP2+ DMA driver 4 * 5 * Copyright (C) 2003 - 2008 Nokia Corporation 6 * Author: Juha Yrjölä <juha.yrjola@nokia.com> 7 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com> 8 * Graphics DMA and LCD DMA graphics tranformations 9 * by Imre Deak <imre.deak@nokia.com> 10 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc. 11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc. 12 * 13 * Copyright (C) 2009 Texas Instruments 14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 15 * 16 * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/ 17 * Converted DMA library into platform driver 18 * - G, Manjunath Kondaiah <manjugk@ti.com> 19 */ 20 21 #include <linux/err.h> 22 #include <linux/io.h> 23 #include <linux/slab.h> 24 #include <linux/module.h> 25 #include <linux/init.h> 26 #include <linux/device.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/dmaengine.h> 29 #include <linux/of.h> 30 #include <linux/omap-dma.h> 31 32 #include "soc.h" 33 34 static const struct omap_dma_reg reg_map[] = { 35 [REVISION] = { 0x0000, 0x00, OMAP_DMA_REG_32BIT }, 36 [GCR] = { 0x0078, 0x00, OMAP_DMA_REG_32BIT }, 37 [IRQSTATUS_L0] = { 0x0008, 0x00, OMAP_DMA_REG_32BIT }, 38 [IRQSTATUS_L1] = { 0x000c, 0x00, OMAP_DMA_REG_32BIT }, 39 [IRQSTATUS_L2] = { 0x0010, 0x00, OMAP_DMA_REG_32BIT }, 40 [IRQSTATUS_L3] = { 0x0014, 0x00, OMAP_DMA_REG_32BIT }, 41 [IRQENABLE_L0] = { 0x0018, 0x00, OMAP_DMA_REG_32BIT }, 42 [IRQENABLE_L1] = { 0x001c, 0x00, OMAP_DMA_REG_32BIT }, 43 [IRQENABLE_L2] = { 0x0020, 0x00, OMAP_DMA_REG_32BIT }, 44 [IRQENABLE_L3] = { 0x0024, 0x00, OMAP_DMA_REG_32BIT }, 45 [SYSSTATUS] = { 0x0028, 0x00, OMAP_DMA_REG_32BIT }, 46 [OCP_SYSCONFIG] = { 0x002c, 0x00, OMAP_DMA_REG_32BIT }, 47 [CAPS_0] = { 0x0064, 0x00, OMAP_DMA_REG_32BIT }, 48 [CAPS_2] = { 0x006c, 0x00, OMAP_DMA_REG_32BIT }, 49 [CAPS_3] = { 0x0070, 0x00, OMAP_DMA_REG_32BIT }, 50 [CAPS_4] = { 0x0074, 0x00, OMAP_DMA_REG_32BIT }, 51 52 /* Common register offsets */ 53 [CCR] = { 0x0080, 0x60, OMAP_DMA_REG_32BIT }, 54 [CLNK_CTRL] = { 0x0084, 0x60, OMAP_DMA_REG_32BIT }, 55 [CICR] = { 0x0088, 0x60, OMAP_DMA_REG_32BIT }, 56 [CSR] = { 0x008c, 0x60, OMAP_DMA_REG_32BIT }, 57 [CSDP] = { 0x0090, 0x60, OMAP_DMA_REG_32BIT }, 58 [CEN] = { 0x0094, 0x60, OMAP_DMA_REG_32BIT }, 59 [CFN] = { 0x0098, 0x60, OMAP_DMA_REG_32BIT }, 60 [CSEI] = { 0x00a4, 0x60, OMAP_DMA_REG_32BIT }, 61 [CSFI] = { 0x00a8, 0x60, OMAP_DMA_REG_32BIT }, 62 [CDEI] = { 0x00ac, 0x60, OMAP_DMA_REG_32BIT }, 63 [CDFI] = { 0x00b0, 0x60, OMAP_DMA_REG_32BIT }, 64 [CSAC] = { 0x00b4, 0x60, OMAP_DMA_REG_32BIT }, 65 [CDAC] = { 0x00b8, 0x60, OMAP_DMA_REG_32BIT }, 66 67 /* Channel specific register offsets */ 68 [CSSA] = { 0x009c, 0x60, OMAP_DMA_REG_32BIT }, 69 [CDSA] = { 0x00a0, 0x60, OMAP_DMA_REG_32BIT }, 70 [CCEN] = { 0x00bc, 0x60, OMAP_DMA_REG_32BIT }, 71 [CCFN] = { 0x00c0, 0x60, OMAP_DMA_REG_32BIT }, 72 [COLOR] = { 0x00c4, 0x60, OMAP_DMA_REG_32BIT }, 73 74 /* OMAP4 specific registers */ 75 [CDP] = { 0x00d0, 0x60, OMAP_DMA_REG_32BIT }, 76 [CNDP] = { 0x00d4, 0x60, OMAP_DMA_REG_32BIT }, 77 [CCDN] = { 0x00d8, 0x60, OMAP_DMA_REG_32BIT }, 78 }; 79 80 static unsigned configure_dma_errata(void) 81 { 82 unsigned errata = 0; 83 84 /* 85 * Errata applicable for OMAP2430ES1.0 and all omap2420 86 * 87 * I. 88 * Erratum ID: Not Available 89 * Inter Frame DMA buffering issue DMA will wrongly 90 * buffer elements if packing and bursting is enabled. This might 91 * result in data gets stalled in FIFO at the end of the block. 92 * Workaround: DMA channels must have BUFFERING_DISABLED bit set to 93 * guarantee no data will stay in the DMA FIFO in case inter frame 94 * buffering occurs 95 * 96 * II. 97 * Erratum ID: Not Available 98 * DMA may hang when several channels are used in parallel 99 * In the following configuration, DMA channel hanging can occur: 100 * a. Channel i, hardware synchronized, is enabled 101 * b. Another channel (Channel x), software synchronized, is enabled. 102 * c. Channel i is disabled before end of transfer 103 * d. Channel i is reenabled. 104 * e. Steps 1 to 4 are repeated a certain number of times. 105 * f. A third channel (Channel y), software synchronized, is enabled. 106 * Channel x and Channel y may hang immediately after step 'f'. 107 * Workaround: 108 * For any channel used - make sure NextLCH_ID is set to the value j. 109 */ 110 if (cpu_is_omap2420() || (cpu_is_omap2430() && 111 (omap_type() == OMAP2430_REV_ES1_0))) { 112 113 SET_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING); 114 SET_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS); 115 } 116 117 /* 118 * Erratum ID: i378: OMAP2+: sDMA Channel is not disabled 119 * after a transaction error. 120 * Workaround: SW should explicitely disable the channel. 121 */ 122 if (cpu_class_is_omap2()) 123 SET_DMA_ERRATA(DMA_ERRATA_i378); 124 125 /* 126 * Erratum ID: i541: sDMA FIFO draining does not finish 127 * If sDMA channel is disabled on the fly, sDMA enters standby even 128 * through FIFO Drain is still in progress 129 * Workaround: Put sDMA in NoStandby more before a logical channel is 130 * disabled, then put it back to SmartStandby right after the channel 131 * finishes FIFO draining. 132 */ 133 if (cpu_is_omap34xx()) 134 SET_DMA_ERRATA(DMA_ERRATA_i541); 135 136 /* 137 * Erratum ID: i88 : Special programming model needed to disable DMA 138 * before end of block. 139 * Workaround: software must ensure that the DMA is configured in No 140 * Standby mode(DMAx_OCP_SYSCONFIG.MIDLEMODE = "01") 141 */ 142 if (omap_type() == OMAP3430_REV_ES1_0) 143 SET_DMA_ERRATA(DMA_ERRATA_i88); 144 145 /* 146 * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is 147 * read before the DMA controller finished disabling the channel. 148 */ 149 SET_DMA_ERRATA(DMA_ERRATA_3_3); 150 151 /* 152 * Erratum ID: Not Available 153 * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared 154 * after secure sram context save and restore. 155 * Work around: Hence we need to manually clear those IRQs to avoid 156 * spurious interrupts. This affects only secure devices. 157 */ 158 if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) 159 SET_DMA_ERRATA(DMA_ROMCODE_BUG); 160 161 return errata; 162 } 163 164 static const struct dma_slave_map omap24xx_sdma_dt_map[] = { 165 /* external DMA requests when tusb6010 is used */ 166 { "musb-hdrc.1.auto", "dmareq0", SDMA_FILTER_PARAM(2) }, 167 { "musb-hdrc.1.auto", "dmareq1", SDMA_FILTER_PARAM(3) }, 168 { "musb-hdrc.1.auto", "dmareq2", SDMA_FILTER_PARAM(14) }, /* OMAP2420 only */ 169 { "musb-hdrc.1.auto", "dmareq3", SDMA_FILTER_PARAM(15) }, /* OMAP2420 only */ 170 { "musb-hdrc.1.auto", "dmareq4", SDMA_FILTER_PARAM(16) }, /* OMAP2420 only */ 171 { "musb-hdrc.1.auto", "dmareq5", SDMA_FILTER_PARAM(64) }, /* OMAP2420 only */ 172 }; 173 174 static struct omap_dma_dev_attr dma_attr = { 175 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | 176 IS_CSSA_32 | IS_CDSA_32, 177 .lch_count = 32, 178 }; 179 180 struct omap_system_dma_plat_info dma_plat_info = { 181 .reg_map = reg_map, 182 .channel_stride = 0x60, 183 .dma_attr = &dma_attr, 184 }; 185 186 /* One time initializations */ 187 static int __init omap2_system_dma_init(void) 188 { 189 dma_plat_info.errata = configure_dma_errata(); 190 191 if (soc_is_omap24xx()) { 192 /* DMA slave map for drivers not yet converted to DT */ 193 dma_plat_info.slave_map = omap24xx_sdma_dt_map; 194 dma_plat_info.slavecnt = ARRAY_SIZE(omap24xx_sdma_dt_map); 195 } 196 197 if (!soc_is_omap242x()) 198 dma_attr.dev_caps |= IS_RW_PRIORITY; 199 200 if (soc_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) 201 dma_attr.dev_caps |= HS_CHANNELS_RESERVED; 202 203 return 0; 204 } 205 omap_arch_initcall(omap2_system_dma_init); 206