1 /* 2 * OMAP2+ DMA driver 3 * 4 * Copyright (C) 2003 - 2008 Nokia Corporation 5 * Author: Juha Yrjölä <juha.yrjola@nokia.com> 6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com> 7 * Graphics DMA and LCD DMA graphics tranformations 8 * by Imre Deak <imre.deak@nokia.com> 9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc. 10 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc. 11 * 12 * Copyright (C) 2009 Texas Instruments 13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 14 * 15 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 16 * Converted DMA library into platform driver 17 * - G, Manjunath Kondaiah <manjugk@ti.com> 18 * 19 * This program is free software; you can redistribute it and/or modify 20 * it under the terms of the GNU General Public License version 2 as 21 * published by the Free Software Foundation. 22 */ 23 24 #include <linux/err.h> 25 #include <linux/io.h> 26 #include <linux/slab.h> 27 #include <linux/module.h> 28 #include <linux/init.h> 29 #include <linux/device.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/dmaengine.h> 32 #include <linux/of.h> 33 #include <linux/omap-dma.h> 34 35 #include "soc.h" 36 #include "omap_hwmod.h" 37 #include "omap_device.h" 38 39 static enum omap_reg_offsets dma_common_ch_end; 40 41 static const struct omap_dma_reg reg_map[] = { 42 [REVISION] = { 0x0000, 0x00, OMAP_DMA_REG_32BIT }, 43 [GCR] = { 0x0078, 0x00, OMAP_DMA_REG_32BIT }, 44 [IRQSTATUS_L0] = { 0x0008, 0x00, OMAP_DMA_REG_32BIT }, 45 [IRQSTATUS_L1] = { 0x000c, 0x00, OMAP_DMA_REG_32BIT }, 46 [IRQSTATUS_L2] = { 0x0010, 0x00, OMAP_DMA_REG_32BIT }, 47 [IRQSTATUS_L3] = { 0x0014, 0x00, OMAP_DMA_REG_32BIT }, 48 [IRQENABLE_L0] = { 0x0018, 0x00, OMAP_DMA_REG_32BIT }, 49 [IRQENABLE_L1] = { 0x001c, 0x00, OMAP_DMA_REG_32BIT }, 50 [IRQENABLE_L2] = { 0x0020, 0x00, OMAP_DMA_REG_32BIT }, 51 [IRQENABLE_L3] = { 0x0024, 0x00, OMAP_DMA_REG_32BIT }, 52 [SYSSTATUS] = { 0x0028, 0x00, OMAP_DMA_REG_32BIT }, 53 [OCP_SYSCONFIG] = { 0x002c, 0x00, OMAP_DMA_REG_32BIT }, 54 [CAPS_0] = { 0x0064, 0x00, OMAP_DMA_REG_32BIT }, 55 [CAPS_2] = { 0x006c, 0x00, OMAP_DMA_REG_32BIT }, 56 [CAPS_3] = { 0x0070, 0x00, OMAP_DMA_REG_32BIT }, 57 [CAPS_4] = { 0x0074, 0x00, OMAP_DMA_REG_32BIT }, 58 59 /* Common register offsets */ 60 [CCR] = { 0x0080, 0x60, OMAP_DMA_REG_32BIT }, 61 [CLNK_CTRL] = { 0x0084, 0x60, OMAP_DMA_REG_32BIT }, 62 [CICR] = { 0x0088, 0x60, OMAP_DMA_REG_32BIT }, 63 [CSR] = { 0x008c, 0x60, OMAP_DMA_REG_32BIT }, 64 [CSDP] = { 0x0090, 0x60, OMAP_DMA_REG_32BIT }, 65 [CEN] = { 0x0094, 0x60, OMAP_DMA_REG_32BIT }, 66 [CFN] = { 0x0098, 0x60, OMAP_DMA_REG_32BIT }, 67 [CSEI] = { 0x00a4, 0x60, OMAP_DMA_REG_32BIT }, 68 [CSFI] = { 0x00a8, 0x60, OMAP_DMA_REG_32BIT }, 69 [CDEI] = { 0x00ac, 0x60, OMAP_DMA_REG_32BIT }, 70 [CDFI] = { 0x00b0, 0x60, OMAP_DMA_REG_32BIT }, 71 [CSAC] = { 0x00b4, 0x60, OMAP_DMA_REG_32BIT }, 72 [CDAC] = { 0x00b8, 0x60, OMAP_DMA_REG_32BIT }, 73 74 /* Channel specific register offsets */ 75 [CSSA] = { 0x009c, 0x60, OMAP_DMA_REG_32BIT }, 76 [CDSA] = { 0x00a0, 0x60, OMAP_DMA_REG_32BIT }, 77 [CCEN] = { 0x00bc, 0x60, OMAP_DMA_REG_32BIT }, 78 [CCFN] = { 0x00c0, 0x60, OMAP_DMA_REG_32BIT }, 79 [COLOR] = { 0x00c4, 0x60, OMAP_DMA_REG_32BIT }, 80 81 /* OMAP4 specific registers */ 82 [CDP] = { 0x00d0, 0x60, OMAP_DMA_REG_32BIT }, 83 [CNDP] = { 0x00d4, 0x60, OMAP_DMA_REG_32BIT }, 84 [CCDN] = { 0x00d8, 0x60, OMAP_DMA_REG_32BIT }, 85 }; 86 87 static void __iomem *dma_base; 88 static inline void dma_write(u32 val, int reg, int lch) 89 { 90 void __iomem *addr = dma_base; 91 92 addr += reg_map[reg].offset; 93 addr += reg_map[reg].stride * lch; 94 95 writel_relaxed(val, addr); 96 } 97 98 static inline u32 dma_read(int reg, int lch) 99 { 100 void __iomem *addr = dma_base; 101 102 addr += reg_map[reg].offset; 103 addr += reg_map[reg].stride * lch; 104 105 return readl_relaxed(addr); 106 } 107 108 static void omap2_clear_dma(int lch) 109 { 110 int i; 111 112 for (i = CSDP; i <= dma_common_ch_end; i += 1) 113 dma_write(0, i, lch); 114 } 115 116 static void omap2_show_dma_caps(void) 117 { 118 u8 revision = dma_read(REVISION, 0) & 0xff; 119 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n", 120 revision >> 4, revision & 0xf); 121 } 122 123 static unsigned configure_dma_errata(void) 124 { 125 unsigned errata = 0; 126 127 /* 128 * Errata applicable for OMAP2430ES1.0 and all omap2420 129 * 130 * I. 131 * Erratum ID: Not Available 132 * Inter Frame DMA buffering issue DMA will wrongly 133 * buffer elements if packing and bursting is enabled. This might 134 * result in data gets stalled in FIFO at the end of the block. 135 * Workaround: DMA channels must have BUFFERING_DISABLED bit set to 136 * guarantee no data will stay in the DMA FIFO in case inter frame 137 * buffering occurs 138 * 139 * II. 140 * Erratum ID: Not Available 141 * DMA may hang when several channels are used in parallel 142 * In the following configuration, DMA channel hanging can occur: 143 * a. Channel i, hardware synchronized, is enabled 144 * b. Another channel (Channel x), software synchronized, is enabled. 145 * c. Channel i is disabled before end of transfer 146 * d. Channel i is reenabled. 147 * e. Steps 1 to 4 are repeated a certain number of times. 148 * f. A third channel (Channel y), software synchronized, is enabled. 149 * Channel x and Channel y may hang immediately after step 'f'. 150 * Workaround: 151 * For any channel used - make sure NextLCH_ID is set to the value j. 152 */ 153 if (cpu_is_omap2420() || (cpu_is_omap2430() && 154 (omap_type() == OMAP2430_REV_ES1_0))) { 155 156 SET_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING); 157 SET_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS); 158 } 159 160 /* 161 * Erratum ID: i378: OMAP2+: sDMA Channel is not disabled 162 * after a transaction error. 163 * Workaround: SW should explicitely disable the channel. 164 */ 165 if (cpu_class_is_omap2()) 166 SET_DMA_ERRATA(DMA_ERRATA_i378); 167 168 /* 169 * Erratum ID: i541: sDMA FIFO draining does not finish 170 * If sDMA channel is disabled on the fly, sDMA enters standby even 171 * through FIFO Drain is still in progress 172 * Workaround: Put sDMA in NoStandby more before a logical channel is 173 * disabled, then put it back to SmartStandby right after the channel 174 * finishes FIFO draining. 175 */ 176 if (cpu_is_omap34xx()) 177 SET_DMA_ERRATA(DMA_ERRATA_i541); 178 179 /* 180 * Erratum ID: i88 : Special programming model needed to disable DMA 181 * before end of block. 182 * Workaround: software must ensure that the DMA is configured in No 183 * Standby mode(DMAx_OCP_SYSCONFIG.MIDLEMODE = "01") 184 */ 185 if (omap_type() == OMAP3430_REV_ES1_0) 186 SET_DMA_ERRATA(DMA_ERRATA_i88); 187 188 /* 189 * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is 190 * read before the DMA controller finished disabling the channel. 191 */ 192 SET_DMA_ERRATA(DMA_ERRATA_3_3); 193 194 /* 195 * Erratum ID: Not Available 196 * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared 197 * after secure sram context save and restore. 198 * Work around: Hence we need to manually clear those IRQs to avoid 199 * spurious interrupts. This affects only secure devices. 200 */ 201 if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) 202 SET_DMA_ERRATA(DMA_ROMCODE_BUG); 203 204 return errata; 205 } 206 207 static const struct dma_slave_map omap24xx_sdma_dt_map[] = { 208 /* external DMA requests when tusb6010 is used */ 209 { "musb-hdrc.1.auto", "dmareq0", SDMA_FILTER_PARAM(2) }, 210 { "musb-hdrc.1.auto", "dmareq1", SDMA_FILTER_PARAM(3) }, 211 { "musb-hdrc.1.auto", "dmareq2", SDMA_FILTER_PARAM(14) }, /* OMAP2420 only */ 212 { "musb-hdrc.1.auto", "dmareq3", SDMA_FILTER_PARAM(15) }, /* OMAP2420 only */ 213 { "musb-hdrc.1.auto", "dmareq4", SDMA_FILTER_PARAM(16) }, /* OMAP2420 only */ 214 { "musb-hdrc.1.auto", "dmareq5", SDMA_FILTER_PARAM(64) }, /* OMAP2420 only */ 215 }; 216 217 static struct omap_system_dma_plat_info dma_plat_info __initdata = { 218 .reg_map = reg_map, 219 .channel_stride = 0x60, 220 .show_dma_caps = omap2_show_dma_caps, 221 .clear_dma = omap2_clear_dma, 222 .dma_write = dma_write, 223 .dma_read = dma_read, 224 }; 225 226 static struct platform_device_info omap_dma_dev_info __initdata = { 227 .name = "omap-dma-engine", 228 .id = -1, 229 .dma_mask = DMA_BIT_MASK(32), 230 }; 231 232 /* One time initializations */ 233 static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused) 234 { 235 struct platform_device *pdev; 236 struct omap_system_dma_plat_info p; 237 struct omap_dma_dev_attr *d; 238 struct resource *mem; 239 char *name = "omap_dma_system"; 240 241 p = dma_plat_info; 242 p.dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr; 243 p.errata = configure_dma_errata(); 244 245 if (soc_is_omap24xx()) { 246 /* DMA slave map for drivers not yet converted to DT */ 247 p.slave_map = omap24xx_sdma_dt_map; 248 p.slavecnt = ARRAY_SIZE(omap24xx_sdma_dt_map); 249 } 250 251 pdev = omap_device_build(name, 0, oh, &p, sizeof(p)); 252 if (IS_ERR(pdev)) { 253 pr_err("%s: Can't build omap_device for %s:%s.\n", 254 __func__, name, oh->name); 255 return PTR_ERR(pdev); 256 } 257 258 omap_dma_dev_info.res = pdev->resource; 259 omap_dma_dev_info.num_res = pdev->num_resources; 260 261 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 262 if (!mem) { 263 dev_err(&pdev->dev, "%s: no mem resource\n", __func__); 264 return -EINVAL; 265 } 266 267 dma_base = ioremap(mem->start, resource_size(mem)); 268 if (!dma_base) { 269 dev_err(&pdev->dev, "%s: ioremap fail\n", __func__); 270 return -ENOMEM; 271 } 272 273 d = oh->dev_attr; 274 275 if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) 276 d->dev_caps |= HS_CHANNELS_RESERVED; 277 278 if (platform_get_irq_byname(pdev, "0") < 0) 279 d->dev_caps |= DMA_ENGINE_HANDLE_IRQ; 280 281 /* Check the capabilities register for descriptor loading feature */ 282 if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS) 283 dma_common_ch_end = CCDN; 284 else 285 dma_common_ch_end = CCFN; 286 287 return 0; 288 } 289 290 static int __init omap2_system_dma_init(void) 291 { 292 return omap_hwmod_for_each_by_class("dma", 293 omap2_system_dma_init_dev, NULL); 294 } 295 omap_arch_initcall(omap2_system_dma_init); 296