1 /* 2 * OMAP2plus display device setup / initialization. 3 * 4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 5 * Senthilvadivu Guruswamy 6 * Sumit Semwal 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 13 * kind, whether express or implied; without even the implied warranty 14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/string.h> 19 #include <linux/kernel.h> 20 #include <linux/init.h> 21 #include <linux/platform_device.h> 22 #include <linux/io.h> 23 #include <linux/clk.h> 24 #include <linux/err.h> 25 #include <linux/delay.h> 26 27 #include <video/omapdss.h> 28 #include <plat/omap_hwmod.h> 29 #include <plat/omap_device.h> 30 #include <plat/omap-pm.h> 31 #include "common.h" 32 33 #include "mux.h" 34 #include "control.h" 35 #include "display.h" 36 37 #define DISPC_CONTROL 0x0040 38 #define DISPC_CONTROL2 0x0238 39 #define DISPC_IRQSTATUS 0x0018 40 41 #define DSS_SYSCONFIG 0x10 42 #define DSS_SYSSTATUS 0x14 43 #define DSS_CONTROL 0x40 44 #define DSS_SDI_CONTROL 0x44 45 #define DSS_PLL_CONTROL 0x48 46 47 #define LCD_EN_MASK (0x1 << 0) 48 #define DIGIT_EN_MASK (0x1 << 1) 49 50 #define FRAMEDONE_IRQ_SHIFT 0 51 #define EVSYNC_EVEN_IRQ_SHIFT 2 52 #define EVSYNC_ODD_IRQ_SHIFT 3 53 #define FRAMEDONE2_IRQ_SHIFT 22 54 #define FRAMEDONETV_IRQ_SHIFT 24 55 56 /* 57 * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC 58 * reset before deciding that something has gone wrong 59 */ 60 #define FRAMEDONE_IRQ_TIMEOUT 100 61 62 static struct platform_device omap_display_device = { 63 .name = "omapdss", 64 .id = -1, 65 .dev = { 66 .platform_data = NULL, 67 }, 68 }; 69 70 struct omap_dss_hwmod_data { 71 const char *oh_name; 72 const char *dev_name; 73 const int id; 74 }; 75 76 static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initdata = { 77 { "dss_core", "omapdss_dss", -1 }, 78 { "dss_dispc", "omapdss_dispc", -1 }, 79 { "dss_rfbi", "omapdss_rfbi", -1 }, 80 { "dss_venc", "omapdss_venc", -1 }, 81 }; 82 83 static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = { 84 { "dss_core", "omapdss_dss", -1 }, 85 { "dss_dispc", "omapdss_dispc", -1 }, 86 { "dss_rfbi", "omapdss_rfbi", -1 }, 87 { "dss_venc", "omapdss_venc", -1 }, 88 { "dss_dsi1", "omapdss_dsi", 0 }, 89 }; 90 91 static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initdata = { 92 { "dss_core", "omapdss_dss", -1 }, 93 { "dss_dispc", "omapdss_dispc", -1 }, 94 { "dss_rfbi", "omapdss_rfbi", -1 }, 95 { "dss_venc", "omapdss_venc", -1 }, 96 { "dss_dsi1", "omapdss_dsi", 0 }, 97 { "dss_dsi2", "omapdss_dsi", 1 }, 98 { "dss_hdmi", "omapdss_hdmi", -1 }, 99 }; 100 101 static void omap4_hdmi_mux_pads(enum omap_hdmi_flags flags) 102 { 103 u32 reg; 104 u16 control_i2c_1; 105 106 omap_mux_init_signal("hdmi_cec", 107 OMAP_PIN_INPUT_PULLUP); 108 omap_mux_init_signal("hdmi_ddc_scl", 109 OMAP_PIN_INPUT_PULLUP); 110 omap_mux_init_signal("hdmi_ddc_sda", 111 OMAP_PIN_INPUT_PULLUP); 112 113 /* 114 * CONTROL_I2C_1: HDMI_DDC_SDA_PULLUPRESX (bit 28) and 115 * HDMI_DDC_SCL_PULLUPRESX (bit 24) are set to disable 116 * internal pull up resistor. 117 */ 118 if (flags & OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP) { 119 control_i2c_1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1; 120 reg = omap4_ctrl_pad_readl(control_i2c_1); 121 reg |= (OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK | 122 OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK); 123 omap4_ctrl_pad_writel(reg, control_i2c_1); 124 } 125 } 126 127 static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes) 128 { 129 u32 enable_mask, enable_shift; 130 u32 pipd_mask, pipd_shift; 131 u32 reg; 132 133 if (dsi_id == 0) { 134 enable_mask = OMAP4_DSI1_LANEENABLE_MASK; 135 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT; 136 pipd_mask = OMAP4_DSI1_PIPD_MASK; 137 pipd_shift = OMAP4_DSI1_PIPD_SHIFT; 138 } else if (dsi_id == 1) { 139 enable_mask = OMAP4_DSI2_LANEENABLE_MASK; 140 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT; 141 pipd_mask = OMAP4_DSI2_PIPD_MASK; 142 pipd_shift = OMAP4_DSI2_PIPD_SHIFT; 143 } else { 144 return -ENODEV; 145 } 146 147 reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY); 148 149 reg &= ~enable_mask; 150 reg &= ~pipd_mask; 151 152 reg |= (lanes << enable_shift) & enable_mask; 153 reg |= (lanes << pipd_shift) & pipd_mask; 154 155 omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY); 156 157 return 0; 158 } 159 160 int omap_hdmi_init(enum omap_hdmi_flags flags) 161 { 162 if (cpu_is_omap44xx()) 163 omap4_hdmi_mux_pads(flags); 164 165 return 0; 166 } 167 168 static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask) 169 { 170 if (cpu_is_omap44xx()) 171 return omap4_dsi_mux_pads(dsi_id, lane_mask); 172 173 return 0; 174 } 175 176 static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask) 177 { 178 if (cpu_is_omap44xx()) 179 omap4_dsi_mux_pads(dsi_id, 0); 180 } 181 182 int __init omap_display_init(struct omap_dss_board_info *board_data) 183 { 184 int r = 0; 185 struct omap_hwmod *oh; 186 struct platform_device *pdev; 187 int i, oh_count; 188 struct omap_display_platform_data pdata; 189 const struct omap_dss_hwmod_data *curr_dss_hwmod; 190 191 memset(&pdata, 0, sizeof(pdata)); 192 193 if (cpu_is_omap24xx()) { 194 curr_dss_hwmod = omap2_dss_hwmod_data; 195 oh_count = ARRAY_SIZE(omap2_dss_hwmod_data); 196 } else if (cpu_is_omap34xx()) { 197 curr_dss_hwmod = omap3_dss_hwmod_data; 198 oh_count = ARRAY_SIZE(omap3_dss_hwmod_data); 199 } else { 200 curr_dss_hwmod = omap4_dss_hwmod_data; 201 oh_count = ARRAY_SIZE(omap4_dss_hwmod_data); 202 } 203 204 if (board_data->dsi_enable_pads == NULL) 205 board_data->dsi_enable_pads = omap_dsi_enable_pads; 206 if (board_data->dsi_disable_pads == NULL) 207 board_data->dsi_disable_pads = omap_dsi_disable_pads; 208 209 pdata.board_data = board_data; 210 pdata.board_data->get_context_loss_count = 211 omap_pm_get_dev_context_loss_count; 212 213 for (i = 0; i < oh_count; i++) { 214 oh = omap_hwmod_lookup(curr_dss_hwmod[i].oh_name); 215 if (!oh) { 216 pr_err("Could not look up %s\n", 217 curr_dss_hwmod[i].oh_name); 218 return -ENODEV; 219 } 220 221 pdev = omap_device_build(curr_dss_hwmod[i].dev_name, 222 curr_dss_hwmod[i].id, oh, &pdata, 223 sizeof(struct omap_display_platform_data), 224 NULL, 0, 0); 225 226 if (WARN((IS_ERR(pdev)), "Could not build omap_device for %s\n", 227 curr_dss_hwmod[i].oh_name)) 228 return -ENODEV; 229 } 230 omap_display_device.dev.platform_data = board_data; 231 232 r = platform_device_register(&omap_display_device); 233 if (r < 0) 234 printk(KERN_ERR "Unable to register OMAP-Display device\n"); 235 236 return r; 237 } 238 239 static void dispc_disable_outputs(void) 240 { 241 u32 v, irq_mask = 0; 242 bool lcd_en, digit_en, lcd2_en = false; 243 int i; 244 struct omap_dss_dispc_dev_attr *da; 245 struct omap_hwmod *oh; 246 247 oh = omap_hwmod_lookup("dss_dispc"); 248 if (!oh) { 249 WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n"); 250 return; 251 } 252 253 if (!oh->dev_attr) { 254 pr_err("display: could not disable outputs during reset due to missing dev_attr\n"); 255 return; 256 } 257 258 da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr; 259 260 /* store value of LCDENABLE and DIGITENABLE bits */ 261 v = omap_hwmod_read(oh, DISPC_CONTROL); 262 lcd_en = v & LCD_EN_MASK; 263 digit_en = v & DIGIT_EN_MASK; 264 265 /* store value of LCDENABLE for LCD2 */ 266 if (da->manager_count > 2) { 267 v = omap_hwmod_read(oh, DISPC_CONTROL2); 268 lcd2_en = v & LCD_EN_MASK; 269 } 270 271 if (!(lcd_en | digit_en | lcd2_en)) 272 return; /* no managers currently enabled */ 273 274 /* 275 * If any manager was enabled, we need to disable it before 276 * DSS clocks are disabled or DISPC module is reset 277 */ 278 if (lcd_en) 279 irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT; 280 281 if (digit_en) { 282 if (da->has_framedonetv_irq) { 283 irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT; 284 } else { 285 irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT | 286 1 << EVSYNC_ODD_IRQ_SHIFT; 287 } 288 } 289 290 if (lcd2_en) 291 irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT; 292 293 /* 294 * clear any previous FRAMEDONE, FRAMEDONETV, 295 * EVSYNC_EVEN/ODD or FRAMEDONE2 interrupts 296 */ 297 omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS); 298 299 /* disable LCD and TV managers */ 300 v = omap_hwmod_read(oh, DISPC_CONTROL); 301 v &= ~(LCD_EN_MASK | DIGIT_EN_MASK); 302 omap_hwmod_write(v, oh, DISPC_CONTROL); 303 304 /* disable LCD2 manager */ 305 if (da->manager_count > 2) { 306 v = omap_hwmod_read(oh, DISPC_CONTROL2); 307 v &= ~LCD_EN_MASK; 308 omap_hwmod_write(v, oh, DISPC_CONTROL2); 309 } 310 311 i = 0; 312 while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) != 313 irq_mask) { 314 i++; 315 if (i > FRAMEDONE_IRQ_TIMEOUT) { 316 pr_err("didn't get FRAMEDONE1/2 or TV interrupt\n"); 317 break; 318 } 319 mdelay(1); 320 } 321 } 322 323 #define MAX_MODULE_SOFTRESET_WAIT 10000 324 int omap_dss_reset(struct omap_hwmod *oh) 325 { 326 struct omap_hwmod_opt_clk *oc; 327 int c = 0; 328 int i, r; 329 330 if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) { 331 pr_err("dss_core: hwmod data doesn't contain reset data\n"); 332 return -EINVAL; 333 } 334 335 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) 336 if (oc->_clk) 337 clk_enable(oc->_clk); 338 339 dispc_disable_outputs(); 340 341 /* clear SDI registers */ 342 if (cpu_is_omap3430()) { 343 omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL); 344 omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL); 345 } 346 347 /* 348 * clear DSS_CONTROL register to switch DSS clock sources to 349 * PRCM clock, if any 350 */ 351 omap_hwmod_write(0x0, oh, DSS_CONTROL); 352 353 omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs) 354 & SYSS_RESETDONE_MASK), 355 MAX_MODULE_SOFTRESET_WAIT, c); 356 357 if (c == MAX_MODULE_SOFTRESET_WAIT) 358 pr_warning("dss_core: waiting for reset to finish failed\n"); 359 else 360 pr_debug("dss_core: softreset done\n"); 361 362 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) 363 if (oc->_clk) 364 clk_disable(oc->_clk); 365 366 r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0; 367 368 return r; 369 } 370